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2012-11-14mainboard/siemens/sitemp_g1p1: Fix CMOS checksum algorithm here, tooNico Huber
Some time ago our CMOS checksum algorithm was changed under the topic: Fix our CMOS checksum algorithm so it matches what /dev/nvram expects Here is another copy of the algorithm that had to be updated. Change-Id: I58659c7b8a89c89c76efdff405ee0620e7302277 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1852 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14Move HAVE_SMI_HANDLER from mainboards to chipsetsStefan Reinauer
Change-Id: Ibb6606fe3996e377181872a4544600f2d58c5439 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1834 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14VIA chipsets: fix compilation without real mode codeStefan Reinauer
The VIA chipsets CX700, VT8623 and VX800 required to be configured with real mode option rom code enabled. This patch fixes the issue and drops some unneeded header files. Change-Id: I0d8a3f8f99c2eacec7666f08f85b99f09c06af84 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1833 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14Tell CBMEM code about ACPI GNVS sectionStefan Reinauer
We moved GNVS to it's own section, but forgot to tell the cbmem code about it. This is purely cosmetical, but add it anyways. Change-Id: Icb3788c0325ea79cc1efff4a876412d07da7936e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1782 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14SMM: Fix save state searching for GSMIDuncan Laurie
The search for save state was comparing the entire RAX value when it needs to just operate on the bottom byte so it can find the GSMI command in bits 7:0 but not the extended command code in bits 15:8. Change-Id: I526c60e6b3732fa3680a17a4bed2a2ef23ccf94f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1774 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14SMM: Save the GNVS pointer when creating APCI tablesDuncan Laurie
At boot time when the ACPI tables are created and the location of GNVS is determined then save that address for resume time. This also sets the values of USB charging in S3/S5 to the expected default values for Stout/Butterfly that were not set correctly. Change-Id: I9b94b868aa6e81aced06c0262cc2697ad4faf1e6 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1768 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14SMM: Pass the ACPI GNVS pointer via state save mapDuncan Laurie
Instead of hijacking some random memory addresses to relay the GNVS pointer to SMM we can use EBX register during the write to APM_CNT register when the SMI is triggered. Change-Id: I79a89512c40353d72ad058cbf2e6a23a696945da Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1766 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14SMM: Avoid use of global variables in SMI handlerDuncan Laurie
Using global variables with the TSEG is a bad idea because they are not relocated properly right now. Instead make the variables static and add accessor functions for the rest of SMM to use. At the same time drop the tcg/smi1 pointers as they are not setup or ever used. (the debug output is added back in a subsequent commit) Change-Id: If0b2d47df4e482ead71bf713c1ef748da840073b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1764 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14SMM: Extract function for finding save state nodeDuncan Laurie
This is currently used by the ELOG GSMI interface but is a good way to pass data to SMM so move the current searching code to a separate function and make it a bit more versatile with the checks it does to find a match so it can be used in other situations. Change-Id: I5b6f92169f77c7707448ec38684cdd53c02fe0a5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1763 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14SMM: Restore GNVS pointer in the resume pathDuncan Laurie
The SMM GNVS pointer is normally updated only when the ACPI tables are created, which does not happen in the resume path. In order to restore this pointer it needs to be available at resume time. The method used to locate it at creation time cannot be used again as that magic signature is overwritten with the address itself. So a new CBMEM ID is added to store the 32bit address so it can be found again easily. A new function is defined to save this pointer in CBMEM which needs to be called when the ACPI tables are created in each mainboard when write_acpi_tables() is called. The cpu_index variable had to be renamed due to a conflict when cpu/cpu.h is added for the smm_setup_structures() prototype. Change-Id: Ic764ff54525e12b617c1dd8d6a3e5c4f547c3e6b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1765 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14Sandybridge: Set PEG clock gatingMarc Jones
If the PEI System Agent doesn't run PCIe initialization, the PEG clock gating will not be setup. Add the PEG clock gating when pei_data->pcie_init is 0. Change-Id: I7e31bcebd11feb4807aa29b528adf09fb013c3ce Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1827 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14Add PCIe init and NMode flag to PEI data structureStefan Reinauer
The IvyBridge reference code does some slow and extensive PCIe init that we do not need on Link. Hence, add a flag to disable/enable running that init code from coreboot. NMode was used during bringup. We'll switch the setting back to auto, to let MRC decide the right thing. Change-Id: Ia989bb9ea079aadfeb41dc3029b7c2c623e84760 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1826 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14Add ddr3lv_support flag to pei_data structureDuncan Laurie
This will enable DDR3 1.35V support for memory training in the reference code. It requires the board to be setup for 1.35V with whatever board-specific GPIOs are available. Change-Id: I14e4686c20f9610f90678e6e3bece8ba80d8621a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1825 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14pei_data.h: Fix commentMarc Jones
I added a comment to the pei_data.h to remind users about how the OC pins are mapped. Change-Id: I4d74eb69fc78816a69e61260c2c9b2b3e58cafec Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1824 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14Provide MRC with a console printing callback functionVadim Bendebury
Let memory initialization code use the coreboot romstage console. This simplifies the code and makes sure that all output is available in /sys/firmware/log. The pei_data structure is modified to allow passing the console output function pointer. Romstage console_tx_byte() is used for this purpose. Change-Id: I722cfcb9ff0cf527c12cb6cac09d77ef17b588e0 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1823 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13Add spinlock to serialize Intel microcode updatesStefan Reinauer
Updating microcode on several threads in a core at once can be harmful. Hence add a spinlock to make sure that does not happen. Change-Id: I0c9526b6194202ae7ab5c66361fe04ce137372cc Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1778 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13cros: Inform U-Boot via fake gpio when VGA Option ROM is loadedBill Richardson
This prepares the way for vboot to inform coreboot when it needs the VGA Option ROM loaded. Coreboot can't always know when it's needed (with keyboard-based dev-mode, coreboot can't tell if we're in dev-mode or not). By the time we get to U-Boot, it's too late, so we need two extra bits - one for vboot to tell coreboot to load the Option ROM and another for coreboot to let vboot know it's been done. This change sets up the communication, but doesn't act on it just yet. Even with this CL we always load the VGA Option ROM, so there's nothing to test. There should be no user-visible change. Change-Id: Ic4e9673a3707b6605064f4879bb3e74d4412322f Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: http://review.coreboot.org/1822 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13Export optionrom status on Stumpy/LumpyVadim Bendebury
ChromeOS' top of the tree u-boot expects coreboot to export information about option ROM status (started/not started). Stumpy and Lumpy were left behind and are not exporting this information. This CL fixes the problem. Change-Id: Id90035bd76ab177e4fc269efc2b74f15f641c77d Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1713 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13Make EmeraldLake2 work againDuncan Laurie
Fix GPIO exporting for new Vboot for oprom-matters GPIO and to make the power button static. Change-Id: Ic042c428a1d43512228c686121fa057d876606e1 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1761 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13Clean up stack checking codeStefan Reinauer
Several small improvements of the stack checking code: - move the CPU0 stack check right before jumping to the payload and out of hardwaremain (that file is too crowded anyways) - fix prototype in lib.h - print size of used stack - use checkstack function both on CPU0 and CPU1-x - print amount of stack used per core Signed-off-by: Stefan Reinauer <reinauer@google.com> Test: Boot coreboot on Link, see the following output: ... CPU1: stack: 00156000 - 00157000, lowest used address 00156c68, stack used: 920 bytes CPU2: stack: 00155000 - 00156000, lowest used address 00155c68, stack used: 920 bytes CPU3: stack: 00154000 - 00155000, lowest used address 00154c68, stack used: 920 bytes ... Jumping to boot code at 1110008 CPU0: stack: 00157000 - 00158000, lowest used address 00157af8, stack used: 1288 bytes Change-Id: I7b83eeee0186559a0a62daa12e3f7782990fd2df Reviewed-on: http://review.coreboot.org/1787 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13Add method for delaying adding of timestampsStefan Reinauer
In hardwaremain() we can't add timestamps before we actually reinitialized the cbmem area. Hence we kept the timestamps in an array and added them later. This is ugly and intrusive and helped hiding a bug that prevented any timestamps to be logged in hardwaremain() when coming out of an S3 resume. The problem is solved by moving the logic to keep a few timestamps around into the timestamp code. This also gets rid of a lot of ugly ifdefs in hardwaremain.c Change-Id: I945fc4c77e990f620c18cbd054ccd87e746706ef Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1785 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13Add Kconfig option to lock/unlock ME firmware during buildStefan Reinauer
For reasons of security and testing we want to be able to enable/disable ME section locking through a config option. Change-Id: I341c577cdae86be62c0e3d32bbd6b3333c004a5f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1798 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13clean up lapic_cpu_init.cStefan Reinauer
- drop changelog and add license header instead - 80+ character fixes - make stacks array static because it's not used externally - rename copy_secondary_start_to_1m_below() Change-Id: I8b461bea21ee0ddd85ea3a3a923d1e15167f54f0 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1821 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13Pass the CPU index as a parameter to startup.Ronald G. Minnich
This addition is in support of future multicore support in coreboot. It also will allow us to remove some asssembly code. The CPU "index" -- i.e., its order in the sequence in which cores are brought up, NOT its APIC id -- is passed into the secondary start. We modify the function to specify regparm(0). We also take this opportunity to do some cleanup: indexes become unsigned ints, not unsigned longs, for example. Build and boot on a multicore system, with pcserial enabled. Capture the output. Observe that the messages Initializing CPU #0 Initializing CPU #1 Initializing CPU #2 Initializing CPU #3 appear exactly as they do prior to this change. Change-Id: I5854d8d957c414f75fdd63fb017d2249330f955d Signed-off-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/1820 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-11-13Fix CONFIG_MAX_CPU set to 1 CPU build problemStefan Reinauer
There are some function dependancies that didn't work when MAX_CPU was set to 1 and the build would fail. Change-Id: I033a42056f7b48a40316e03772ed89ad9cb013fe Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1819 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-11-13Support better tracking of AP stack usage.Ronald G. Minnich
This change allows us to figure out how much of the AP stacks we are using, as well as to catch any case of an AP overrunning its stack. Also, the stack is poisoned, which is a good way to catch programming errors -- code should never count on auto variables being zerod. The stack bases are recorded in a new array, stacks. At the end, when all APs are initialized, the stacks are walked and the lowest level of the stack that is reached is printed. Build and boot and look for output like this: CPU1: stack allocated from 00148000 to 00148ff4:\ lowest stack address was 00148c4c CPU2: stack allocated from 00147000 to 00147ff4:\ lowest stack address was 00147c4c CPU3: stack allocated from 00146000 to 00146ff4:\ lowest stack address was 00146c4c Note that we used only about 1K of stack, even though in this case we allocated 4K (and in the main branch, we allocate 32K!) Change-Id: I99b7b9086848496feb3ecd207f64203fa69fadf5 Signed-off-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/1818 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-11-13SandyBridge/IvyBridge: Add IFD and ME firmware automaticallyStefan Reinauer
Right now coreboot's build process produces images that are not booting on actual hardware because they are smaller than the actual flash device and also don't have an IFD nor an ME firmware in them. In order to produce bootable images, you needed a wrapper script / extra step until now. With this change, the resulting coreboot.rom is actually bootable. Change-Id: I82714069fb004d4badc41698747a704bd9fed4da Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1771 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12vboot: Add option to skip TPM resume on S3 resumeStefan Reinauer
Change-Id: Ie4a98cc8af0dbcf09c7ace79668949ace5938c12 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1752 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12mmio pci config: Remove register constraintsAaron Durbin
The currently encoded register constraints fails compilation for SMM code or any code that compiles with -fPIC. The reason is that the ebx register is used for GOT base register. I don't believe the comment eluding to register constraints for AMD processors still applies. Therefore remove mmio_conf.h, and use the mmio methods in io.h. Change-Id: I391e5c2088ebc760b3a6ed6c37b65bbecab40a5c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/1801 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12cbfstool: Rework to use getopt style parametersStefan Reinauer
- Adding more and more optional and non-optional parameters bloated cbfstool and made the code hard to read with a lot of parsing in the actual cbfs handling functions. This change switches over to use getopt style options for everything but command and cbfs file name. - This allows us to simplify the coreboot Makefiles a bit - Also, add guards to include files - Fix some 80+ character lines - Add more detailed error reporting - Free memory we're allocating Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Ia9137942deb8d26bbb30068e6de72466afe9b0a7 Reviewed-on: http://review.coreboot.org/1800 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12Initial IGD OpRegion implementationStefan Reinauer
Change-Id: I9e57c5792409830895a1147799acab95d910a336 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1757 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12romcc_io: add pci_or_configX functions.Aaron Durbin
Some of the modules use their own rolled pci_or_configX functions. Therefore, make them first class so everyone can use them without copying them. Change-Id: I9a4d3364c832548dbfe18139c27cce2d60c3316d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/1797 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12x86/Makefile.inc: Test if the strings are equal by single equal signZheng Bao
Double equal sign like "test a == b" works. It really does, except NetBSD. But I haven't found any clue in the manual for the command test about "==". Change-Id: I37254cfeb688fd1092f2e549d24f8eb270f02fd8 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1817 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-11-12If cmos is invalid, always set the rtc date and timeStefan Reinauer
If cmos is invalid for any reason, always set the date and time before marking RTC valid. Change-Id: Ib9d154802f75221d58bf28ba9c813f2529904596 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1790 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12Remove duplicate defines from mc146818rtc.cMarc Jones
Remove the duplicate #defines and use what is set in mc146818rtc.h. Change-Id: Ic471e03c68b591d19c0646fdbea78374af11c8b8 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1789 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12Avoid using hardcoded values in MRC cache codeVadim Bendebury
The MRC cache code, as implemented, in some cases uses configuration settings for MRC cache region, and in some cases - the values read from FMAP. These do not necessarily match, the code should use FMAP across the board. This change also refactors mrccache.c to limit number of iterations through the cache area and number of fmap area searches. Change-Id: Idb9cb70ead4baa3601aa244afc326d5be0d06446 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1788 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12ivybridge: Catch unknown CPU revisionsStefan Reinauer
Adding an entry for 0x306a0 will make sure that all CPUs with CPUIDs 0x306aX will execute the driver (analog to Sandybridge behavior) Change-Id: I0353f3a48ecfd41274fdf6ee302c7d34482f1b5b Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1783 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12Store timestamps before resuming from suspendStefan Reinauer
in the resume case, timestamps were collected in RAM stage but not stored in CBMEM. This leads to only a single time stamp covering 200ms being available for all of ram stage. Change-Id: Ibf0bb92caf5e032c12fe4e1b9b84b3624d499511 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1781 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12Reduce default stack size to 4KStefan Reinauer
coreboot uses about 2K of stack on the BSP, and about 1K of stack on the APs. No reason to use an overdimensonal stack of 32k per core/thread. Change-Id: I734c240b992d40e1e35db3df5437c36da0a755cf Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1780 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12Add dependency for CONFIG_AP_IN_SIPI_WAITStefan Reinauer
Change-Id: Ia20c138dae1fc1382abe74303e1117472c513d1d Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1779 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12SPI: Add early romstage SPI driver using hardware sequencingDuncan Laurie
This is a basic romstage driver that can be used for the MRC cache code on systems where we do not have the MRC cache stored in a flash region that is memory mapped. It uses the hardware sequencing interface to avoid having to know anything about the flash chip itself. BUG=chrome-os-partner:15031 BRANCH=stout TEST=manual: this was tested with debug code added to romstage that attempted to read the MRC cache at offset 0x3e0000. SPI READ offset=003e0000 size=64 buffer=ff7fba00 SPI ADDR 0x003e0000 SPI HSFC 0x3f00 SPI READ: 0=4443524d SPI READ: 1=00000bb0 SPI READ: 2=00008e24 SPI READ: 3=00000000 SPI READ: 4=001c8bbb SPI READ: 5=0c206466 SPI READ: 6=0a043220 SPI READ: 7=000058b4 SPI READ: 8=00000000 SPI READ: 9=00000000 SPI READ: 10=00100000 SPI READ: 11=00100005 SPI READ: 12=20202025 SPI READ: 13=000e0001 SPI READ: 14=00000000 SPI READ: 15=00000000 Change-Id: I5f78f53111f912ff5dda52bbf90fdc1824b82681 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1777 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12ELOG: Support for non-memory mapped flashDuncan Laurie
If the event log is stored in flash that is not memory mapped then it must use the SPI controller to read from the flash device instead of relying on memory accesses. In addition a new CBMEM ID is added to keep an resident copy of the ELOG around if needed. The use of CBMEM for this is guarded by a new CONFIG_ELOG_CBMEM config option. This CBMEM buffer is created and filled late in the process when the SMBIOS table is being created because CBMEM is not functional when ELOG is first initialized. The downside to using CBMEM is that events added via the SMI handler at runtime are not reflected in the CBMEM copy because I don't want to let the SMM handler write to memory outside the TSEG region. In reality the only time we add runtime events is at kernel shutdown so the impact is limited. Test: 1) Test with CONFIG_ELOG_CBMEM enabled to ensure the event log is operational and SMBIOS points to address in CBMEM. The test should involve at least on reboot to ensure that the kernel is able to write events as well. > mosys -l smbios info log | grep ^address address | 0xacedd000 > mosys eventlog list 0 | 2012-10-10 14:02:46 | Log area cleared | 4096 1 | 2012-10-10 14:02:46 | System boot | 478 2 | 2012-10-10 14:02:46 | System Reset 3 | 2012-10-10 14:03:33 | Kernel Event | Clean Shutdown 4 | 2012-10-10 14:03:34 | System boot | 479 5 | 2012-10-10 14:03:34 | System Reset 2) Test with CONFIG_ELOG_CBMEM disabled to ensure the event log is operational and SMBIOS points to memory mapped flash. The test should involve at least on reboot to ensure that the kernel is able to write events as well. > mosys -l smbios info log | grep ^address address | 0xffbf0000 > mosys eventlog list 0 | 2012-10-10 14:33:17 | Log area cleared | 4096 1 | 2012-10-10 14:33:18 | System boot | 480 2 | 2012-10-10 14:33:18 | System Reset 3 | 2012-10-10 14:33:35 | Kernel Event | Clean Shutdown 4 | 2012-10-10 14:33:36 | System boot | 481 5 | 2012-10-10 14:33:36 | System Reset Change-Id: I87755d5291ce209c1e647792227c433dc966615d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1776 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12SPI: Fix and enable Fast Read supportDuncan Laurie
- Fix handling of 5-byte Fast Read command in the ICH SPI driver. This fix is ported from the U-boot driver. - Allow CONFIG_SPI_FLASH_NO_FAST_READ to be overridden by defining a name for the bool in Kconfig and removing the forced select in southbridge config - Fix use of CONFIG_SPI_FLASH_NO_FAST_READ in SPI drivers to use #if instead of #ifdef - Relocate flash functions in SMM so they are usable. This really only needs to happen for read function pointer since it uses a global function rather than a static one from the chip, but it is good to ensure the rest are set up correctly as well. Change-Id: Ic1bb0764cb111f96dd8a389d83b39fe8f5e72fbd Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1775 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12Fix gcc-4.7 building problem.Han Shen
Applied function attribute to function definition to avoid 'conflicting type' warning. Function declaration is in src/include/cpu.h void secondary_cpu_init(unsigned int cpu_index)__attribute__((regparm(0))); But function definition in lapic_cpu_init.c is missing the "__attribute__" part. Change-Id: Idb7cd00fda5a2d486893f9866920929c685d266e Signed-off-by: Han Shen <shenhan@google.com> Reviewed-on: http://review.coreboot.org/1784 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-11-12Add bd82x6x mainboards ASPM overrides.Marc Jones
The Intel PCH can override the ASPM settings via the MPC2 register. Add a chip override for F0-F7. Mainboards may implement this as needed. This also fixes the final PM setup being done too early. It was being done prior to the PCIe ASPM setup, which happens in the bridge scan. Change-Id: Idf2d2374899873fc6b1a2b00abdb683ea9f5bd6b Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1796 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-12SPI: Configure Software Sequence SPI Freq to match descriptorDuncan Laurie
Right now the SPI bus is getting set to 20mhz for transactions initiated with the software sequence interface. In order to be able to do reasonable fastread/write/erase we can bump this up to a higher value at boot before it gets locked at 20mhz. To do this read out the speed set in the SPI descriptor for hardware sequencing and apply it to software sequencing. Change-Id: I79aa2fe7f30f734785d61955ed81329fc654f4a4 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/1773 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-12SPI: Add Fast Read to the OPMENU for locked down SPIDuncan Laurie
The chips we are using do not use BE52 (block erase 0x52) so we can use that opcode menu location to enable fast read. Change-Id: I18f3e0e5e462b052358654faa0c82103b23a9f61 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/1772 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-12oprom: Ensure that mode information is valid before putting it in the tables.Gabe Black
At least when CONFIG_CHROMEOS is turned on, it's possible for CONFIG_FRAMEBUFFER_KEEP_VESA_MODE to be set but for there not to be any valid information to put into the framebuffer coreboot table. That means that what's put in there is junk, probably all zeroes from the uninitialized global variable the mode information is stored in (mode_info). When a payload uses libpayload and turns on the coreboot framebuffer console, that console will attempt to scroll at some point and decrease the cursor's y coordinate until it is less than the number of rows claimed by the console. The number of rows is computed by taking the vertical resolution of the framebuffer and dividing it by the height of the font. Because the mode information was all zeroes, the coreboot table info is all zeroes, and that means that the number of rows the console claims is zero. You can't get the unsigned y coordinate of the cursor to be less than zero, so libpayload gets stuck in an infinite loop. The solution this change implements is to add a new function, vbe_mode_info_valid, which simply returns whether or not mode_info has anything in it. If not, the framebuffer coreboot table is not created, and libpayload doesn't get stuck. Change-Id: I08f3ec628e4453f0cfe9e15c4d8dfd40327f91c9 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/1758 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-12Define post codes for OS boot and resumeDuncan Laurie
And move the pre-hardwaremain post code to 0x79 so it comes before hardwaremain at 0x80. Emit these codes from ACPI OS resume vector as well as the finalize step in bd82x6x southbridge. Change-Id: I7f258998a2f6549016e99b67bc21f7c59d2bcf9e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1702 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-12Pass correct sleep type to mainboard sleep handlerStefan Reinauer
The sleep type is 5 for S3 and 7 for S5. Change-Id: I7ffdb3d27b6994ac4a12a343caf4d7abb82fe6ca Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1760 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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