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2012-04-16S3 code in the mainboard.zbao
Persimmon is the demo board. Tested by Linux and Windows 7. Change-Id: I5ded942b51e63ebeb08ace0b202b4ed239b0c14c Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/624 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-04-16S3 code in coreboot public folder.zbao
1. Move the Stack to high memory. 2. Restore the MTRR before Coreboot jump to the wakeup vector. Change-Id: I9872e02fcd7eed98e7f630aa29ece810ac32d55a Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/623 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-04-16ACPI HEST table.zbao
HEST feature starts from ACPI 4.0. HEST is one of four kinds of tables of ACPI Platform Error Interfaces (APEI). In Windows world, APEI is called Windows Hardware Error Architecture (WHEA). APEI consists of four separate tables: 1. Error Record Serialization Table (ERST) 2. BOOT Error Record Table (BERT) 3. Hardware Error Source Table (HEST) 4. Error Injection Table (EINJ) All these 4 tables have the same header as FADT, MADT, etc. They are pointed by RSDP. For the HEST, it contains the error source. The types of them are defined as type description 1. Machine Check Exception (MCE) 2. Corrected Machine Check (CMC) 3. NMI Error 6. PCI Express Root Port AER 7. PCI Express Device AER 8. PCI Express Bridge AER 9. Generic Hardware Error Source Error source types 3, 4, and 5 are reserved for legacy reasons and must not be used. Currently AMD board only provide part of "Machine Check Exception (MCE)" & Corrected Machine Check (CMC)". we need to provide the header of each error source. Other types of Error Sources is in TODO list. Only persimmon is tested. Linux can add HEST feature. The dmesg says, ACPI: HEST 0000000066fe5010 00198 (v03 CORE COREBOOT 00000000 CORE 00000000) ...... HEST: Table parsing has been initialized. No more message is got. Windows can boot with this patch. Havent found a way to test it. Change-Id: I447e7f57b8e8f0433a145a43d0710910afabf00f Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/888 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2012-04-15cmos.layout: Remove invalid warningVikram Narayanan
"This file must be in UNIX format" is not valid anymore. Change-Id: I86169b12e7db159c1d3f380b0434874e9b6f5274 Signed-off-by: Vikram Narayanan <vikram186@gmail.com> Reviewed-on: http://review.coreboot.org/899 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-04-13Bifferboard: Fix MAINBOARD_PART_NUMBER.Uwe Hermann
Change-Id: I4acbeee8a0d26fae220ac22940b6f924e19af19c Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Reviewed-on: http://review.coreboot.org/894 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2012-04-12Convert AOpen DXPL Plus mainboard to CARKyösti Mälkki
Tested on real hardware, mainboard with dual Xeon P4 HT CPUs requires cache-as-ram init code with AP SIPI protocol. Also enable 2nd CPU and PATA and clean-up Kconfig and ACPI. Change-Id: I415482f3af22df79d82492c49aed83549f29aa56 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/886 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-12Add support for aligned allocationRon Minnich
Add a memalign function and have malloc use it. Also, change the default alignment for malloc to u64-aligned. Change-Id: I0788637008f5cb5ac801d8bbdc430ca992c98e81 Signed-off-by: Ron Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/887 Tested-by: build bot (Jenkins) Reviewed-by: Mathias Krause <minipli@googlemail.com>
2012-04-12S3 code in vendorcode folder.zbao
Change the ExecuteFinalHltInstruction to assembly code. so we can make sure the code can run stackless. Change-Id: I783ced6cf7c5bc29c12a37aef29077e610d8957d Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/622 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-12Add Southbridge support for S3.zbao
1. Add some CIMX call for S3. 2. Detect sleep type. Change-Id: I62888e8d8a03987ca88f5c935fa660f6b49a4fe9 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/621 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-12Unify IO APIC address specificationPatrick Georgi
Some places still hardcoded the address instead of using IO_APIC_ADDR. Change-Id: I3941c1ff62972ce56a5bc466eab7134f901773d3 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/677 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-11Intel e7505: cleanupsKyösti Mälkki
Fix delay loop comments. Time waited and the comments did not match in the origin (e7501), so delays currently "just work". Move reset detection to main raminit and don't use generic sdram_initialize for now, as there are local debug functions I need to use. Fix AOpen respectively. Disable ecc scrub, until I have it fixed for cache-as-ram use. Change-Id: I0529297f43c565d30b5fb7d1836700278ac029c4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/883 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-11Intel e7505: renames onlyKyösti Mälkki
Drop maybe-prefix in registers and tables. Have a name in place of PCI_DEV(x,y,z) to avoid confusion. Change-Id: I88f51b50d7fd83294aa14455a83418630e1bab85 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/882 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-11Remove obsolete empy macro definitionRon Minnich
In the early days of v2 the (e.g.) #ifdef SMP style was frowned upon in some quarters. Hence, empty definitions of functions were created. This particular function, possibly the last remaining example, was no longer even being used anywhere. Signed-off-by: Ron Minnich <rminnich@gmail.com>
2012-04-08Actually return %ebx value from cpuid_ebx()Jonathan A. Kollasch
Change-Id: I75f8f942950cad94439a10e389490ecfdd9272fe Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/880 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-06Remove Dell s1850Ron Minnich
It's almost 10 years old. It never worked. It's a soldered in FLASH, so mistakes are fatal. It's got no redeeming features. Remove the dell directory. In 12 years of trying to work with Dell we have not had much interest. It's misleading to have it there. Change-Id: I83ff009bd7a6d5289229ca39608789ae5c33710b Reviewed-on: http://review.coreboot.org/876 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-06Add support for SMSC MEC1308/1310 SuperI/O ECStefan Reinauer
Change-Id: If7921a66bab35f72c8455d5f0befc32a514ab417 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/825 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-06Add initial support for SMSC SIO1007 SuperI/O chipStefan Reinauer
early_serial and some ACPI needed for compilation Change-Id: I5dd970676488697156e0630392884f31149ac85b Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/824 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-06Add support for SMSC LPC47N207 SuperI/O chipStefan Reinauer
This includes only early serial support for now. Change-Id: I9a2a439e1d17a989428033fdb4a4b813553dab6d Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/823 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-06Fixes and Sandybridge support for lapic cpu initStefan Reinauer
- preprocessor macros should not use defined(CONFIG_*) but just CONFIG_* - drop AMD CPU model 14XXX config variable use. Those do not exist. - skip some delays on Sandybridge systems - Count how long we're waiting for each AP to stop - Skip speedstep specific CPU entries Change-Id: I13db384ba4e28acbe7f0f8c9cd169954b39f167d Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/871 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2012-04-06Fix support for RAM-less multi-processor initKyösti Mälkki
Fix regression after commit: 7dfe32c5408916b6cb23f1ec48e473e1c728d300 Only align 16-bit entry on platforms that really require it, indicated by selecting SIPI_VECTOR_IN_ROM in CPU Kconfig. Disable assertion test of AP_SIPI_VECTOR for platforms not depending on this feature. Build of romstage should be fixed to get the vector address from bootblock build automatically. Change-Id: Ide470833c0254df1a9ff708369ab1c095ccfb98d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/875 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-06Add Sandybridge/Cougar Point support to SMM relocation handlerStefan Reinauer
Previously this part of smmrelocate.S had to be omitted because the CONFIG_ options for those components did not exist yet. Add them back. Change-Id: I6ac94ca804e03062724401a08d1d174adac5e830 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/874 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2012-04-06Cache 8MB flash instead of 4MBStefan Reinauer
Also fix the MTRR check to use the total_mtrrs variable instead of a hardcoded 8. Change-Id: I2c5ceb3910cd949f43ecf5b8aff857d6ffe0b1a5 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/873 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-06Factor out function to find driver for a CPUStefan Reinauer
This function can be used outside of the normal CPU setup Change-Id: I810c63b8aff868a6f69d5b992bea1cfae5a5996b Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/868 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-06Add constants for fast path resume copyingStefan Reinauer
cache as ram does not usually cache the ram before it is up. Hence, if romstage.c backs up resume memory, the involved memcpy is always uncached. This makes resume very slow. On Sandybridge we copy the memory later, after enabling caching, and that allows us to resume in as little as 250ms. Change-Id: I31a71ad4468679d39880cf9a8c4e497bb7addf8f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/872 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-04-05Fix timer frequency detection on SandybridgeStefan Reinauer
Change-Id: Ide720bd91cde56a0afdd231d93500c371b1ffbe8 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/870 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-04-05amdfam10: add phenom II as known cpuBernhard Urban
Change-Id: I84a0f9e8e7a15c0aac8dc380de3ddf70b1decbd7 Signed-off-by: Bernhard Urban <lewurm@gmail.com> Reviewed-on: http://review.coreboot.org/864 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-05Invalidate cache before first jumpStefan Reinauer
Some CPUs (Sandybridge) seem to require this, and it does not hurt on other CPUs. Change-Id: I4fdb281b2b684ab5fea999aae28ca08dce24da4d Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/869 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-04-05smbios: Don't fill out firmware version on ChromeOSStefan Reinauer
In ChromeOS we potentially have different payloads with different versions. Since the user land tools get information on which one of them is loaded, leave the string in smbios empty so we can fill it out in the payload. Also fill out system version number and serial number with some constant values. Change-Id: Id1fed5a54b511c730975fa83347452f1274b8504 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/867 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-04-05Fill out ChromeOS specific coreboot table extensionsStefan Reinauer
ChromeOS uses two extensions to the coreboot table: - ChromeOS specific GPIO description for onboard switches - position of verified boot area in nvram Change-Id: I8c389feec54c00faf2770aafbfd2223ac9da1362 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/866 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-05Update documentation in smmrelocate.S to mention TSEGStefan Reinauer
Change-Id: I392f5fc475b15b458fc015e176e45888e7de27fb Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/861 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-05Add support for Intel Sandybridge CPUStefan Reinauer
Change-Id: I9f37e291c00c0640c6600d8fdd6dcc13c3e5b8d5 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/855 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-05Add support for Intel Sandybridge CPU (northbridge part)Stefan Reinauer
Change-Id: I06228ecf9cac931ad34e32871d5a4f2a4857b2ac Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/854 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-04Use fast memset in SMM mode, tooStefan Reinauer
... and always include IP checksumming in romstage. It's generally useful and our upcoming port needs it. Change-Id: I248402d96a23e58354744e053b9d5cca6b74ad3a Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/827 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-04Add support for Intel Panther Point PCHStefan Reinauer
Change-Id: Iac3cd25b36493bb203e849674320e113cc5fce32 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/853 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-04Add support for mainboard specific suspend/resume handlerStefan Reinauer
Some mainboards (most likely laptops) will need mainboard specific functions called upon a resume from suspend. Change-Id: If1518a4b016bba776643adaef0ae64ff49f57e51 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/852 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-04Move TPM code to romstageStefan Reinauer
We want to do TPM initialization as early as possible to keep the impact on boot time low. Therefore move it to romstage. Change-Id: I5f2e021e0b11bd70a78ad1f05ec09802d015dd9e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/856 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-04Drop verified boot code from acpi.cStefan Reinauer
We changed our verified boot initialization to run from romstage, as that allows faster boot times and does not add as much ChromeOS specific code to generic files. Change-Id: Id4164c26d524ea0ffce34467cf91379a19a4b2f6 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/851 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-04Add support to run SMM handler in TSEG instead of ASEGStefan Reinauer
Traditionally coreboot's SMM handler runs in ASEG (0xa0000), "behind" the graphics memory. This approach has two issues: - It limits the possible size of the SMM handler (and the number of CPUs supported in a system) - It's not considered a supported path anymore in newer CPUs. Change-Id: I9f2877e46873ab2ea8f1157ead4bc644a50be19e Signed-off-by: Duncan Laurie <dlaurie@google.com> Acked-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/842 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2012-04-04Don't unconditionally show ChromeOS optionsStefan Reinauer
Google ChromeOS specific options were shown in the main menu unconditionally, even on non-ChromeOS devices. Instead, hide these options unless CONFIG_CHROMEOS is set, and also put them in a separate menu. Change-Id: I75f533ed5046d6df4f7d959a0ca4c2441340ef2f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/848 Reviewed-by: Martin Roth <martin@se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Mathias Krause <minipli@googlemail.com>
2012-04-03Add support for Intel Turbo Boost featureStefan Reinauer
From wikipedia: Intel Turbo Boost is a technology implemented by Intel in certain versions of their Nehalem- and Sandy Bridge-based CPUs, including Core i5 and Core i7 that enables the processor to run above its base operating frequency via dynamic control of the CPU's "clock rate". It is activated when the operating system requests the highest performance state of the processor. Change-Id: I166ead7c219083006c2b05859eb18749c6fbe832 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/844 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-03smbios: add support for onboard devices extended informationStefan Reinauer
Add support for type 41 smbios tables (to be used by board specific smbios handlers) Change-Id: Id6af5e4b1f5c5c78c63759d24fdc7cf8537ae5e6 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/843 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-04-02Apply cache-as-ram conditionally on socket mPGA604Kyösti Mälkki
The socket mPGA604 is for P4 Xeon which to my knowledge is always HT-enabled. I assume the existing usage of car/cache_as_ram.inc on socket_mPGA604, namely the Tyan S2735, as broken. Existing car/cache_as_ram.inc has invalid SIPI vector and it does not initialise AP CPU's to activate L2 cache. Other mPGA604 boards are not affected, as they have not been converted to CAR. Change-Id: I7320589695c7f6a695b313a8d0b01b6b1cafbb04 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/607 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-02S3 code whitespaces changes.zbao
some blank changing is integrated into the previous patches, which hold the unsplitted diff hunk. Change-Id: If9e5066927c5e27fee7ac8422dbfbf2cbeac7df5 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/625 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-04-02Add sb800 spi support.zbao
It is for S3, storing the recovring data in the nonvolatile storage, i.e., flash. Change-Id: Ie9e4f42a80c93d92d2e442f0e833ce06d88294f9 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/620 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-04-02x86, oprom: ensure DF is always clearedMathias Krause
The Option ROM might mess with the EFLAGS register and break assumptions the C part of coreboot implicitly has, e.g. the state of the direction flag. Prevent Option ROMs from confusing coreboot by restoring the old EFLAGS value after the Option ROMs has finished and always clear the direction flag before calling the C part of the interrupt handler. Change-Id: I84663be6681b17f95f48d93f0b730e443336b4a8 Signed-off-by: Mathias Krause <minipli@googlemail.com> Reviewed-on: http://review.coreboot.org/837 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-02[ChromeOS] Don't initialize VGA Option ROM in normal modeStefan Reinauer
ChromeOS features two different modes: normal mode and developer mode (aka jailbreak mode). In developer mode, we need to display a warning screen for security reasons. However, in normal mode we want to boot blazingly fast. Therefore we don't run (VGA) option ROMs, unless we have to print something on the screen before the kernel is loaded. Change-Id: I37f63d0b082a48e037e65bde2b380f9b8743ed29 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/829 Tested-by: build bot (Jenkins) Reviewed-by: Mathias Krause <minipli@googlemail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-02Add EC component for SMSC MEC1308/1310Stefan Reinauer
Change-Id: I92109fb633a1a3090b4b1767dd119b8c8a1b5f81 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/828 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-02Add support for ITE IT8772F SuperI/O chipStefan Reinauer
Change-Id: I8e80c22eb0f3cb68f2457be6b2e7894df60ed632 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/822 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-02Add a helper function to determine the number of enabled CPUsStefan Reinauer
Change-Id: Ia72926002571e0f250849fa5db048bd8b2e92400 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/821 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-02Align: Make sure 1 is treated as unsigned long instead of intStefan Reinauer
... and drop duplicate definition in via/epia-n code. Change-Id: Id79daaaa35c4d412c8c1f621a3638d129681d331 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/820 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 04:40:00 +0000