coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2012-05-08	Some more #if cleanup	Patrick Georgi
2012-05-08	Add config_enabled() from Linux	Patrick Georgi
2012-05-08	Clean up #ifs	Patrick Georgi
2012-05-04	Make CBFS output more consistent	Stefan Reinauer
2012-05-04	siemens/sitemp_g1p1: Drop debug code	Patrick Georgi
2012-05-04	roda/rk886ex: Expose VGA devices in devicetree	Patrick Georgi
2012-05-03	Don't pre-enable SATA AHCI in romstage.c	Stefan Reinauer
2012-05-03	Print some useful debugging information in PSS table creation	Stefan Reinauer
2012-05-03	Make creation of CBMEM_ID_RESUME_SCRATCH depending on Agesa	Stefan Reinauer
2012-05-03	Add missing newline to printk in Sandybridge init code	Stefan Reinauer
2012-05-03	Tell CBMEM pretty printer about MRC cache	Stefan Reinauer
2012-05-03	Fix register corruption during Intel Microcode update	Stefan Reinauer
2012-05-02	ChromeOS: drop unused debug header description	Stefan Reinauer
2012-05-02	Make Intel i5000 specific options only appear on i5000 systems	Stefan Reinauer
2012-05-02	Don't include console.h in microcode.c when compiling with ROMCC	Stefan Reinauer
2012-05-02	Strip quotes from Sandybridge MRC blob	Stefan Reinauer
2012-05-02	Sandybridge: Display platform information early	Vadim Bendebury
2012-05-01	Fix issue with PCIe power management setup	Duncan Laurie
2012-05-01	Add an option to enable PCIe root port coalescing	Duncan Laurie
2012-05-01	Update PCIe Root Port _PRT to handle re-mapped functions	Duncan Laurie
2012-05-01	Drop CONFIG_MAX_PHYSICAL_CPUS on non-AMD boards	Stefan Reinauer
2012-05-01	Fix SATA port map to only enable port 0	Stefan Reinauer
2012-05-01	Update Ivybridge GT power meter tables	Duncan Laurie
2012-05-01	Update ivybridge graphics initialization	Duncan Laurie
2012-05-01	Fix TPM driver to work with multiple vendor TPMs	Stefan Reinauer
2012-05-01	Don't disable ACPI in the S3 resume path	Duncan Laurie
2012-05-01	Only send ME Dram Init Done message on Sandybridge	Duncan Laurie
2012-05-01	Modify DMI init for IvyBridge	Vincent Palatin
2012-05-01	add new LPC controller device ID value	Vadim Bendebury
2012-05-01	Allow device ID arrays in the PCI driver structure	Vadim Bendebury
2012-05-01	Clean up Emerald Lake 2 mainboard directory	Gabe Black
2012-05-01	Allow more CPU cores on Emerald Lake 2 CRB	Stefan Reinauer
2012-05-01	Set up ChromeOS dev mode, recovery, and write protect GPIOs on Emerald Lake 2.	Gabe Black
2012-05-01	Fix Sandybridge/Ivybridge mainboards according to code review	Stefan Reinauer
2012-05-01	Move VSA support from x86 to Geode	Patrick Georgi
2012-05-01	Support adding stages with cbfs-files	Patrick Georgi
2012-05-01	Make geode_lx use the vsa from blobs repository	Patrick Georgi
2012-05-01	Set up the Emerald Lake 2 SMI and SCI sources based on the schematic.	Gabe Black
2012-05-01	Add Kconfig options to handle the blobs repository	Patrick Georgi
2012-04-30	Add support for Sandybridge base Samsung ChromeBox	Stefan Reinauer
2012-04-30	Add support for Sandybridge based Samsung ChromeBook	Stefan Reinauer
2012-04-30	Add support for Intel Emerald Lake 2 CRB	Stefan Reinauer
2012-04-30	Fix up Sandybridge C state generation code	Stefan Reinauer
2012-04-30	acpigen: make acpigen_write_CST_package_entry non-static	Stefan Reinauer
2012-04-30	Sandybridge: Temporarily disable MRC cache finding code	Stefan Reinauer
2012-04-30	acpi: Add defines for functional fixed hardware	Stefan Reinauer
2012-04-30	acpigen: Add support for generating T state tables	Stefan Reinauer
2012-04-30	Rework ACPI CST table generation	Stefan Reinauer
2012-04-30	Add default map_oprom_vendev() for AMD Family 14h processors.	Martin Roth
2012-04-29	Update amd/south_station/fadt.c with various fixes	Martin Roth