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2018-08-13soc/broadcom/cygnus: Increase romstage SRAM size in memlayoutPhilipp Deppenwiese
* Needed for additional code in later patches. * SOC is obsolete anyway. Change-Id: I5bbdf19cc886103e9e7a6b75219d6881cfe9c757 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/23764 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13mb/google/octopus: Enable SAR config for Intel 9560 moduleJohn Zhao
Enable the GEO SAR feature for Octopus. Program wifi_sar VPD key. coreboot reads the VPD and creates the ACPI table as per the WGDS spec. BUG=b:112288077 TEST=Program VPD key, extract acpi table ssdt and valiate WGDS entry. Change-Id: I40a6fd9e0ec8b440996bf3389322fd89bcca15a4 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/27966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-12mb/google/octopus: Do not configure IOStandby for WLAN_PE_RSTFurquan Shaikh
PERST signal is asserted/deasserted by ACPI routines during suspend/resume. Configuring IOStandby for WLAN_PE_RST can result in failure to resume from suspend state with wake-over-WLAN. This change removes the IOStandby configuration for WLAN_PE_RST. BUG=b:112371978 Change-Id: Ic7c0b2aa144233f8bbb4e5169d96347a1290abe1 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-12mb/google/octopus: Configure WiFi wake as NC when using CNViFurquan Shaikh
When CNVi is being used, external wake using GPIO_119 is not required. This change configures GPIO_119 as PAD_NC if CNVi is taken out of reset. BUG=b:112371978 Change-Id: Ifee90f428ed43c4d7c612c170476aff43b4a33ce Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-12soc/intel/apollolake: Get rid of cnvi.aslFurquan Shaikh
There is no need to add a special cnvi.asl file for the CNVi device. This can be handled by drivers/intel/wifi just like a PCIe WiFi device. This change gets rid of the cnvi.asl file and its usage in southbridge.asl file. BUG=b:112371978 Change-Id: I0b798cdd430768730b7ada61ca4cb1f63c2a4229 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-12mb/google/octopus: Use correct chip for CNVi deviceFurquan Shaikh
This change uses drivers/intel/wifi chip for CNVi device to ensure that: 1. Correct device name shows up in ACPI node 2. It is possible to pass any parameters from devicetree to wifi driver for SSDT generation. BUG=b:112371978 Change-Id: Ia49820dd4f9cf2e0a9ef14931fbddd8a723208c0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-12drivers/intel/wifi: Get rid of unused wrdd.aslFurquan Shaikh
This change gets rid of unused wrdd.asl in intel wifi driver. This file became redundant when all boards moved to using SSDT for wifi device. Change-Id: I8b5b3816d77c90e75052c58a3120ab62185873a7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27963 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-12drivers/intel/wifi: Skip adding SSDT entry if device is disabledFurquan Shaikh
This change checks to ensure that device is enabled before adding entry into SSDT. BUG=b:112371978 Change-Id: Ibe4811bef8cf0978b7a82d66a32f96247b9c823d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-12mb/google/octopus: Dynamically disable CNVi/PCIe deviceFurquan Shaikh
This change checks to see if CNVi module is out of reset: 1. If yes, then PCIe device for WiFi is disabled. 2. If no, then CNVi device is disabled. BUG=b:112371978 Change-Id: I6e6cf2e646c897df017913056db87ac0cffa1a8e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-08-12soc/intel/apollolake: Add CNVi device to list of PCI devsFurquan Shaikh
This change adds CNVi device to list of PCI devs. BUG=b:112371978 Change-Id: I6def98db3846c2244812a9a2ce84340bd2149b48 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-12mb/google/octopus: Disable unused I2C2 in devicetreeFurquan Shaikh
I2C2 is unused on all octopus variants. This change disables it in devicetree. BUG=b:112458032 Change-Id: I55abef864c06a448011f9570d3e6c0aa8bfdc5bc Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28016 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-12mb/google/octopus/var/fleex: Update GPIO config for fleex bid >= 1Furquan Shaikh
This change updates GPIO configuration for fleex boards with id >= 1 This follows the same model as phaser: a. Dynamically update touchscreen power enable GPIO in devicetree. b. Provide default and bid0 tables for GPIO configuration in ramstage. c. Configure WLAN enable GPIO differently in bootblock based on boardid. d. Disable unused I2C devices in devicetree. BUG=b:112458032 TEST=No errors observed on boot-up on fleex. Change-Id: Ib4c449168b08e2393e2395d6b49469be5599c2ce Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-12mb/asus/maximus_iv_gene-z: Add VBTTristan Corrick
The file `data.vbt` matches the VBT in the latest version of the vendor firmware (version 3603). Tested with Linux 4.9 and everything works as expected. Change-Id: I8e3b1d274ac0df63989d966f477013e780611fa1 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/28050 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-11drivers/pc80/tpm: add support for SLB9665 TPM2.0 moduleKamil Wcislo
SLB9665 are not initialized correctly. It looks like SLB9665 and SLB9660 return the same DEV ID. Initialize these devices according to TPM Kconfig selections. Tested on apu2 with following change: https://review.coreboot.org/#/c/coreboot/+/28000/ Change-Id: Ic20b9a65ef6a4ee392a9352f7c9bf01b2496f482 Signed-off-by: Kamil Wcislo <kamil.wcislo@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/21983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-08-10drivers/i2c: Add i2c TPM support for different stagesPhilipp Deppenwiese
Change-Id: Ib0839933f8b59f0c87cdda4e5374828bd6f1099f Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/23759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-08-10soc/cavium/cn81xx: Fix minor thingsPatrick Rudolph
* Move cbmem.c to cn81xx folder * Store CBMEM below 4 GiB * Make sure CBMEM doesn't overlap with ATF scratchpad * Fix ATF scratchpad not marked as reserved due to wrong calculation * The scratchpad is the last 1 MiB at the end of DRAM. Tested on Cavium CN81xx EVB: The ATF scratchpad is now marked reserved and the configuration tables are located below 4 GiB. Linux still boots. Change-Id: Ibbc8b586f04bd6867c045f5546b32a77c057ac74 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27955 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-10[HACK]cavium/cn81xx/soc: Don't advertise CAR area as usablePatrick Rudolph
It's broken. Change-Id: I3ec8fff99e21cbdf4ad3f4562ff9bbc1cd3c135b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/28003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-08-10lib/fit: support booting initrd placed above 4GiBPatrick Rudolph
Store initrd offset as 64bit integer. Tested on Cavium CN81XX EVB: The initrd could be loaded when placed above 4GiB. Previously it failed to find the initrd. Change-Id: I5d1ae860ae4a4465546bc0ef89937d611d1e56ab Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/28002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-08-10mb/google/octopus: add support for new shared memory configAaron Durbin
Allow for shared dram configuration by introducing a new table that collapses the common settings after removing the part numbers. When employing this scheme the part number comes from CBI. BUG=b:112203105 TEST=Placed part number in cbi. Faked out memory sku id. And enabled DRAM part num always in cbi. Everything checked out. Change-Id: I5229695ce3eb686421b89ac55d8df4b9fcec705c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/27991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-10src: Fix typoElyes HAOUAS
Change-Id: I689c5663ef59861f79b68220abd146144f7618de Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-10src/drivers: Fix typoElyes HAOUAS
Change-Id: I9144937b72a98517cbd41c093cff7bad543b4140 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27916 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-10mb/gigabyte/ga-{h61m-s2pv,b75m-d3h,b75m-d3v}: Clean up CMOS filesAngel Pons
Options that were deemed unneceesary on other code reviews have been removed from the layout files. In addition, the checksummed range has been extended to cover sata_mode and gfx_uma_size. Change-Id: Id9e904f447809231806a786e39ed638f21e1bc5a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/27217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-08-10mb/gigabyte/ga-{h61m-s2pv,b75m-d3h,b75m-d3v}: Clean up mainboard codeAngel Pons
I ported ga-h61m-s2pv based on the two Gigabyte b75m boards. Based on another mainboard's code review comments, this patch improves the code quality of these three similar boards. ga-h61m-s2pv is tested and confirmed to be working, but I cannot say the same regarding the other two mainboards as I do not have them. Change-Id: Ib7747cceb5ba56f791677204cdc4c54c129c70c3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/27211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-08-10fit: Handle decompression errors properlyPatrick Rudolph
Set payload to NULL in case of decompression errors. Fixes the attempt to boot a kernel that couldn't be decompressed. Change-Id: I3a602b0e90923a0b5a3683c4a0adf9e4733d5a2a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-10src/soc/intel: Add new device IDs to support coffeelakeMaulik
1. Add new device IDs for SATA, GT and Northbridge to pci_ids.h 2. Add entry to identify CFL U GT and CPU to respective files 3. Add entry to identify CFL U to report_platform.c BUG=none BRANCH=none TEST=Boot to CFL U RVP board with this patch and check if coreboot is able to enumerate various devices and display correct component names properly in serial logs. Change-Id: I47c97fb9eb813587cd655e2bce05a686091619ed Signed-off-by: Maulik <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/27522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-08-10arm64: Turn architectural register accessors into inline functionsJulius Werner
Accesses to architectural registers should be really fast -- they're just registers, after all. In fact, the arm64 architecture uses them for some timing-senstive uses like the architectural timer. A read should be: one instruction, no data dependencies, done. However, our current coreboot framework wraps each of these accesses into a separate function. Suddenly you have to spill registers on a stack, make a function call, move your stack pointer, etc. When running without MMU this adds a significant enough delay to cause timing problems when bitbanging a UART on SDM845. This patch replaces all those existing functions with static inline definitions in the header so they will get reduced to a single instruction as they should be. Also use some macros to condense the code a little since they're all so regular, which should make it easier to add more in the future. This patch also expands all the data types to uint64_t since that's what the actual assembly instruction accesses, even if the register itself only has 32 bits (the others will be ignored by the processor and set to 0 on read). Arm regularly expands registers as they add new bit fields to them with newer iterations of the architecture anyway, so this just prepares us for the inevitable. Change-Id: I2c41cc3ce49ee26bf12cd34e3d0509d8e61ffc63 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-10arm64: Drop checks for current exception level, hardcode EL3 assumptionJulius Werner
When we first created the arm64 port, we weren't quite sure whether coreboot would always run in EL3 on all platforms. The AArch64 A.R.M. technically considers this exception level optional, but in practice all SoCs seem to support it. We have since accumulated a lot of code that already hardcodes an implicit or explicit assumption of executing in EL3 somewhere, so coreboot wouldn't work on a system that tries to enter it in EL1/2 right now anyway. However, some of our low level support libraries (in particular those for accessing architectural registers) still have provisions for running at different exception levels built-in, and often use switch statements over the current exception level to decide which register to access. This includes an unnecessarily large amount of code for what should be single-instruction operations and precludes further optimization via inlining. This patch removes any remaining code that dynamically depends on the current exception level and makes the assumption that coreboot executes at EL3 official. If this ever needs to change for a future platform, it would probably be cleaner to set the expected exception level in a Kconfig rather than always probing it at runtime. Change-Id: I1a9fb9b4227bd15a013080d1c7eabd48515fdb67 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-10arm64: Remove set_cntfrq() functionJulius Werner
CNTFRQ_EL0 is a normal AArch64 architectural register like hundreds of others that are all accessed through the raw_(read|write)_${register}() family of functions. There's no reason why this register in particular should have an inconsistent accessor, so replace all instances of set_cntfrq() with raw_write_cntfrq_el0() and get rid of it. Change-Id: I599519ba71c287d4085f9ad28d7349ef0b1eea9b Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27947 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-10marvell: Remove 'mvmap2315' SoCJulius Werner
I'm pretty sure this SoC doesn't actually exist. Change-Id: I53e268ee1795e524a2a4562d67a2b9f28af966d1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27965 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-10google: Remove board 'rotor'Julius Werner
Rotor is dead, long live [PROJECT NAME REDACTED]! Change-Id: Ia9308944257255e077a44c1df262c7f49c69890c Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27964 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-09mb/google/octopus: add support for fetching DRAM part number from CBIAaron Durbin
Add 3 new Kconfig options: DRAM_PART_NUM_IN_CBI DRAM_PART_NUM_ALWAYS_IN_CBI DRAM_PART_IN_CBI_BOARD_ID_MIN These control whether to 1. attempt to use CBI at all 2. always use cbi and 3. conditionally use cbi based on board id. The intent is that the MIN variant would be used for the tranisition period then cut over to ALWAYS after full transition. Since multiple OEMs have different schedules these options are there to bridge the gap. yorp. bip, and octopus build targets would never flip DRAM_PART_NUM_IN_CBI, but in case someone does the MIN values are 255 to always take the old path. BUG=b:112203105 TEST=Set correct part number on phaser during testing. Change-Id: If9a0102806d78e89330b42aa6947d503a8a2deac Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/27946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-09arch/x86/tables.c: Avoid static analysis error for unused valueRichard Spiegel
Within procedure arch_write_tables, the pointer "rom_table_end" is updated every time a table is created. However, after creating last table, pointer rom_table_end is not used, though it is updated. Add a "(void)rom_table_end;" at the end to avoid the static analysis error. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: I8a34026795c7f0d1bb86c5f5c0469d40aa53994a Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09cpu/x86/mp_init.c: Avoid static analysis error for unused valueRichard Spiegel
Within procedure save_bsp_msrs, the structure pointer "msr_entry" is updated every time procedure save_msr() is called. However, after the last call of save_msr(), "msr_entry" is not used, thus causing a static analysis error. Add a "(void)msr_entry;" at the end to avoid the static analysis error. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: If0fb336fbf49eec3da255fadbe38b3a38768d0cf Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/cpu: Fix typoElyes HAOUAS
Change-Id: I13dec72b2de2a525d45909e697c33fbdc31111cb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/device: Fix typoElyes HAOUAS
Change-Id: I65e57b37db9649b30ca25b2150f21ebffee73105 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/ec/google/chromeec: Fix typoElyes HAOUAS
Change-Id: Ia05c9c5233319fe74d81c1f1db6ca3c2d875f9e7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/include: Fix typoElyes HAOUAS
Change-Id: Iff445dccf29957078b8308d73fb302d03cf47d31 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/lib: Fix typoElyes HAOUAS
Change-Id: Ie5bf036a63a254dd95b45a0823086c8079eeafe2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/mainboard: Fix typoElyes HAOUAS
Change-Id: Ief6a04ccb63658b5fb03cd1d298bf00948cf7410 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/arch: Fix typoElyes HAOUAS
Change-Id: I24d219b4ce6033f64886e22973ca8716113d319f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/northbridge: Fix typoElyes HAOUAS
Change-Id: I00094028036f33892362b935899e1bceef1da625 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/security/vboot: Fix typoElyes HAOUAS
Change-Id: Ie98ee00a83d837b6d6491fed3a474048dc23e104 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/soc: Fix typoElyes HAOUAS
Change-Id: I8053d0f0863aa4d93692487f1ca802195c2d475f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/superio: Fix typo and remove unneeded whitespaceElyes HAOUAS
Change-Id: Iadc28d1632aa9b7d0b028c229049a348d5c07882 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09google/grunt: Override BayHub EMMC driving strengthKevin Chiu
Careena EVT SanDisk EMMC sku has high fail rate of 0x5B reboot failure. It'll need to increase 1.8V EMMC CLK/CMD, Data driving strength for this issue. CLK[6:4] CMD,DATA[3:1] original register value: 0x6B enhanced: 0x7F BUG=b:111964336 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I3db38ff12c566c258895c6643008a0472ca528bb Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/27816 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-09drivers/spi/spi_flash.c: Check input parameterRichard Spiegel
In procedure spi_flash_cmd_erase(), parameter "len" is not validated and could lead to the return of an invalid (non-initialized) value. Validate the parameter early on. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: I0b5129a15c9e0ea45f4dba4ab0729196cb64699b Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/device/pci_rom.c: Remove double initializationRichard Spiegel
In procedure pci_rom_probe(), variable vendev is initialized twice. Remove one initialization. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: I8a71aa1aea2047ab2d98e09d1d6610de552b6cb4 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27949 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-09arch/x86/exception.c: Remove double initializationRichard Spiegel
In procedure exception_init(), structure pointer gates is initialized twice. Remove one initialization. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: If0280963e8b796f795e77a11569277dcf16b4507 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27948 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-09cpu/x86/mp_init.c: Fix error treatmentRichard Spiegel
In procedure allocate_cpu_devices(), if structure pointer new is null skip using the pointer. Add a "continue;" to skip using the pointer. The issue was found by static analysis tool. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: I7011fbfa0725f22a6dfbca6752e668eddac3463c Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27951 Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-09mb/google/octopus: remove disable_periodic_retraining optionsAaron Durbin
The Micron material that was broken has long since been fixed that required this option. glkrvp had these stale entries and were subsequently copied to octopus. Remove the need for this option. BUG=b:35581751 Change-Id: Id73584367c2ad0e4958b5ea0f04a28e5fc82d085 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/27959 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 14:48:30 +0000