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2015-12-09mohonpeak/Kconfig: Fix whitespace issuesMartin Roth
Auto-indent did me wrong, and I didn't notice it. Change-Id: I5a736cf53a3bdbe57b28b2d6a55befd341d8dfd8 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12655 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-12-09sb/amd/sb700: Enable watchdog timer for OS useTimothy Pearson
Change-Id: Ib0281139cafe74a22a24a377b3fdec1c59e934f3 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12687 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-09google/oak: define flash sizePatrick Georgi
We never defined the flash size for this board, so the (too small) default was used. Instead, adopt the size given in depthcharge's fmap description. Change-Id: I63782922ee05a9595d6c0de56750460ebb67aec6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12674 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-12-09amdfwtool: Hide the prefix of targetZheng Bao
Make the definitions of rules compliant with others. Change-Id: Ieef3a9c3fae5beaa1ea3e14e890cfb9145090c3b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/12685 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-09AMD/bettong: Add missing uart.c for UARTZheng Bao
Change-Id: Ie49732c6874f2b443e314eb3412ddee054d9c0bb Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/12669 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-08sb/amd/sr5650: Allow resource allocator to assign bus numbersTimothy Pearson
At some point in the past disconnected PCIe bridges were completely disabled to work around a hang on bridge probe. This hang was resolved at some point, and the disconnected PCIe bridges should be enabled to receive a bus number per the RPR. This resolves a slew of warnings in the Linux boot log regarding invalid bridge configurations for disconnected bridge devices. Change-Id: Ic26e2d62ec5ddb9f22275c2afec7d560326263c7 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12673 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-12-08vendorcode/google/chromeos: Only select ELOG if SPI_FLASH is availableMartin Roth
ELOG requires SPI_FLASH, so don't bother selecting if if SPI_FLASH isn't available. Change-Id: I080ac47e74aba820c94409d4913647abee215076 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12661 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-08intel/strago: Remove CONFIG_ from CONFIG_GOP_SUPPORT inside KconfigMartin Roth
The CONFIG_ is only used for Kconfig symbols outside of Kconfig. If used inside Kconfig, you'd end up with CONFIG_CONFIG_GOP_SUPPORT when it was used in the C code. Change-Id: I572323ef08fdd937d33ded1c27a418b3ad856147 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12664 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-08console: Allow ARM64 platforms to select bootblock consoleMartin Roth
Change-Id: I09943aafe29f6e7a2a878e7b6141661982dfc645 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12658 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-08soc/intel/common: Remove USE_FMAP - symbol doesn't existMartin Roth
The USE_FMAP Kconfig symbol doesn't exist, so remove things that are depending on it not being enabled. Change-Id: I1946f5d13a762ab07744a1d9a6cb754433e6701d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12663 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-08lenovo/t500: Add clone of Lenovo T400Francis Rowe
The existing code for the Lenovo T400 works without changes on the Lenovo T500. Same HDA verbs are provided by Lenovo BIOS on both laptops. Change-Id: I300408a8a0ed00476aee6061925befc2822fb505 Signed-off-by: Francis Rowe <info@gluglug.org.uk> Reviewed-on: https://review.coreboot.org/10545 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-08soc/intel/skylake: Remove obsolete Kconfig symbolsMartin Roth
CPU_MICROCODE_IN_CBFS was renamed to SUPPORT_CPU_UCODE_IN_CBFS in commit 66e0c4c8 (cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFS) Both CPU_MICROCODE_IN_CBFS and SUPPORT_CPU_UCODE_IN_CBFS were present, so just remove CPU_MICROCODE_IN_CBFS. SMM_MODULES was removed in commit 44cbe10f (smm: Merge configs SMM_MODULES and SMM_TSEG) Change-Id: Icdd4fcc5a3a97aee443742aaab3df92b53ff4589 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12662 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-08qemu-x86: Enable SMP supportPatrick Georgi
QEMU can do this for a while now. Change-Id: I3a5027a7afc9dd18463d26cb42fe68747a89f6b0 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: https://review.coreboot.org/12656 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-12-08northbridge/amd/agesa/agesawrapper.c: Fix Kconfig symbolsMartin Roth
The Kconfig symbols were missing an underscore, so were not getting evaluated properly. Change-Id: I619cf3f44f44f9c9699482d64164d3db28cd4c8f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12559 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-12-08AMD/bettong: Remove the useless period (trivial)Zheng Bao
It seems that no one add period in Kconfig. Change-Id: Ie9c585a8e6f1a73036b92b2873dc19284d82dc39 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/12668 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2015-12-08intel/littleplains: Update with recent changes to mohonpeakMartin Roth
- Change SEABIOS_MALLOC_UPPERMEMORY to using PAYLOAD_CONFIGFILE. - Add saved seabios .config with CONFIG_MALLOC_UPPERMEMORY unset. - Remove fixed microcode location. Change-Id: I8b723edf6d6b5542f118e9e0e1aee8104d9cde86 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12635 Tested-by: build bot (Jenkins) Reviewed-by: David Guckian <david.guckian@intel.com>
2015-12-08intel/common/firmware: Add option to configure SPI for EM100Martin Roth
Add a Kconfig option to set the firmware descriptor to allow EM100 use. Change-Id: If5d7cd6ad671f0328ee5be0b5e660dbc837fcac3 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12637 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-12-07mainboard/asus/kgpe-d16: Use I/O PCI access in bootblockTimothy Pearson
The existing code incorrectly used standard PCI access calls in the bootblock. Use the I/O PCI access calls as the normal PCI access mechanisms have not yet been set up. Also ensure the recovery jumper GPIO has been set to input mode before reading it. Change-Id: Id626d01526427004b2404e4d9b44d7c987d172d1 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12651 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-12-06fsp_baytrail: Add missing newline to eMMC Mode logBen Gardner
Change-Id: Icd697053c2ea1a2ac42bdd045134d223d93d5403 Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/12623 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-06pcengines/apu1: Supply _HID object for ACPI GPIO devicesMartin Roth
The _HID was present for the top level BTNS and LEDS Devices, but was missing in the individual devices. The alternative would be to supply the GPIO being used as an _ADR object, but since it looks like the driver already has another method of handling that, it isn't required. Fixes these IASL warnings: dsdt.aml 1522: Device (BTN1) Warning 3141 - ^ Missing dependency (Device object requires a _HID or _ADR in same scope) dsdt.aml 1567: Device (LED1) Warning 3141 - ^ Missing dependency (Device object requires a _HID or _ADR in same scope) dsdt.aml 1576: Device (LED2) Warning 3141 - ^ Missing dependency (Device object requires a _HID or _ADR in same scope) dsdt.aml 1587: Device (LED3) Warning 3141 - ^ Missing dependency (Device object requires a _HID or _ADR in same scope) Change-Id: I67c48084a6ee2a104ffff2b5a986d24a51ee49e1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12582 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06intel/fsp_rangeley: change non-existent config options to #definesMartin Roth
Kconfig symbols CONFIG_ACPI_INCLUDE_PMIO and CONFIG_ACPI_INCLUDE_GPIO were never added to the coreboot codebase when the Rangeley code was brought in from Sage. These symbols disabled ACPI code that was unused because it caused dmesg warnings due to conflicts with drivers trying to claim the same addresses as the ACPI code. Because it could be used on some other platforms, it was left in instead of being completely removed. - Change the Kconfig symbol names to simple #defines in the mainboard code. - Add the #defines along with comments to the reference platform. - Hook everything together in dsdt.asl - Update new mainboard littleplains the same way. Change-Id: I1f62157c6e447ea9b7207699572930e4711fc3e0 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12552 Reviewed-by: David Guckian <david.guckian@intel.com> Tested-by: build bot (Jenkins)
2015-12-06Remove #ifdef checks on Kconfig symbolsMartin Roth
In coreboot, bool, hex, and int type symbols are ALWAYS defined. Change-Id: I58a36b37075988bb5ff67ac692c7d93c145b0dbc Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12560 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06amd/pi/00660F01: Remove 'PER_DEVICE_ACPI_TABLES'Martin Roth
The PER_DEVICE_ACPI_TABLES Kconfig symbol is no longer used as it was removed in commit 83f81cad (acpi: Remove monolithic ACPI) Change-Id: Ie6ba252f6e7d33da9d4500f1201367f116e4c505 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12554 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-06hp/pavilion_m6_1035dx: Fix IASL warning - Missing _HID objectMartin Roth
- Add System board _HID object. - Remove Kconfig default disabling IASL warnings as errors Fixes warning: dsdt.aml 64: Device (MB) { Warning 3141 - ^ Missing dependency (Device object requires a _HID or _ADR in same scope) Change-Id: I4fa6ab2a6744d58ded8b0feb361e002d90e11474 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12532 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06Rangeley: Change A, A, A, A INT routing to A, A, A, BMartin Roth
Devices that have their interrupt routing set to A, A, A, A don't get any interrupt values assigned because that series evaluates to 0. The code that sets the interrupt values checks to make sure a value is set by verifying that it's not 0. On Bay Trail, these are all single-function graphics devices, so by changing one of the unused interrupt lines from A to any other value, it assigns the values correctly. This issue did not affect ACPI interrupt routing. This is just a workaround, and the root issue still needs to be fixed. Change-Id: I4e6fe56084cbe86b309da15d61b296f1936458ec Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12630 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06fsp_baytrail: Change A, A, A, A IRQ routing to A, A, A, BMartin Roth
Devices that have their interrupt routing set to A, A, A, A don't get any interrupt values assigned because that series evaluates to 0. The code that sets the interrupt values checks to make sure a value is set by verifying that it's not 0. On Bay Trail, these are all single-function graphics devices, so by changing one of the unused interrupt lines from A to any other value, it assigns the values correctly. This issue did not affect ACPI interrupt routing. This is just a workaround, and the root issue still needs to be fixed. Change-Id: I78866e3e0079435037e457a4fb04979254b56ee2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12629 Tested-by: build bot (Jenkins) Reviewed-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06southbridge/intel/fspi89xx: Don't include common/firmware makefileMartin Roth
The folder southbridge/intel/common/firmware is already being included so does not need to be added a second time here. Change-Id: I60d795a60c772547278a5a5e0c9a023a93f90417 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12636 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06fsp_model_406dx: use external microcode .h files for rangeleyMartin Roth
The microcode for the Rangeley chip is supplied as .h files in the Rangeley FSP POSTGOLD4 package. When the rangeley microcode gets put into the blobs directory, this can be reverted and the binary file put into the makefile. Change-Id: I30e7436f26a247bc9431f249becfa5fe8c581be7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12335 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06intel/eagleheights: Fix IASL warningsMartin Roth
The eagleheights platform had 3 warnings: The SIO device needs an _ADR object to specify the address in addition to the operating region. Not all the paths through the _OSC method returned a value. According to the ACPI spec (5.0 & 6.0), bit 2 needs to be set for an unrecognized GUID. dsdt.aml 341: Device(SIO) { Warning 3141 - ^ Missing dependency (Device object requires a _HID or _ADR in same scope) dsdt.aml 140: Method (_OSC, 4) Warning 3115 - ^ Not all control paths return a value (_OSC) dsdt.aml 140: Method (_OSC, 4) Warning 3107 - ^ Reserved method must return a value (Buffer required for _OSC) - Remove Kconfig default disabling IASL warnings as errors. Change-Id: Iab52f19b96468e142b06430d99ba1d9f367d126e Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12522 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-04google/oak: Add timestamps in romstageYidi Lin
BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: Idf74265c9c1ab3a1a74fd18dfd289fccad25177e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 569c433886b19cd08d168e995bf34156c2ba6963 Original-Change-Id: I07fda6a0719d49e2c07249276ae2cc0b57fdfeda Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292660 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12610 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-04mediatek/mt8173: Add APIs for PMIC GPIO controlBiao Huang
BRANCH=chromeos-2015.07 BUG=none TEST=verified on Oak rev3 Change-Id: Ied991f13b73e70b91cc267222f351b588df8df66 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4bc08ce28611d8b940642483c09614d2b8205c1f Original-Change-Id: If78e154ff7f553f65aa44d370820cc8c7f829c96 Original-Signed-off-by: Biao Huang <biao.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/297224 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12609 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-04mediatek/mt8173: Add mt6391 PMIC driverhenryc.chen
BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: I2b9e1fc16183a29ba308313d347f2f0e948e96a7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ee56cab3b5c04838af80690c21d3aa160d71501a Original-Change-Id: I2eaa0a406c29b7c9012e3c9860967fc3f27a48a5 Original-Signed-off-by: henryc.chen <henryc.chen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292669 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12608 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-04esd/atom15: import esd atom15 boardMichael Tasche
This patch adds esd atom15 board with Intel Atom E3815 SoC. Change-Id: I430a40ad8ab3316d34ec5567329370f69db3f15e Signed-off-by: Michael Tasche <michael.tasche@esd.eu> Reviewed-on: https://review.coreboot.org/12632 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-04intel/minnowmax: Fix IRQ connection for legacy uart at 0x3f8Michael Tasche
The E38xx legacy uart fires IRQ4, not IRQ3. PCI based IRQ A is switched from IRQ4 to IRQ3, to get a working IRQ for the legacy uart. Change-Id: Ibc8e824c92bf1b9a92594ddc5d8a06726c9f1744 Signed-off-by: Michael Tasche <michael.tasche@esd.eu> Reviewed-on: https://review.coreboot.org/12622 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2015-12-04northbridge/amd/amdht: Reduce excessive romstage array sizeTimothy Pearson
Change-Id: Ibcdf5d3927375da5cb72987ae83eaaa789ab9a70 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12573 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-04arch/x86/bootblock_normal: Update to use fewer registersMartin Roth
- Move initialization of entry to later in main. - Make boot_mode an unsigned char - no need to use int. - Remove unnecessary variable filenames. - Only get and try to boot fallback once. Change-Id: I823092c60dd8c2de0a36ec7fdbba3e68f6b7567a Test: compiled. Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12574 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-04cbfs: Fix typo in cbfs_prog_stage_load()Julius Werner
The proper return value to signal an error from cbfs_prog_stage_load() is -1, not 0. Change-Id: Ie53b0359c7c036e3f809d1f941dab53f090b84ab Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12633 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-12-04braswell/skylake: Add FspUpdVpd.h to fix compilationStefan Reinauer
Imported from cros repo 18ae19c Change-Id: Ib88ac9b37d2f86d323b9a04cb17a5a490c61ff5b Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/12467 Reviewed-by: Hannah Williams <hannah.williams@intel.com> Tested-by: build bot (Jenkins)
2015-12-04mainboard/biostar/am1ml: Force basic SPI read modeSergej Ivanov
This patch force AGESA to use basic SPI read mode. Without it board hangs during spi configure if W25Q32 chip is used. Change-Id: I3e17cd21702626be5061d2fc14adc0c22f167efb Signed-off-by: Sergej Ivanov <getinaks@gmail.com> Reviewed-on: https://review.coreboot.org/12580 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-03intel/mohonpeak: Change SEABIOS_MALLOC_UPPERMEMORY to config_seabiosMartin Roth
Instead of the SEABIOS_MALLOC_UPPERMEMORY option, use a saved SeaBIOS .config file to do the same thing. Change-Id: I29110a382b7770329ef938876426e571fbbbb339 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12569 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-12-03google/oak: Add board_id() and ram_code() implementationCC Ma
BRANCH=none BUG=none TEST=Oak build pass Change-Id: Ic2fd9b2ec0592d1f7195d72c60dab15961de0a9e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4d0b00a779b87b0b625cc2bccd8f7470b79e6410 Original-Change-Id: Id9f17d64e9e30946817b86ec8cdfe67ea3dbc798 Original-Signed-off-by: CC Ma <cc.ma@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292675 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12607 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03google/oak: Implement the code which reads GPIOs for ChromeOS.Yidi Lin
BUG=none BRANCH=none TEST=emerge-oak corebootk Change-Id: Ic1a0d640cac7fd98acd06d619736303fa449c0a1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ce465e8cbdf6465c072e476a91a400d78c959218 Original-Change-Id: Iade51db02f45264fdffe387e0563b60e637c0710 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292674 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12606 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03google/oak: Initialize the necessary pinsBiao Huang
BRANCH=none BUG=none TEST=verified on Oak rev2 & rev3 Change-Id: I35776f5bdf54243236afba860ae8e9117a160cde Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b46bd9a079107ab78964f7e39582b3b5c863b559 Original-Change-Id: I6696972d07adbf3da5967f09c1638bb977c10207 Original-Signed-off-by: Biao Huang <biao.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292673 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12605 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03google/chell: update dptf TSR1 & TSR2 critial pointsWisley
update dptf TSR1 & TSR2 critial points from 70 to 75 TSR1 & TSR2 are reach 68 degree that is close to 70 degree afer SVPT test, change the point will avoid to trigger critial in our factory run in test BRANCH=none BUG=none TEST=build and boot chell DUT Change-Id: Ie5b8b24d82e929a7bd254967b70b61fda2c8bd0a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cf29fee19edf425010cc76af95b7a8e73a3d82bb Original-Change-Id: Idb9dd77432cfd246c1c612e52c6f945352e265ca Original-Signed-off-by: Wisley Chen <Wisley.Chen@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313967 Original-Commit-Ready: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Chen Wisley <wisley.chen@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Chen Wisley <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/12604 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03mediatek/mt8173: Add GPIO driverBiao Huang
BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: I54755d81144b27cc9a674434609b2d99f1d486ec Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d88a3ed43ad32e245e54a9599fb8667ce288217b Original-Change-Id: I1142091650c0de2207c7635031aa7edfe487ad88 Original-Signed-off-by: Biao Huang <biao.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292672 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12603 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03mediatek/mt8173: move PRERAM_CBFS_CACHE from SRAM_L2CYidi Lin
L2C will be released after DRAM is initialized. Move PRERAM_CBFS_CACHE from SRAM_L2C to ensure that it can be switched correctly. BRANCH=none BUG=chrome-os-partner47952 TEST=none Change-Id: I255a0116148777d384dda43682365a5e2375cb5d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 19fcc170e57da514aee9e22289619729ddc2f792 Original-Change-Id: If3d9c1ef05dee0a10ee9151b63b8fd92cc9def51 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313888 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12602 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03cbfs_spi: Initialize spi_flash when initializing cbfs_cacheMary Ruthven
Most devices do not use SPI before they initialize CBMEM. This change initializes spi_flash in the CBMEM_INIT_HOOK to initialize the postram cbfs cache so it is not overwritten when boot_device_init is called later. BUG=chromium:210230 BRANCH=none TEST=confirm that the first cbfs access can occur before RAM initialized and after on panther and jerry. Change-Id: If3b6efc04082190e81c3773c0d3ce116bb12421f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0ab242786a16eba7fb423694f6b266e27d7660ec Original-Change-Id: I5f884b473e51e6813fdd726bba06b56baf3841b0 Original-Signed-off-by: Mary Ruthven <mruthven@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/314311 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12601 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03intel/kunimitsu: Coreboot GPIO changes for FAB 4.Saurabh Satija
This patch adds GPIO mappings for PCH_BUZZER, AUDIO_DB_ID, AUDIO_IRQ and BOOT_BEEP. BUG=chrome-os-partner:47513 BRANCH=none TEST=Built for kunimitsu but not verified on Fab 4. Change-Id: I0172df3aa2a5c4bfc24422aa0bfb7e5f677d37c9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ba66bef6d402a1040f0f13bc828de400bc6371b7 Original-Change-Id: I1f2ed8fc283883a523a77e07de14ed90057b719b Original-Signed-off-by: Saurabh Satija <saurabh.satija@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311806 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/12600 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03google/glados: Disable kepler deviceDuncan Laurie
Disable the kepler device to save power and enable S0ix testing. It has been disabled in the ME image and was not working anyway.. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot on glados Change-Id: I6640c7a09d418ba4b4de6f16138c124436dd8758 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6490769a32539cb6ef429717f021519c152a4a54 Original-Change-Id: If6e384dd2218c6a110747a489329a59fa6433c02 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/313827 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12599 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-12-03google/chell: Update mainboard for EVTDuncan Laurie
- Disable kepler device, it is removed and was not used on proto anyway. - Enable GPP_D22 as GPO to control I2S2 buffer for bit-bang PDM. - Disable HS400, this is breaking some devices on proto boards and is being disabled to reduce risk for EVT build. - Change Type-C USB2 port drive strength. BUG=chrome-os-partner:47346 BRANCH=none TEST=build and boot on chell proto Change-Id: Icf31f08302c89b2e66735f7036df914c0a0b9e8c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d00abc12efa69a99e6b0272228f52fb29e6b9180 Original-Change-Id: I63bda0b06c7523df9af9aed9b82280133b01d010 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/313825 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12598 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-11 18:13:22 +0000