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2017-10-31x86/lapic: Use the existing lapicid() functionMarc Jones
coreboot has a lapicid() function, so use it. Change-Id: I7f536c229f271674c34d722b5db96ce665b720f1 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-29LB_TAGS: change the value of CB_TAG_MAC_ADDRS to 0x33Ronald G. Minnich
When building the Go version of cbmem I found that LB_TAG_MAC_ADDRS has the same value as LB_TAG_VERSION_TIMESTAMP. I am guessing that this tag was little used. In any event, move it forward to 0x33. Change-Id: I038ad68e787e56903a2ed9cb530809a55821c313 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/22218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-29cpu/intel/model_1067x: Select UDELAY_LAPICArthur Heymans
This was moved out of northbridge/gm45 but was accidentally? commented out in c5d972d073c "Move select UDELAY_LAPIC from nb/gm45/Kconfig to cpu/model_1067x/Kconfig" The intel eagleheights mainboard also uses UDELAY_LAPIC with this change and is untested. Change-Id: I70e51fa50935baf187cef60f2e636251b40d6475 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22172 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-29nb/intel/i3100: Don't select UDELAY_IOArthur Heymans
This partially reverts 2510e2aa "northbridge/intel/i3100: Unify UDELAY selection" which moved all supported boards from UDELAY_TSC to UDELAY_IO. Since UDELAY_IO is the default this changes nothing. Change-Id: I42856e5929a7ba047987414a25cd0ae9712434a7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22173 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-29arch/x86: Restore forwarding table on resume for non EARLY_EBDA_INITFurquan Shaikh
In commit c06a3f72 (arch/x86: initialize EBDA in S3 and S0/S5 path), BDA and EBDA are wiped in the resume path. It results in coreboot forwarding table address being wiped out since it is stored in the BDA. This issue was resolved for platforms using EARLY_EBDA_INIT in commit f46a9a0d (arch/x86: restore forwarding table on resume for EARLY_EBDA_INIT). However platforms that do not use EARLY_EBDA_INIT still run into the same issue and hence cbmem does not work on resume. This change fixes the issue by using the stash/restore of forwarding table address for all platforms using BDA. BUG=b:68412690 TEST=Verified that cbmem works on S3 resume for coral. Change-Id: I42ae2ccb0b4ce8e989b1032d82b9bb34d0d84db0 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-283rdparty/lib{hwbase,gfxinit}: Update to latest masterNico Huber
Simplifies our C interface function gma_gfxinit(), due to the following changes: * *libgfxinit* knows about the underlying PCI device now and can probe MMIO addresses by itself. * The framebuffer mapping is now completely handled inside the library where we validate that we neither overflow - the stolen memory, - the GTT address space, the GTT itself nor - the aperture window (i.e. resource2 of the PCI device) that we use to access the framebuffer. Other changes: * Fixes and a quirk for DP training. * Fix for DP-VGA adapters that report an analog display in EDID. * Fixes for Skylake support with coreboot. * DDI Buffer drive-strength configuration for Haswell, Broadwell and Skylake. * `gfx_test` can now be run from X windows (with glitches). * Compatibility with GCC 7 and SPARK GPL 2017. TEST=Booted lenovo/t420 and verified that everything works as usual. Change-Id: I001ba973d864811503410579fd7ad55ab8612759 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-28drivers/intel/gma: Put gma_gfxinit() into its own headerNico Huber
The current header `i915.h` is too invasive to be used everywhere where we want to use *libgfxinit*. Change-Id: Iba57256d536e301e598d98182448d2daa1bf9a89 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-28lib: Prepare for libhwbase' generated config fileNico Huber
Add new libhwbase options and add a class for files generated during build. This follows the same pattern as for libgfxinit. Change-Id: Ie5b84992fa687e4e94b6d959a64086c638f66eb8 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-28mainboard/google/Kahlee: Combine BiosCallOuts filesMartin Roth
There's no need to have these separated. BUG=b:64932381 Test=Build & Boot Change-Id: I22898d3bf95d5e9a8fc2643bfccae1e2f5b29e44 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-27soc/intel/apollolake: Switch to common p2sbLijian Zhao
Using common p2sb driver instead of private one. TEST=Boot up into OS, and read back registers through PCR by iotools, return is not 0xffffffff. Change-Id: I30f3ef7bc37a8cb268af6fe2e4da3ec835c17633 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-27soc/intel/cannonlake: Use common p2sb driverLijian Zhao
Add common p2sb driver support. TEST=Boot up into OS and read back pcr mmio address by iotools, return is not 0xffffffff. Change-Id: Ida66663e6daabfcb94d7e3224d75b118fc7cf829 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-27intel/common/p2sb: Add common p2sb driverLijian Zhao
Add common p2sb device driver that will use fixed resource instead dynamic assigned by PCI enumeration. TEST=None Change-Id: Ie3f7036a5956e3db1662678aaf43023ff79ae10e Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22189 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-27soc/amd/common: Remove agesa_LateRunApTask() callbackMarc Jones
agesa_LateRunApTask() is not a callback, but a AGESA call. This is a mistake in the AGESA spec and the function is in the wrong section. bug=b:66690176, b:67210418 branch=none test=none Change-Id: I900e7db13a58e73a7b054e06088bc77c89445876 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-10-26soc/intel/cannonlake: Add support for C state and P stateShaunak Saha
This patch adds the C state and P state configurations for cannonlake soc. TEST = Boot and test the CPU states for all the cores are present in "powertop" tool output. Change-Id: I4ba156354f87646b25d0f9114ebf0583eedf72df Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/21891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-26soc/intel/cannonlake: remove duplicate power_state migrationPatrick Georgi
Common PMC code comes with its own. Change-Id: Ic055f046a2da1c56af4cc7936602d6191ffe7eef Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/22182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-26purism/librem_skl: add new variant Librem 15 v3Matt DeVillier
Add new board librem15v3 as a variant of the librem_skl baseboard. Changes from the librem13v2: - Change board name and version - Change GPIO A18, A19, A20, D9, D10 and D11 from NC to GPIO - Enable PCI device 1c.4 - Change USB port definitions in devicetree TEST: build w/SeaBIOS, boot PureOS on Librem 15 v3 hardware Change-Id: I7c762a34f5b961c908e4a29ec331da4b0dea9986 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22048 Reviewed-by: Youness Alaoui <snifikino@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-26soc/intel/apollolake: avoid double accounting for power statePatrick Georgi
intel/common's pmclib already keeps track of the power state (since commit f073872e22728fe8ade85022740af95cc129e9a5 and doing it twice can mess up the data that ends up in cbmem (and from there, everything else), so don't. BUG=b:67976359 BRANCH=none TEST=builds Change-Id: I69c804a2a3bee43add940d8c827b7250f2fe9024 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/22179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-26purism/librem13v2: convert to variant setupMatt DeVillier
Convert the Purism Librem13v2 board to a variant setup, in preparation of adding the librem15v3 as a new variant. The 13v2 and 15v3 are nearly identical, so this minimizes new code to add support for the latter. Change-Id: I5d648cdb8f63c03de5474253203b3d0853673294 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22047 Reviewed-by: Youness Alaoui <snifikino@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-25soc/intel/apollolake: Fix broken GNVS offset for chromeosFurquan Shaikh
Change 03a235(soc/intel/apollolake: Add GNVS variables and include SGX ASL) added new GNVS variables but did not adjust the unused array size and thus broke chromeos offset. This change fixes the above issue by reducing the size of unused array. BUG=b:68254376 TEST=Verified that chromeos offset is correct. crossystem is able to read all variables. Change-Id: I279bfc4c702e46b88c1c7a067a24326ff8fed368 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22177 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-25soc/intel/skylake: Fix broken GNVS offset for chromeosFurquan Shaikh
Change 90ebf9 (soc/intel/skylake: Add GNVS variables and include SGX ASL) added new GNVS variables but did not adjust the unused array size and thus broke chromeos offset. This change fixes the above issue by reducing the size of unused array. BUG=b:68254376 TEST=Verified that chromeos offset is correct. crossystem is able to read all variables. Change-Id: I5f76f5bba4f0f50a23a863450743385ad2a82b2b Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22176 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-25superio/acpi/pnp.asl: Fix PNP_READ_DMA/PNP_WRITE_DMA macrosKeith Hui
These macros, broken since day one, should CreateByteField instead of CreateWordField. Without the fix, any ASLs that try to use it will fail to compile with a "ResourceTag smaller than Field" warning. Change-Id: Ieeb509aece8836785998b23fdc805a747d40a77a Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/22066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-24mainboard/intel/cannonlake_rvp: Enable variant gpio configurationJohn Zhao
This patch refers to variant_gpio_table for board gpio configuration. Change-Id: If5b4c20ceccb32fc1ab4246482d8fecb491777c4 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2017-10-23soc: Add Kconfig for each soc vendorChris Ching
Allows explicit ordering for vendors that share a common configuration that must be sourced last. The issue is that chips in soc/{amd,intel}/[ab].* will be able to override defaults set in this file, but Kconfig files that get sourced later (soc/amd/[d-z].*) will NOT be able to override these defaults. Note: intel and amd soc chips now need to be added manually to the new Kconfig file BUG=b:62235314 TEST=make lint-stable Change-Id: Ida82ef184712e092aec1381a47aa1b54b74ed6b6 Signed-off-by: Chris Ching <chingcodes@google.com> Reviewed-on: https://review.coreboot.org/22123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-23mb/sapphire/pureplatinumh61: Remove S3 resume delayNicola Corna
It seems that recent changes in coreboot have fixed the raminit issues on this board; the workaround of 10 ms delay after the S3 resume is not needed anymore and can be removed. Change-Id: If8fb97ecf3eb797f53270a053201fafd32031678 Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/21485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-23drv/intel/gma/opregion: fix opregion version for WindowsMatt DeVillier
Although Intel's current spec[1] shows the OpRegion structure version as being the top 16 bits of the field, Intel's Windows drivers require the OpRegion structure version to be in the top 8 bits of the field when not using a VGA BIOS (eg, NGI or GOP driver). As the Linux i915 driver only checks that the version is >= 2, there is no change in functionality there. This change effectively matches Intel's implementation in TianoCore, where the version is set to 0x0200 << 16. [1] https://01.org/sites/default/files/documentation/skl_opregion_rev0p5.pdf TEST: Boot Windows [8.1,10] in UEFI mode w/GOP graphics init and Legacy mode with libgfxinit, observe Intel GPU driver functional. Change-Id: Ic2903ee4829689ec4117aec93dce0b87cec6f313 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-10-23purism/librem13v2: migrate from FSP 1.1 to 2.0Matt DeVillier
Migrate the Librem13v2 from using FSP 1.1 to the public/GitHub FSP 2.0 Skylake/Kabylake release: - select FSP 2.0 in Kconfig - adjust romstage/ramstage functions as required - refactor pei_data functions - remove VR_RING domain from devicetree (unsupported in FSP 2.0) - add SataSpeedLimit parameter to work around power-related issue when operating at SATA 6.0Gbps speed TEST: build/boot Librem13v2, observe successful boot, lack of SATA-related errors in dmesg. Change-Id: Iedcc18d7279409ccd36deb0001567b0aa5197adf Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-23soc/intel/cannonlake: Increase stack size from 4KiB to 8KiBJohn Zhao
Backtracking stack used BEFORE each function call: 1. cbfs_boot_locate(&file_desc, "vbt.bin", NULL): 4104 (stack overrun) 2. locate_vbt: 4068 3. vbt_get: 4036 4. platforms_fsp_silicon_params_cb: 3924 5. do_silicon_init(&fsps_hdr): 3684 (3684-1092=2592 due to fsps) 6. fsp_silicon_init: 1092 Increase the stack size from 4kiB to 8kiB to prevent stack overrun. TEST=No stack overrun is observed and it boots to OS properly. Change-Id: I7e458b4489cea32449f197621ec81009ea7dd0bd Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21977 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-23mainboard/google/coral: Add USB2 phy setting override for Astronautren kuo
In order to pass type C USB2 eye diagram for sku Astronaut, USB2 port#1 PHY register needs to be overridden. sku ID:0,1 Astronaut (USB) port#1: PERPORTPETXISET = 7 PERPORTTXISET = 2 sku ID:61,62 Astronaut (LTE) port#1: PERPORTPETXISET = 7 PERPORTTXISET = 5 BUG=b:68120012 BRANCH=master TEST=emerge-coral coreboot chromeos-bootimage Change-Id: Icf5c9e5f4dae15630ec4d6ca6648cae78ca910c6 Signed-off-by: Ren Kuo <ren.kuo@quantatw.com> Reviewed-on: https://review.coreboot.org/22135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-22nb/intel/pineview: Port ACPI opregion to pineviewPatrick Rudolph
Port the ACPI opregion implementation that resides in drivers/intel/gma to older platforms. It allows to include a vbt.bin and allows GNU/Linux to load the opregion as ASLB is being set. Windows' Intel will likely ignore it as it relies on legacy VBIOS to be loaded at 0xc0000. Change-Id: Ifc9fc52d84dcbb0da577e61467ece8a48752f44b Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/21775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-22superio/ite/common: Make PECI a thermal modeVagiz Trakhanov
Instead of setting "peci_tmpin" in the devicetree, THERMAL_PECI is now a mode of TMPIN like THERMAL_RESISTOR and THERMAL_DIODE. Since the logic to set temperature offsets and limits is in the function that sets thermal modes, it makes sense to treat PECI as yet another mode. As of this commit, there are no boards that actually use peci_tmpin from ite/common. There are three boards that have a similar device tree option, but those boards use it8772f, which implements all superio functions on its own. The first user will probably be Gigabyte GA-Z77-DS3H. Change-Id: I39da50c124ad767f8681302733cf004622975e81 Signed-off-by: Vagiz Trakhanov <rakkin@autistici.org> Reviewed-on: https://review.coreboot.org/22076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-22superio/ite/common: Add temperature limitsVagiz Trakhanov
Add devicetree options to set temperature limits that are used to alarm user when temperature exceeds defined values. Audio alerts by superio are not implemented yet, but since limits are visible to userland, some software might use them as is. For instance, lm-sensors displays "ALERT" when temperature exceeds limits. Change-Id: I56e041fb78f518d6a9640dc2b3985459991242b9 Signed-off-by: Vagiz Tarkhanov <rakkin@autistici.org> Reviewed-on: https://review.coreboot.org/21844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-10-22superio/ite/common: Add temperature offsetVagiz Trakhanov
Add a devicetree option to set temperature adjustment registers required for thermal diode sensors and PECI. However, this commit does not have the code needed to make PECI interface actually use these registers. It only applies to diodes. As a temporary workaround, one can set both THERMAL_DIODE and peci_tmpin to the same TMPIN, e.g. TMPIN3.mode="THERMAL_DIODE" and peci_tmpin="3". PECI, apparently, takes precedence over diode, so the adjustment register will be set and PECI activated. Or simply use the followup patch, which makes THERMAL_PECI a mode like THERMAL_DIODE. I don't have hardware to test THERMAL_DIODE mode, but in case of PECI, without this patch I had about -60°C on idle. Now, with offset 97, which was taken from vendor bios, PECI readings became reasonable 35°C. TEST=Set a temperature offset, then ensure that the value you set is reflected in /sys/class/hwmon/hwmon*/temp[1-3]_offset Change-Id: Ibce6809ca86b6c7c0c696676e309665fc57965d4 Signed-off-by: Vagiz Tarkhanov <rakkin@autistici.org> Reviewed-on: https://review.coreboot.org/21843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-10-22soc/intel/cannonlake: Change max root port to 16Lijian Zhao
Cannonlake SOC support up to 16 PCI express root port. BUG=CID 1381813;1381814; Change-Id: I4df610e3fb01bd8e62be7e9c62144125f2a96c25 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-22security/vboot: Move vboot2 to security kconfig sectionPhilipp Deppenwiese
This commit just moves the vboot sources into the security directory and fixes kconfig/makefile paths. Fix vboot2 headers Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-22soc/intel/skylake: pass SataSpeedLimit param to FSP2Matt DeVillier
The Librem13v2 needs to set this parameter to work around power-related issues with some SATA devices. Change-Id: I7fcef36ec8662e18834394b72427a0633c6b7e92 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22045 Reviewed-by: Youness Alaoui <snifikino@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-22purism/librem13v2: Update microcode length in CBFSYouness Alaoui
Microcode blob has been updated, so update the length to match Change-Id: I46ac10e5c6cd6492c98a7034649797f301101abc Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-22purism/librem13v2: Fix USB settings and set OC pinYouness Alaoui
The USB settings were wrong in some places, or missing and the USB_OC values were taken from the schematics. Change-Id: I29b564a4161c486f5e8556b1726471bfa2351b7a Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/22043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-22purism/librem13v2: Update devicetree settingsYouness Alaoui
Disable SataDevSlp and update other values to match vendor/AMI firmware. Change-Id: I6f278be54b86450575c366d68bfa6a67575b0fdd Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-22purism/librem13v2: Change DRAM Rcomp/DQS valuesYouness Alaoui
The RComp values have been updated to match what is shown in the schematics. Extracting the Memory configuration blob from the original BIOS (A blob which contains the correct binary sequence matching the RComp values appears in object with GUID 2D27C618-7DCD-41F5-BB10-21166BE7E143), I could find and confirm the DQ and DQS mapping. Small code cleaning in romstage.c with no effect. Change-Id: I35c734269b365fd759e9bd56224a80a8a8df5a57 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/22041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2017-10-22purism/librem13v2: Add reading of serial number from CBFSYouness Alaoui
Check CBFS for 'serial_number' field, and use value if exists; otherwise use value set at compile time. Change-Id: I4b50f6310ca32b9dd372db075a5b5729e3b06619 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/22040 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-22skylake/me: Add debug output of HFST registersYouness Alaoui
The ME status is the interpretation of the status registers, but having the actual status registers printed is important and it doesn't hurt to show them. Change-Id: I6ef3401b36fedfa8aed14f4a62bdbec3d8c6d446 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/21960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-22google/kahlee: Add PSP to devicetree.cbMarshall Dawson
Add the missing device and ensure it shows up in the devicetree prior to PCI enumeration. Change-Id: Ia2c4ba1200422b36c533e86065a4fcd10c4b2722 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22055 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-22amd/gardenia: Add PSP to devicetree.cbMarshall Dawson
Add the missing device and ensure it shows up in the devicetree prior to PCI enumeration. Change-Id: I44c7df6a2be149ed61094f67ef1c578736e5b55c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-22soc/amd/common: Revert PI blob search hackMarshall Dawson
Remove the check for CONFIG_VBOOT when finding the binaryPI blob and rely on the cbfs search 100% of the time. The change was initially put in to avoid a hang when vboot presearched memory for the blob. The implementation now supports early cbmem init and cbmem_top() is careful to return 0 if DRAM has not yet been set up. As a result the hang no longer occurs and the hack may be removed safely. BUG=b:67747902 Change-Id: I1f38709fcce250b0902a639ebf0554219bc47cf8 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-22src/security: Add security kconfig stubPhilipp Deppenwiese
Change-Id: I965bf87d8673e22c088093f0fa17e93dbb9a00d9 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-22mb/google/link: Enable libgfxinitNico Huber
Beside the high-resolution eDP panel, it features a dual-mode mini-DP port. Change-Id: Iae60c1f930f5778ee3b5d9d19227168257e9ae06 Tested-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2017-10-22soc/amd/stoneyridge: Remove duplicate macros in pci_devs.hChris Ching
BUG=b:68046770 TEST=build Change-Id: Iea0df0dc7baa384cac45a300fdcc8d59f0aac798 Signed-off-by: Chris Ching <chingcodes@google.com> Reviewed-on: https://review.coreboot.org/22114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-22intel/i210: Set bus master bit in command registerWerner Zeh
There are still Ethernet drivers out there in the wild which expect that the master enable bit was set by firmware. A missing master enable bit will lead to a non-functional driver. Though it is clear the task of the driver to set this bit it is too late now. So work around this issue on firmware level...again! Change-Id: I677b22c643b73634b1a2129d948b991446e1f8fd Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/22036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2017-10-20kahlee: Set Kahlee GPEsMarc Jones
Add GPE configuration table. Remove GPE3 from the power button ASL and set the EC to GPE3(AGPIO22). Set the EC and PCIE/WLAN SCI GPIO signals. Set GPE ASL methods for: PCIE/WLAN 8h EHCI 18h XHCI 1fh Note EC GPE3 methods are in the EC ASL. BUG=b:63268311 BRANCH=none TEST=Test lidswitch powers the device on and off at the login screen. Change-Id: I27c880ee84b6797d999d4d5951602b654ede948e Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22096 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-20cr50_enable_update: Add printk before EC hibernateShelley Chen
Add printout before EC hibernates during a cr50 update to clarify that failure is due to EC rather than cr50. Ran into a situation where DUT shut down during cr50 update and the EC was the culprit. BUG=None BRANCH=None TEST=None Change-Id: I54813fec123de69604d1da4dfc65eaeb77d1662e Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/22120 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 07:22:42 +0000