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2019-12-17superio/aspeed/ast2400: Add AST2500 supportPatrick Rudolph
The AST2500 is similar to the AST2400, but it also supports ESPI mode. In ESPI mode the IRQ level must be 0 and UART3/UART4 aren't usable. Change-Id: Iea45740427ad56656040e6342f5316ec9d38122f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-12-17mb/google/rambi: add VBTs for variantsMatt DeVillier
Add VBTs for all rambi variants, extracted from VGA BIOS from stock firmware images using intelvbttool. Test: boot several rambi variants using MrChromebox edk2/master branch with Baytrail GOP driver and extracted VBTs. Change-Id: I401ae5accd852fc5211092a5944fc85871b642ae Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-17mb/google/jecht: Add VBTs for all variantsMatt DeVillier
Add VBTs for jecht variants, extracted from VGA BIOS from stock firmware images using intelvbttool, zero-padded to 0x11ff bytes to make the Intel BMP editor happy. Use a common VBT for all except tidus, since it differs from the others. Change-Id: I570bdb749ef7d49f41539074220bb16c9c100342 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-16src/soc/intel/cannonlake: Bump MAX_CPU from 8->12Edward O'Callaghan
This impacts boards: hatch (&variants) and drallion. Some variants like Puff can have up to 12 cores. coreboot should take the min() where MAX_CPU is the upper bound. Further to that, boards themseleves shouldn't be setting the MAX_CPUS, the chipset should be and so do that. BRANCH=none BUG=b:146255011 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I284d027886f662ebb8414ea92540916ed19bc797 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-12-16biostar/am1ml: Switch away from ROMCC_BOOTBLOCKSergej Ivanov
Switching was done by moving a SIO configuration and a clocks setup from 'romstage.c' to 'bootblock.c' TEST=Boots into Ubuntu Linux 16.04.6 without a problem. Change-Id: I7a972b531183b08af7b325bd686cf3eb7558082f Signed-off-by: Sergej Ivanov <getinaks@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-16device/pnp: use correct width type for pnp_info.functionFelix Held
Change-Id: Idbc1b37a8c98fe7fa24d8632e6a55c046e2d2869 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-12-16device/pnp: introduce and use PNP_SKIP_FUNCTIONFelix Held
-1 shouldn't be assigned to an unsigned variable, so use an otherwise unused constant here. Since 7 is the highest virtual LDN number, using 0xffff as PNP_SKIP_FUNCTION marker has no unwanted side effects. Change-Id: I5e31e7ef9dad5fedfd5552963c298336c533a5e9 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-12-16mb: Use fixed value in RcompTarget structureWim Vervoorn
Now RCOMP_TARGET_PARAMS is defined and used once in the definition of the RcompTarget structure. All other structures in these functions use a fixed value. Replace RCOMP_TARGET_PARAMS with fixed value. BUG=N/A TEST=build Change-Id: Ibe7c72c65975354433e9a0c613bda715eb782412 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37658 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-16vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v1433Aamir Bohra
The FSP-M/S/T headers added are generated as per FSP v1433. Change-Id: Iacb44204c3f7220a20ab3edc2163c97188014bbf Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37559 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-16soc/intel/tigerlake: Add FSP header and Fsp.fd file path for Jasper LakeAamir Bohra
Change-Id: I66d48206a4c1c31802e85c08ab935f81f10aadbc Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-12-16superio/ite/it8728f: remove unused LDN selection register defineFelix Held
Change-Id: Ie7a8af46a59c36b0dd62f227a6b53918c8fde7b8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37742 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-16soc/amd,{agesa,pi}/hudson: Have do_board_reset in all stagesKyösti Mälkki
Change-Id: I38a721c359ab7761c5a3ea79da0c159fd7f58970 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37711 Reviewed-by: Mike Banon <mikebdp2@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-16superio/ite: remove unused stdint.h include from header filesFelix Held
Change-Id: Ica1c9f0c92886a081ab69612174a8d1d467b0713 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-12-16mb/google/beltino: Add VBTs for all variantsMatt DeVillier
Add VBTs for beltino variants, extracted from VGA BIOS from stock firmware images using intelvbttool, zero-padded to 0x11ff bytes to make the Intel BMP editor happy. Use a common VBT for all except monroe, since it differs as it has a built-in display (being a Chromebase vs Chromebox). Change-Id: I82afb20a5648695c2cd568384a26839ab28be3da Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-16mb/google/slippy: Update VBT fileMatt DeVillier
Update VBT using file extracted from VGA BIOS from stock firmware image using intelvbttool, zero-padded to 0x11ff bytes to make the Intel BMP editor happy. Change-Id: I9f53e80305ec8de78a3d5c930224b394b5c8618a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37732 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-16mb/google/auron: add VBTs for variantsMatt DeVillier
Add VBTs for all auron variants, extracted from VGA BIOS from stock firmware images using intelvbttool, zero-padded to 0x11ff bytes to make the Intel BMP editor happy. Test: boot several auron variants with libgfxinit and Tianocore payload, ensure both internal and external displays as well as HDMI audio function properly under Linux (4.x/5.x). Change-Id: Ibc4eabfa5d02b4c08755cf52835b5df8c1291fea Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-16ec/google/chromeec/acpi: move PS2K under PCI0Matt DeVillier
Commit 77ad581ce [chromeec: PS2K node can't be under SIO node] moved the PS2K ACPI device from under the SIO device to under the LPCB, and while this fixed the keyboard under Windows for Skylake devices, it was insufficient for Baytrail and Braswell devices (and likely Apollo Lake/Gemini Lake too). Moving the PS2K device under PCI0 allows the PS2K to be functional under Windows for all Chrome-EC platforms. Test: build/boot various Chrome-EC devices from IVB, HSW, BDW, BYT, SKL, BSW, and KBL platforms, verify keyboard functional under both Linux (4.x and 5.x) and Windows 10. Change-Id: If773eea69dc46030b6db9d64c3855be49951d4c0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37542 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-163rdparty/fsp: Update to current master againNico Huber
We had to role the `fsp` submodule back for a minute due to a regression with the Coffee Lake binary. Intel silently mixed FSP 2.1 features into the Coffee Lake FSP which is supposed to be FSP 2.0. With the stack and heap usage partitioned for FSP using coreboot's stack (config FSP_USES_ CB_STACK), it works again. To make this even messier: We already selected this Kconfig option for Whiskey Lake, which is supposed to use the very same FSP binary. So with either submodule pointer, something was always broken :-/ Change-Id: Id2aa17aaa2c843dcc7e0fb28779d1e5948da83c9 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Mimoja <coreboot@mimoja.de>
2019-12-16arch/x86: Make X86 stages select ARCH_X86Arthur Heymans
Also, don't define the default as this results in spurious lines in the .config. TEST: Build all boards with where config.h differed with BUILD_TIMELESS=1 and remained the same Change-Id: Ic77b696f493d7648f317f0ba0a27fdee5212961e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31316 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-16drivers/intel/fsp1_1: Drop unused functionArthur Heymans
Change-Id: Ide336fb900360c446bffcc5ca31bf51e7746cae1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-16sc7180: clock: Add support for QUP DFSR configurationTaniya Das
Support configuring the qup dfsr registers. Tested: validated DFSR clock configuration and M/N/D values. Change-Id: I146ac7c2197606965265f2a770769312af76041e Signed-off-by: Taniya Das <tdas@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-12-16soc/intel/common/block/chip/Kconfig: Fix minor whitespaceHimanshu Sahdev aka CunningLearner
Change-Id: I662420e6e05a6489950c583dfd37df5826153214 Signed-off-by: Himanshu Sahdev aka CunningLearner <sahdev.himan@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: RONAK KANABAR <ronak199323@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-16mb/facebook/monolith: Add vboot-ro.fmd to support measured bootWim Vervoorn
Add an fmd file with a layout that allows configuring the system for measured boot without enabling verified boot. BUG=N/A TEST=tested on facebook monolith Change-Id: I85fc6bee3f28fa4454d43df0e8bd1e511e1d0caf Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37673 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-16mb/facebook/monolith: Remove % tag from fmd fileWim Vervoorn
cbfstool doesn't support % tag yet while this was in the fmd. Revert the fmd changes that use the % tag. BUG=N/A TEST=build Change-Id: I2dc8b8f56ee0890e01be3bed939ed922feb15e89 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-12-16mb/facebook/monolith/gpio.h: Update GPIO configurationWim Vervoorn
Update signal names and GPIO configuration. Remove unused GPE_EC_WAKE and EC_XXX_GPI defines. BUG=N/A TEST=tested on facebook monolith Change-Id: Iae5edb8418894a669ed49c2d78672d8957010f3c Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-12-16soc/intel/tigerlake: Pick correct pmc base reg from pch typeMaulik V Vaghela
Update PMC shadow register base address for Jasperlake Correct PCH detection logic based on PCH ids and return correct base address based on PCH detected since our code supports both tgl and jsl. Change-Id: Iea3311b3dc8dc3ee5ea54db1148f386c2a5dd563 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2019-12-16mb/g/drallion: Remove Wilco 1.0 CML variants from drallion codeMike Wiitala
Remove the sarien_cml and arcada_cml subdirectories from the drallion/variants directory. BUG=b:140068267 TEST=./build_packages --board=drallion Confirm that drallion still builds successfully. BRANCH=none Change-Id: I9648965ca222d4d68bf73738716ad1c93739b03f Signed-off-by: Mike Wiitala <mwiitala@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-12-15AGESA: Disable boards from buildKyösti Mälkki
As per the 4.11 release requirement, C_ENVIRONMENT_BOOTBLOCK=y is a mandatory feature, which most AGESA and binaryPI boards lack. Disable such platforms from the build for the time being. The Kconfig symbol has been flipped, ROMCC_BOOTBLOCK=n is the same mandated feature as C_ENVIRONMENT_BOOTBLOCK=y. If a platform does not reach ROMCC_BOOTBLOCK=n within a reasonable timeframe both the mainboard and the respective unused platform support code will get removed. Change-Id: I7fceb0370f7f4f5f52080277c5d21615d3ab3454 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-12-15drivers/mrc_cache: Redo indentingMarshall Dawson
Indent continuation lines of an if test farther than its "true" expression to be executed. Change-Id: I3dfa4049761095dcbb6797f1533d6a513e3b503c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-15asus/f2a85-m: switch away from ROMCC_BOOTBLOCKIdwer Vollering
Change-Id: I1d7127e2f9bd5bd9677feb2b0e686a854c4e3885 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37727 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-15mb/msi/ms7721: Don't rewrite pnp_{enter,exit}_conf_state functionElyes HAOUAS
Change-Id: Ib27c518fb5ce99e17be25b974ff5adc8c6b3f3a6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37570 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-15mb/roda/rk886ex: Don't rewrite pnp_{enter,exit}_conf_state functionElyes HAOUAS
Change-Id: Ie9918e5114bb880e37680a85eab2bd224b0b082c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-12-15mainboard/google/puff: Toggle on DqPinsInterleavedEdward O'Callaghan
BRANCH=none BUG=b:146172098 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: Ib2da3baace9255ef25c0f03390a064fd77ef9ae5 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2019-12-14Revert "{northbridge,soc,southbridge}: Don't use both of _ADR and _HID"Nico Huber
This reverts commit 01787608670adec26fcea48173e18395e51c790e. AMD: Dropping the _HID of PCI root bus doesn't work well and people started to notice the breakage. Intel: These platforms have a devicetree switch to choose between PCI and ACPI modes. In the former case we need _ADR, but in the latter _HID as the PCI devices are hidden. The conflicting use of _ADR and _HID still needs to be fixed before we can bump our IASL version. Change-Id: If7b52b9e8f2f53574849aa3fddfccfa016288179 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37710 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-14sb/intel/*: Remove romcc guardsArthur Heymans
These platforms now use a GCC compiled bootblock. Change-Id: I9a0139f497fe84860664195ed6584f90daecec16 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-14bootblock: Provide some common prototypesKyösti Mälkki
The split of bootblock initialisation to cpu, northbridge and southbridge is not specific to intel at all, create new header <arch/bootblock.h> as AMD will want some of these too. Change-Id: I702cc6bad4afee4f61acf58b9155608b28eb417e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-14asrock/e350m1: Switch away from ROMCC_BOOTBLOCKDenis 'GNUtoo' Carikli
Change-Id: Ie14db10b6a72e19ac67254ca8f95bcf6ac8af8d3 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@cyberdimension.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-12-13security/vboot: Ensure firmware body size is respected againJulius Werner
CB:36845 simplified how coreboot finds the RW CBFS after vboot has and eliminated a layer of caching. Unfortunately, we missed the fact that the former cached value didn't exactly match the FMAP section... it was in fact truncated to the data actually used by vboot. That patch unintentionally broke this truncation which leads to performance regressions on certain CBFS accesses. This patch makes use of a new API function added to vboot (CL:1965920) which we can use to retrieve the real firmware body length as before. (Also stop making all the vb2_context pointers const. vboot generally never marks context pointers as const in its API functions, even when the function doesn't modify the context. Therefore constifying it inside coreboot just makes things weird because it prevents you from calling random API functions for no reason. If we really want const context pointers, that's a refactoring that would have to start inside vboot first.) This patch brings in upstream vboot commit 4b0408d2: 2019-12-12 Julius Werner 2lib: Move firmware body size reporting to separate function Change-Id: I167cd40cb435dbae7f09d6069c9f1ffc1d99fe13 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-12-13soc/intel/common: Add PCI device IDs for CMP-HGaggery Tsai
This patch adds PCI device IDs for CMP-H. TEST=build coreboot.rom and boot to the OS Change-Id: Ia7413f75757c64b389a39d6e171f88eb61036c58 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-12-13superio/*: Don't use conf_mode directlyPatrick Rudolph
Use the functions defined in device/pnp.h instead of using the conf_mode directly. This will make future refactoring easier. Change-Id: Ibb94d86b3ee861f44cded469ff58b545dd7311fd Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-12-13gizmosphere/gizmo: Switch away from ROMCC_BOOTBLOCKKyösti Mälkki
No special treatment required for bootblock. Change-Id: I1a08d4da94ab34bf62fbfdd2cb66f2b44a847916 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37452 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-13pcengines/apu1: Switch away from ROMCC_BOOTBLOCKMichał Żygowski
TEST=boot PC Engines apu1 with C bootblock patch and launch Debian with Linux kernel 4.14.50 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I36af6d3871a57f462a7508745663d9759de1c47d Reviewed-on: https://review.coreboot.org/c/coreboot/+/37332 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-13sb/amd/cimx/sb800: Postpone Sb_Poweron_Init() callKyösti Mälkki
With LPC decode enables explicitly set in C env bootblock, this call can be delayed to happen before AMD_INIT_RESET. Change-Id: I3a28eaa2cf70b770b022760a2380ded0f43e9a6f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-12-12vboot: update secdata naming schemeJoel Kitching
secdata -> secdata_firmware secdatak -> secdata_kernel BUG=b:124141368, chromium:972956 TEST=make clean && make test-abuild BRANCH=none Change-Id: Ie2051de51c8f483a8921831385557fad816eb9fb Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-12-12vc/amd/pi: Fix typoPatrick Georgi
Change-Id: Ic3d1b9f90c6ed3d85ff209f433de9ab939d760a6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37676 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-12mb/google/nocturne: adjust VBT boot resolutionMatt DeVillier
On nocturne, the VBT specifies that the native panel resolution (3000x2000) is to be used by FSP/GOP init, which makes payload and grub menus extremely difficult to read. Change the default POST resolution specified by the VBT to 1500x1000 instead (200% scaling) which is much more legible. Test: build/boot nocturne with GOP init and Tianocore payload, observe menu text is actually readable. Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Change-Id: I767a2b8319c7673e3460acfad534140409bf1d57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37621 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-12AGESA, binaryPI: Remove generic device for SPD eepromsKyösti Mälkki
These entries have no functional purpose, followup work will disallow chip entries that do not link in the respective driver. Change-Id: Ieab695022d0dd2f2671f9058db97bdd6fb29a10d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-12nb/{haswell,i945,sandybridge}: Drop outdated commentElyes HAOUAS
'e7525/northbridge.c' does not exist anymore. Change-Id: I5520760f59a3c6f89afb1360b12bd9763fba562a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37653 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Mimoja <coreboot@mimoja.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-12mb/google/hatch/variant/akemi: Increase Goodix touch screen reset delay timePeichao Wang
Confirmed with Goodix team, so increase reset delay time from 120ms to 150ms. BUG=b:144267684 TEST=FW_NAME="akemi" emerge-hatch coreboot chromeos-ec chromeos-bootimage Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I4ff95ac89314fc031620ca28e4f6e6e26cdef3f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37544 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-12soc/mediatek/mt8183: skip fast calibration for high frequency of TX RX windowHuayang Duan
For low frequency (e.g., 1600 or 2400 Mbps) we can do fast calibration for TX and RX window. However, for high frequency (e.g., 3200 or 3600 Mbps) a full calibration is needed. BUG=b:80501386,b:142358843 BRANCH=kukui TEST=Boots correctly on Kukui Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: I00d563ece4cf91ef5e8e12b6cf7f777849375a24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36921 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 21:23:05 +0000