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2018-01-17cpu/intel/speedstep: Fix the PNOT ACPI methodArthur Heymans
The PNOT method never notifies the CPU to update it's _CST methods due to reliance on inexisting variable (PDCx). Add a method in the speedstep ssdt generator to notify all available CPU nodes and hook this up in this file. The cpu.asl file is moved to cpu/intel/speedstep/acpi since it now relies on code generated in the speedstep ssdt generator. CPUs not using the speedstep code never included this PNOT method so this is a logical place for this code to be. Change-Id: Ie2ba5e07b401d6f7c80c31f2bfcd9ef3ac0c1ad1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-17ec/h8: Store PWRS and notify CPU on AC power plug/unplug eventsArthur Heymans
PWRS is is the power source gnvs. Notifying CPU is needed to change P- and C-states on these events. Change-Id: I0818d10474523fb14f7ba7cfbf61166b89442083 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-17soc/intel/apollolake: Fix prev_sleep_state on G3 exitHannah Williams
If waking up from S5, then prev_sleep_state was correct but not when waking up from G3. Change-Id: I39011a0846f042d224a7cd65f736e749acc8ec75 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/23221 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-17vx900: decode the whole ROMLubomir Rintel
Fixes supports for flash ROMs larger than 512K, such as the 1M one in HP t5550 Thin Client. Change-Id: I4d6287e130809c33dfbd40bce7913a95b4b3a9c7 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-17arch/x86/acpi_device: Provide macros for GPIO input with polarityFurquan Shaikh
Similar to ACPI_GPIO_OUTPUT, this change provides ACPI_GPIO_INPUT_* macros with ACTIVE_LOW and ACTIVE_HIGH polarity. Change-Id: I77da6ad2f04d7f7bb6774df35105bdbe963d87d3 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-17AGESA f15: Drop CAR teardown without POSTCAR_STAGEKyösti Mälkki
Change-Id: Ie5ff62ee1c7ca193ba841c5b2fb20940ec657625 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-17mb/google/nautilus: Add MIPI camera asl files for IMX258 and DW9807Andy Yeh
* Add IMX258 sensor entity * Add DW9807 VCM control entity * Enable CIO2 and IMGu in devicetree.cb TEST: Verified the MIPI camera function on DUT board Change-Id: Iebd41ac3631829bbb0b008761eb67c3db3e94638 Signed-off-by: Andy Yeh <andy.yeh@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/23056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-01-17mb/google/poppy: Move PMIC specific objects to appropriate scopeRizwan Qureshi
Right now the poppy baseboard camera topology allows to add maximum of 2 sensors. The sensors can be of different vendors. The current ASL code structure doesn't allow sensor customization. Moving PMIC specific objects from sensor objects to PMIC scope and having separate sensor ASL files will help in unbinding the PMIC and sensor objects and allow some customizations. BUG=None BRANCH=None TEST=Build and boot soraka, make sure both camera's are working fine and also verify that the generated DSDT looks fine. Change-Id: I63ae1a685b78bda212c5c48a4c2dc744164a3cb5 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/23168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-01-17mb/google/poppy: Split ports and endpoints config for CIO2Rizwan Qureshi
The variant boards can have a custom endpoints, splitting the ASL code aids customizing the endpoints as per the variant board setup. BUG=None BRANCH=None TEST=build boot soraka, verify that the cameras are working fine and generated DSDT tables are same as before. Change-Id: I5f1cded25bfb6a7baf18b211f9773dfecdc2f264 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/23167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-01-17soc/amd/common/block/pi: Fix AGESA heap deallocatorMarc Jones
The deallocation was always subtracting the header, even when it shouldn't. This caused problems for the allocator where buffer sizes were incorrect and freed and used buffers could collide. Fix the deallocation size. Clear deallocated concatinated buffer header memory. Fix the initial calculation of the total buffer size available to be allocated. BUG=b:71764350 TEST= Boot grunt. BRANCH=none Change-Id: I2789ddf72d662f24709dc5d9873741169cc4ef36 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/23284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-17AGESA f15 boards: Remove - using LATE_CBMEM_INITKyösti Mälkki
Boards that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. Removed boards: amd/dinar tyan/s2886 supermicro/h8scm supermicro/h8qgi Change-Id: I16be3b43fc0c48d58ed8b6667880c9571c6f5510 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/23274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-17soc/intel/cannonlake: Add option to select FSP_CARSubrata Banik
This patch provides an option for non-chrome devices to make use of FSP-T for performing cache-as-ram initialization. Majority of IOTG users are using FSP-T for CAR implementation and aren't able to select FSP_CAR Kconfig from SoC without conflicting with existing CAR config. TEST=Ensure that both the Chrome platform and non Chrome OS platform can select either CAR implementation based on Kconfig options FSP_CAR or CAR_NEM_ENHANCED. By default Chrome platform choose CAR_NEM_ENHANCED Kconfig and non Chrome platforms choose FSP_CAR by default. Change-Id: If565b649fe1c2abdbcf0a740c15db7253c084ae7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-16soc/intel/cannonlake: Program DMI PCR settingsLijian Zhao
According to CNL PCH BIOS spec (570374) 2.4.1, DMI cycle decoding needs to be programmed before it gets locked. Update lpc programming to add decode programming on DMI side as well. Also enabled io port 0x200 decoding by default. BUG=b.70765863 TEST=Apply changes and add chromeos EC decoding in mainboard devicetree.cb, then read back IO port in depthcharge cli and check that return is not zero. Change-Id: I6b8f393c92cbd0632fed86212ae384ff53c9f8c3 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-16soc/intel/apollolake: Set ACPI_FADT_LOW_PWR_IDLE_S0 for S0ixShaunak Saha
This patch sets the ACPI FADT flag ACPI_FADT_LOW_PWR_IDLE_S0 if S0IX is enabled for the platform. TEST= Boot to OS and check the ACPI_FADT_LOW_PWR_IDLE_S0 flag is set in FACP table. Change-Id: Ibb43d5c8024dcdf753416e4bd2a457991cc7a433 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/23095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-15Intel i82830 boards & chips: Remove - using LATE_CBMEM_INITMartin Roth
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: cpu/intel/socket_mFCBGA479 northbridge/intel/i82830 Mainboards: mainboard/rca/rm4100 mainboard/thomson/ip1000 Change-Id: I9574179516c30bb0d6a29741254293c2cc6f12e9 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-15Intel i3100 boards & chips: Remove - using LATE_CBMEM_INITMartin Roth
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: northbridge/intel/i3100 southbridge/intel/i3100 superio/intel/i3100 cpu/intel/socket_mPGA479M Mainboards: mainboard/intel/truxton mainboard/intel/mtarvon mainboard/intel/truxton Change-Id: Ic2bbdc8ceb3ba0359c120cf4286b0c5b7dc653bb Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-15Intel i5000 board & chips: Remove - using LATE_CBMEM_INITMartin Roth
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: northbridge/intel/i5000 Mainboards: mainboard/supermicro/x7db8 mainboard/asus/dsbf Change-Id: I6614c0033b4439d196f26819998d3f85e6d11c00 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-15Intel i855 board & chips: Remove - using LATE_CBMEM_INITMartin Roth
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: northbridge/intel/i855 Mainboards: mainboard/lanner/em8510 Change-Id: Ic9ba0ba7e2b6e602a5749cc531dd705c49e3f08d Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-15Intel sch board & chip: Remove - using LATE_CBMEM_INITMartin Roth
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: soc/intel/sch Mainboards: mainboard/iwave/iWRainbowG6 Change-Id: Ida0570988a23fd0d13c6fcbe54f94ab0668c9eae Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-15DMP Vortex86ex board & chip: Remove - using LATE_CBMEM_INITMartin Roth
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: soc/dmp/vortex86ex Mainboards: mainboard/dmp/vortex86ex Change-Id: Iee7b6005cc2964b2346aaf4dbd9b2d2112b7403f Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-15AMD GX2 boards & chips: Remove - using LATE_CBMEM_INITMartin Roth
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: cpu/amd/geode_gx2 northbridge/amd/gx2 southbridge/amd/cs5535 Mainboards: mainboard/amd/rumba mainboard/lippert/frontrunner mainboard/wyse/s50 Change-Id: I81c130f53bbfa001edbfdb7a878ef115757f620c Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-15mb/google/poppy/variants/nami: Enable elan touchpadvan_chen
BUG=b:71838954 TEST= 1. emerge-nami coreboot chromeos-bootimage 2. check touchpad function 3. evtest /dev/input/event5: Elan Touchpad Change-Id: I14471d1473a3b3ecf15aaf362b47874704cd3bf0 Signed-off-by: van_chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/23133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-15mb/lenovo/x200/dock.asl: Issue DOCK ACPI events based on Dock IDArthur Heymans
Some Dock events only need to happen based on the Dock Id (which functions as a presence detect GPIO). Inspired by vendor bios DSDT. This fixes undock ACPI events being issued when pulling out the power when docked or undocked (but still generates one when forcibly undocked) Tested on X200: pull power and see if undock events are generated in dmesg. Change-Id: I1eef971d49508bcd94d5d1cf2b70395b7cd80b1c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-15vx900: skip remap of high memory ranges if unnecessaryLubomir Rintel
If the DRAM does *not* actually overlap the PCI space, the remap code notices it is the case, but for some reason proceeds with the remapping, attempting to remap a negatively sized chunk. Bummer. With a single 1024M (two ranks of 512M) module: Nothing to remap Mem remapping enabled Remapstart 5120(MB) Remapend 6144(MB) Top of RAM 1024MB New top of RAM 2560MB Wrote remap map a0101 Mem remapping enabled Remapstart 4096(MB) Remapend 2560(MB) New top of memory is at 2560MB Needless to say, subsequent ram_resource() ruins the memory map for the OS -- Linux won't boot without a mem= argument and memtest quickly. TEST=memtest and Linux boot on HP t5550 with 1024M of memory Change-Id: Ic221723a26c5d1a03bf34c7722b0abe115f456ba Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-15vx900: map the SPI controllerLubomir Rintel
This is required for Flashrom to work well. Change-Id: Id756d86a7f3b34f816ea7a7ed78f159512f550d5 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-15vx900: fix format strings for DEBUG_RAM_SETUP=yLubomir Rintel
Change-Id: I990969cf1389c19032c4a0fafbdef45b9d6d1e8b Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-14mb/asrock/g41c-gs: Add IO decode range for SIO HWMONArthur Heymans
Change-Id: Ic02c3a6265f11c1571369bc04371d28b6f989736 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21464 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-14mb/asus/p5gc-mx/romstage.c: Remove unused IO decode rangesArthur Heymans
This source file was mostly copied from ga-945gcm-s2l but had different IO decode ranges. Change-Id: I54cb165000fad6984edf13fb33519fb9c9f0350f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-14mb/*/*/romstage.c: Clean up targets with i82801gxArthur Heymans
Things cleaned up in this patch: * Add macros for the GENx_DEC registers; * replace many magic numbers by macros; * remove many writes to DxxIP since they were 'setting' reset default values; * fix some comments about decode ranges. Change-Id: I9d6a0ff3d391947f611a2f3c65684f4ee57bc263 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-14AMD CIMx SB800: late.c: Use variable `device` from for loop conditionPaul Menzel
Use the variable `device` instead of `dev` in the predicate of the if condition, as `dev` is not changed in the for loop. The for loop was added in the following commit. commit 8fed77ae4c46122859d0718678e54546e126d4bc Author: Scott Duplichan <scott@notabs.org> Date: Sat Jun 18 10:46:45 2011 -0500 ASRock E350M1: Configure SB800 GPP ports to support onboard pcie nic Reviewed-on: http://review.coreboot.org/44 The assumption that the devices are ordered in the tree seem to hold in this case (although it is not ensured) and therefore at least with the ASRock E350M1 no (visible) change is experienced as the children are all of type `DEVICE_PATH_PCI`. Change-Id: Iaa2fa13305dbe924965d27680cd02fe30c2f58a5 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/2562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-14mainboard/asus/am1i-a: add support for board ASUS AM1I-AGergely Kiss
Add code to support the board ASUS AM1I-A. Tested with multiple payloads and OSes with satisfactory results. S3 suspend/resume works fine with Linux but has issues with Windows (an exception is thrown). However, after manually rebooting, Windows resumes the suspended session. * Tested with: SeaBIOS 1.11 + Linux 4.10 - OK * Tested with: tianocore vEDK2017 + MS Windows 8.1 - OK * Tested with: FILO 0.6.0 - hangs after showing the banner Details are going to be published on the board's status page. Change-Id: I3d9432849560df81536bbb2ce4c87cd265b820f7 Signed-off-by: Gergely Kiss <mail.gery@gmail.com> Reviewed-on: https://review.coreboot.org/23002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-13mainboard/google/kahlee: Finish GPIO90 setup for GruntMartin Roth
GPIO 90 is being used as a GPIO. The IOMUX register is set correctly, but these additional registers need to be set to use it as a GPIO. - Split structures into variant specific versions. These will be moved into the variant tree in a follow-on patch - Set GENINT_DISABLE bit - Disable interrupts for this GPIO. BUG=b:71867096 TEST=Build and boot grunt. Verify registers are set correctly. Change-Id: I4b8d12720167b298ee6e0acf80edf414539975b0 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23228 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-13soc/amd/stoneyridge: Add definition for GENINT_DISABLEMartin Roth
BUG=b:71867096 TEST=None Change-Id: Ic8111d34355e6667c37a51d285ebb50c1659f4e5 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23227 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-13mainboard/google/kahlee: Fix GPIO tableMartin Roth
The GPIOs that are being set low had the wrong value getting set. FCH_GPIO_OUTPUT_VALUE was being set instead of FCH_GPIO_OUTPUT_ENABLE. BUG=b:70234300 TEST=Build and boot Grunt Change-Id: I16792b76252506a43aac92738b04096ae3fde01c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-01-13google/kahlee/grunt: Add grunt touchpad ASLDaniel Kurtz
Grunt and Kahlee touchpads are on different i2c busses; I2CC and I2CD, respectively. Since grunt is the 'baseboard', put its configuration under baseboard, and include it from the grunt variant. BUG=b:71820409 TEST=Boot grunt to kernel, use evtest to test trackpad. TEST=Boot kahlee to kernel, use evtest to test trackpad. Change-Id: I1aeacf9a840342e73c1e219a825b39a124b4dd57 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23232 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-13google/kahlee/grunt: Add Grunt audio codec ASLDaniel Kurtz
Grunt and Kahlee have different audio codecs. Create a new audio .asl for the baseboard for grunt's codec, link to it from the grunt mainboard, and move the kahlee codec table from the baseboard mainboard to its own .asl in variant/kahlee. Note, we can't use the generic drivers due to the PCI scope expectation. The AMD I2C are not PCI devices. BUG=b:69397774 TEST=Codec driver loads. Check dmesg. Change-Id: I1cc245357d1f3d444e5a5012466eaa5d75d637eb Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Signed-off-by: Marc Jones <marcj303@gmail.com> Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23226 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-13google/kahlee/grunt: Move ASL to variantsMarc Jones
Move the apci/ to the baseboard and move mainboard.asl to each variant. BUG=b:71873651 TEST=build BRANCH=none Change-Id: I8a829f2946e4b280cd78574eb8dbda6c2a9a1028 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/23229 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-01-13soc/amd/stonyridge: Give I2C devices unique _UIDsDaniel Kurtz
The ACPI unique identifier (_UID) should be unique. This doesn't actually matter much for Linux, though, since the kernel can handle it when the BIOS doesn't get this right. See: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=b4b6cae2f36d92b31788f10816709d5290a1119a b4b6cae2f36d ACPI / platform: use ACPI device name instead of _HID._UID Change-Id: I8b1b3143174584a93f3d45bf482b8922b3f0ec12 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-01-13Revert "soc/amd/common/pi: Fix issue in AGESA heap allocator"Marc Jones
This reverts commit 0f5651584ebb8e2ccfa151275bfd2f70e74bae9b. This is not the correct fix for the heap allocator. It looks like the root cause is in the buffer size of the deallocate function. Change-Id: I33c479a30d89a665677d3e4914194ae8136504af Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/23245 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chris Ching <chingcodes@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-13mainboard/google/zoombini/variants/meowth: set GPD_2 to NF1Nick Vaccaro
Meowth uses GPD_2 as a dedicated lan_wake pin, so GPD_2 must be set to use NF1 instead of gpio. BUG=b:64395641 BRANCH=none TEST=none Change-Id: Iadf7158a792dfae0ea5e824d197a558524cdb5fd Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-12mb/compulab/intense_pc: Change devicetree to correct CPU socketHal Martin
Intense PC uses FCBGA1023 socket, not rPGA989. Correct the socket in the devicetree. Change-Id: Ie657af2f51dfb7add90b19b26c0c37d312d59821 Signed-off-by: Hal Martin <hal.martin@gmail.com> Reviewed-on: https://review.coreboot.org/22762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-01-12mb/compulab/intense_pc: enable SuperIO UARTHal Martin
Enable the UART via SMSC SIO1007 SuperIO, this allows you to see boot boot messages from coreboot over the integrated RS-232 port (requires use of included dongle). Change-Id: I11a4c532ed73a0cf27d6e7bef6e04035c3942567 Signed-off-by: Hal Martin <hal.martin@gmail.com> Reviewed-on: https://review.coreboot.org/22737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-12mainboard/hp: Add Elitebook Revolve 810 G1Bill XIE
The code is based on autoport and that for 8470p. Tested: - CPU i5-3437U - Slotted DIMM 8GiB - Soldered RAM 4GiB from Hynix (There may be more models here) - Onboard USB2 interfaces (digitizer, wlan slot, wwan slot, camera) - Mini pci-e on wlan slot - On board SDHCI connected to pci-e - USB3 ports - USB3 hub on dock (connected to USB3 port 1) - NVRAM options for North and South bridges - S3 - TPM1 on LPC - Linux 4.13.13-1 within Debian GNU/Linux testing, loaded from SeaBIOS, or Linux payload (Heads) Not work: - An "NFC" device connected to LPC Not implemented yet: - Detecting the model of Soldered RAM at runtime, and loading the corresponding SPD datum (3 observed) from CBFS Change-Id: Iba9c361591697e6a2b3b7b485f7f1649c2a83524 Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/22972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-01-12mb/google/poppy/variants/nami: Fix DA7219 IRQ issueKaiyen Chang
Change PAD_CFG_GPI_GPIO_DRIVE to PAD_CFG_GPI_APIC for GPIO D9 to meet the requirement of DA7219 IRQ pin. BUG=b:70646770 BRANCH=none TEST=Use aplay and arecord to verify headphone function. Change-Id: Id6cff8325c4c7f02f6f4df547fde286e2ef83d5c Signed-off-by: Kaiyen Chang <kaiyen.chang@intel.com> Reviewed-on: https://review.coreboot.org/23160 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-12soc/intel/common/block: Check for NULL before dereferenceShaunak Saha
We check for NULL from the return of function acpi_device_path before passing it to acpigen_write_scope to avoid NULL pointer dereference. Change-Id: I997461c9b639acc3c323263d304333d3a894267c Found-by: Klockworks Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/23094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-12soc/intel/skylake: Override KBL IccMax settingsGaggery Tsai
According to Intel document #559100 KBL EDS v2.8, section 7.2 DC specifications, the IccMax setting for KBL-U, KBL-U42 and Celeron/Pentium are different. This patch overrides the IccMax settings for KBL-U/R/Y since device tree could not handle all KBL-U/R combinations when multiple SKUs are adopted in a project. Besides, it is inefficient to maintain the same code for all variants. Hence, place it in the common code so that all variants could leverage the benefits. +----------------+-------------+---------------+------+-----+ | Domain/Setting | SA | IA | GTUS | GTS | +----------------+-------------+---------------+------+-----+ | IccMax(KBL-U/R)| 6A(U42) | 64A(U42) | 31A | 31A | | | 4.5A(Others)| 29A(Celeron) | | | | | | 32A(i3/i5) | | | +----------------+-------------+---------------+------+-----+ | IccMax(KBL-Y) | 4.1A | 24A | 24A | 24A | +----------------+-------------+---------------+------+-----+ BUG=b:71369428 BRANCH=None TEST=Remove icc_max setting from devicetree & emerge-fizz coreboot chromeos-bootimage & Ensure the KBL-U42, KBL-U22 and Celeron SKUs are identified correctly and IccMax settings are passed to FSPS correctly. Change-Id: I291462b73d3fbd17f17975de7fd77dc48ca99251 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/23060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-12ec/lenovo/h8: Add support for bluetooth on wifiPatrick Rudolph
The EC does enable bluetooth on wifi cards and BDC at the same time. Check the new Kconfig to support bluetooth on wifi in case no BDC is installed and the BDC detection fails. Change-Id: I23f14c937252a296dc543db49ec9e093e7e24604 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/21578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-12mb/google/fizz: update DPTF settingsKevin Chiu
TCPU: _CRT: 100 _PSV: 93 _TRT: 100/5(s) TSR0: _CRT: 83 _PSV: 70 _TRT: 100/10(s) TSR1: _CRT: 73 _PSV: 67 _TRT: 100/30(s) TCC: 6 for 94'C PL1: max: 15W min: 3W BUG=b:70294260 BRANCH=master TEST=build Change-Id: Ie17f4395d2199009fd68a600d818f2be54bc8935 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/23155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-12mb/google/fizz: Disable PCH LanKane Chen
Fizz has external Lan on PCIE port. The Lan device on PCH is not used. BUG=b:70889517 Change-Id: I99894bedec14a44724ac7c22d0c894132a795b78 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/23180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-12mainboard/glkrvp: Add EC_GOOGLE_CHROMEEC_SWITCHESShaunak Saha
This patch adds the EC_GOOGLE_CHROMEEC_SWITCHES option so that we use the common switch.c file Change-Id: I93a2ba63015db17989c89ce1b5897de6a93e201f Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/23131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 01:20:36 +0000