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2018-01-23binaryPI: Move agesawrapper.h headerKyösti Mälkki
Change-Id: Ib8d4d3ee490188ce171188d859549da586683e26 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-23AGESA_LEGACY: Apply final cleanup and file removalsKyösti Mälkki
With no boards left using AGESA_LEGACY, wipe out remains of that everywhere in the tree. Change-Id: I0ddc1f400e56e42fe8a43b4766195e3a187dcea6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-23sb/intel/bd82x6x: Reduce function-disable messNico Huber
Most affected boards set the function disabled (FD) register to an arbitrary state dumped from systems running the vendor BIOS. This makes it impossible to enable the devices in devicetree and a pretty big mess of course because nobody cared to keep the register in sync with the devicetree. To get completely rid of most of the writes to FD, move setting of PCH_DISABLE_ALWAYS into the southbridge code where it belongs. Change-Id: Ia2a507cbcdf218d09738e2e16f0d3ad1dcf57b8b Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/23255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hal Martin <hal.martin+coreboot@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Bill XIE <persmule@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-01-23nb/intel/i945: Use ESMRAMC instead of 0x9eElyes HAOUAS
Macro renamed to be in accordance with the name used in the datasheet. Change-Id: I5671c39608769b2c5ea2fb17809430f56e5f0b71 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/23330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-01-23mainboard/intel/cannonlake_rvp: Add support for MAX98373 speaker ampN, Harshapriya
Add NHLT and dt support for max98373 amp BUG=None TEST=check SSDT and verify entries for max98373 TEST=check NHLT ACPI tables included blobs for max98373 Change-Id: I0b402f89f1ece9e62a394f713c4b0feff29bd1e5 Signed-off-by: N, Harshapriya <harshapriya.n@intel.com> Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/22674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-23drivers/i2c/max98373: Add driver for generating device in SSDTN, Harshapriya
Add a device driver to generate the device and required properties into the SSDT for max98373. TEST=verified SSDT contained relevant params BUG=None Change-Id: Id45f74e52855f4b19276e1d3d673d5448207ef4b Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Signed-off-by: N, Harshapriya <harshapriya.n@intel.com> Reviewed-on: https://review.coreboot.org/22673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-23mainboard/intel/cannonlake_rvp: Add support for SND_MAX98357_DA7219Lijian Zhao
Add NHLT and dt support for Audio with Max98357 and DA7219 TEST=verified NHLT tables and SSDT entries BUG=None Change-Id: If7960eb6bb441f35cbd9a8a6acc37f03e04e3b70 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/22144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-23soc/intel/cannonlake: Add audio NHLT supportLijian Zhao
Add audio NHLT support for cannonlake, reference code is implementation in apollolake. CQ-DEPEND=CL:*533799 BUG=None TEST=None Change-Id: Ie8561cc64412bef54329b317874a8fe12e0bf889 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/22134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-22drivers/net: Add device index for multiple NIC cardsGaggery Tsai
This patch adds a member device_index to r8168 chip information which allows driver to identify which NIC card requests MAC address. In this implementation, only 10 NIC cards are supported, the device index is in the range of 0 to 10. Regarding to MAC address mapping, when there is only one NIC on DUT, it is treated as a special case mapping to "ethernet_mac" in VPD for backward compatibility. When there are multiple NICs on DUT, they are mapping to "ethernet_macN" where N is [0-9]. Device tree configuration: For single NIC: .device_index = "0", maps to "ethernet_mac" For multiple NICs: .device_index = "[1-10]", maps to "ethernet_mac[device_index - 1]" BUG=b:69950854 BRANCH=None TEST=Added device_index = [0-10] under /drivers/net in device tree && Programmed the mac address to VPD in shell vpd -s ethernet_mac=<mac address> or vpd -s ethernet-mac[0-9]=<mac address> && reboot the system. Ensure the MAC address was fetched correctly by ifconfig command. Change-Id: I108b9bfba39370c8906a2fa4d2b39b106e884e0c Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/22984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-22mainboard/google/zoombini: mrc cacheCaveh Jalali
this enables the MRC recovery cache for zoombini & variants. the Kconfig options are: HAS_RECOVERY_MRC_CACHE MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN one note of caution: early board builds will likely fail to boot with: tlcl_extend: response is 0 tlcl_extend: response is 0 tlcl_lock_nv_write: response is 0 tlcl_lock_nv_write: response is 28b Failed to lock rec hash space(1f) Saving nvdata hard_reset() called! the fix is to boot into recovery once, then it's business as usual. using servo, this can be done with: dut-control power_state:rec BUG=b:71785303 BRANCH=chromeos-2016.05 TEST=boots on meowth... Change-Id: I77f36d36a70c8c9c74a7fa3a114d3177f33a708b Signed-off-by: Caveh Jalali <caveh@google.com> Reviewed-on: https://review.coreboot.org/23298 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-22mainboard/google/zoombini: add EC to ACPI tablesCaveh Jalali
this adds missing ACPI entries for the EC, CPU, and power button. also, the EC to AP wakeup pin assignment is fixed. BUG=b:71819257 BRANCH=chromeos-2016.05 TEST=booted on meowth. /sys/class/power_supply now gets populated. Change-Id: I0d091bdf25f9a806bd36329d1f17ac34b3115e48 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/23237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2018-01-22amd/stoneyridge/include/soc/southbridge.h: Replace SATA magic numbersRichard Spiegel
CONFIG_STONEYRIDGE_SATA_MODE is compared against "magical numbers". Because actual literals are in AGESA.h and adding agesa_headers.h to southbridge.h causes compile errors, move comparison code from southbridge.h to southbridge.c (where they are actually used). Replace these numbers with actual literals. BUG=b:71754828 TEST=Build kahlee. Change-Id: I711473bf492d5ceca026ccd112c2c389a23bdbf9 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-22AMD/stoneyridge: Fix SATA reset inconsistencyRichard Spiegel
At AGESA AmdInitReset, SATA enable and IDE enable (elements of FCH_RESET_INTERFACE) are programmed twice (before calling AGESA for AmdInitReset and from said AGESA function call out), using different functions with different results. The first would result in TRUE/FALSE, the second set would result in TRUE/TRUE. Use the functions of the second set within the first set, and remove them from the second set. BUG=b:71754828 TEST=Build kahlle without the change, boot and record output. Rebuild kahlee with the change, boot and record output. Compare both outputs, the should be no change except in timing. Change-Id: I326fcc8801542aa7feef286d02abdfe63354cdd0 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-22mb/google/fizz: Remove IccMax settings from DTGaggery Tsai
This patch removes IccMax settings from device tree since they are handled in SoC code from patch e1a75d. BUG=b:71369428 BRANCH=None TEST="USE=fw_debug emerge-fizz chromeos-mrc coreboot chromeos-bootimage" & ensure the IccMax settings passed to FSP are from SoC code. Change-Id: I6b01c50a2589d1722c5bf4aa2f44a9574df818f4 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/23278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2018-01-22mainboard/google/zoombini/variants/meowth: enable PCH_FP_PWR_ENVincent Palatin
Turn on the load switch to the FP MCU at startup, so the kernel can detect it and use it. The load switch enable pin is connected to the GPP_A11 PCH pin (aka PCH_FP_PWR_EN). BRANCH=none BUG=b:71986991 TEST=on Meowth, see the kernel detecting a cros_fp device at startup: [ 2.133456] cros-ec-spi spi-PRP0001:00: Fingerprint MCU detected. [ 2.157420] cros-ec-spi spi-PRP0001:00: Chrome EC device registered Change-Id: Id3c40b965a5f018c63481c2e2eea3fc8307352bd Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://review.coreboot.org/23329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-22mainboard/google/zoombini/variants/meowth: configure FP MCU SPI deviceVincent Palatin
Configure the FP MCU interface on GSPI1. BRANCH=none BUG=b:71986991 TEST=boot on reworked Meowth with a ZerbleBarn board attached to GSPI1 and see the cros_ec kernel driver detecting it. Change-Id: Ib874ddaf4948a766fd05c11f4675dbfdb679059d Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://review.coreboot.org/23328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-22mainboard/asus/am1i-a: remove unwanted variableGergely Kiss
The variable t32 was originally used to do bitwise operations, but it is not required anymore. Also, it was assigned twice accidentally, which introduced a new Coverity Scan defect. Found-by: Coverity (CID 1385126: (UNUSED_VALUE)) Change-Id: I77afd5064304a36991f63cf1328e13820144efb6 Signed-off-by: Gergely Kiss <mail.gery@gmail.com> Reviewed-on: https://review.coreboot.org/23320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-20drivers/mrc_cache: Always generate an FMAP regionArthur Heymans
This automatically generates an FMAP region for the MRC_CACHE driver which is easier to handle than a cbfsfile. Adds some spaces and more comments to Makefile.inc to improve readability. Tested on Thinkpad x200 with some proof of concept patches. Change-Id: Iaaca36b1123b094ec1bbe5df4fb25660919173ca Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-19amd/stoneyridge: Remove unused S3 NVRAM save/restoreMarshall Dawson
Remove the BiosRam read and write functions that were brought over from the hudson source. The functionality will be superseded later with new general-purpose functions. Change-Id: Ib80c66b838fdbdd388a392b4fedaac36bf0bbb0c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22725 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-19amd/stoneyridge: Add BIOS RAM R/W functionsMarshall Dawson
The internal FCH contains 256 bytes of "BiosRam" that maintains its state until RSMRST# is asserted or standby power is lost. Add functions to support read and write operations. Change-Id: I2ddf58a63e69b2775de9a8163534b13dad2ea2fe Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-01-19amd/stoneyridge: Move SB index/data pairs to iomap.hMarshall Dawson
Relocate the I/O registers to the iomap for PM, PM2, and BIOSRAM. Change-Id: I3a59adc974a8a90bfc586188b829a7252356b3cb Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22723 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-19amd/stoneyridge: Move acpi_get_sleep_type to sb_utilMarshall Dawson
Relocate the acpi_get_sleep_type() function out of the southbridge ramstage file. This will make it more convenient for using elsewhere. Change-Id: Id7ba709bb867fb00ed6c7fa7526de087a3b9b3ca Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-19soc/amd/common: Make agesa_heap_base non-staticMarshall Dawson
The cbmem location holding the heap will be used to store additional information in subsequent patches. Remove the static designation from agesa_heap_base. Change-Id: Ic607432fd6500ef69b5d47793896cf12a699d8b7 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22721 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-19amd/common: Remove GetHeapBase camel caseMarshall Dawson
A subsequent patch will use GetHeapBase() in more files than heapmanager.c. Convert it to a format more similar to existing coreboot source. Change-Id: I8362af849fc9d7cb1b8a93113e8d78dcac51c20a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22903 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-19amd/common: Define regions in AGESA cbmemMarshall Dawson
In 6c747068 "amd/stoneyridge: Put AGESA heap into cbmem" the AGESA heap was moved completely into cbmem. This was a departure from the "late cbmem init" method of adding it late in post, then storing the S3 volatile data to the region. Remove the hardcoded base address that was missed in that commit. To prepare for S3 support, split the region into subregions for heap, AGESA's S3 volatile storage, and an MTRR save area. BUG=b:69614064 Change-Id: I06c137f56516f3a04091d1191cd657a0aa07320b Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-19amd/common/s3: Remove legacy spi.cMarshall Dawson
Remove the original spi.c file that writes S3 NV data to flash in a proprietary format. The s3 folder is retained to facilitate new development. Change-Id: I1b5fe8e854c3d2dd71506c2acd6ff73e4b86d7d4 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-19drivers/mrc_cache: Make bootstate for SPI writes variableMarshall Dawson
The default time for writing MRC data to flash is at the exit of BS_DEV_ENUMERATE but this is too early for some implementations. Add an option to Kconfig for allowing a late option to be selected. The timing of the late option is at the entry of BS_OS_RESUME_CHECK. TEST=Select option and inspect console log on Kahlee BUG=b:69614064 Change-Id: Ie7ba9070829d98414ee788e14d1a768145d742ea Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22937 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-19drivers/amd/agesa: Fix AGESA heap deallocatorMarc Jones
Ported from commit e6033ce1 soc/amd/common/block/pi: Fix AGESA heap deallocator The deallocation was always subtracting the header, even when it shouldn't. This caused problems for the allocator where buffer sizes were incorrect and freed and used buffers could collide. Fix the deallocation size. Clear deallocated concatinated buffer header memory. Fix the initial calculation of the total buffer size available to be allocated. Original-Change-Id: I2789ddf72d662f24709dc5d9873741169cc4ef36 Change-Id: Ibac916fcd964adca97a72617428e3d53012e13a1 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/23309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-18Intel i440bx boards: Remove - using LATE_CBMEM_INITKyösti Mälkki
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. Mainboards: src/mainboard/a-trend/atc-6220 src/mainboard/a-trend/atc-6240 src/mainboard/abit/be6-ii_v2_0 src/mainboard/azza/pt-6ibd src/mainboard/biostar/m6tba src/mainboard/compaq/deskpro_en_sff_p600 src/mainboard/gigabyte/ga-6bxc src/mainboard/gigabyte/ga-6bxe src/mainboard/msi/ms6119 src/mainboard/msi/ms6147 src/mainboard/msi/ms6156 src/mainboard/nokia/ip530 src/mainboard/soyo/sy-6ba-plus-iii src/mainboard/tyan/s1846 Change-Id: Id895963f9641bcaaa65e8a8cb21213a758a9ad80 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/23301 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-18Intel i82810 boards & chips: Remove - using LATE_CBMEM_INITKyösti Mälkki
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: northbridge/intel/i82810 Mainboards: src/mainboard/asus/mew-am src/mainboard/asus/mew-vm src/mainboard/ecs/p6iwp-fe src/mainboard/hp/e_vectra_p2706t src/mainboard/intel/d810e2cb src/mainboard/mitac/6513wu src/mainboard/msi/ms6178 src/mainboard/nec/powermate2000 Change-Id: Ib273316c59f499e6cd3a0e4c4dc4c2cce94ff291 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/23300 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-18mainboard/google/zoombini/variant/meowth: add memory optionsNick Vaccaro
Add support for new memory stuffing options that will appear on the P1 meowth boards. new strap setting - associated SPD file ---------------------------------------- 0b001 - Hynix_H9HCNNN8KUMLHR_1GB.spd.hex 0b010 - Samsung_K4F6E3S4HM_2GB.spd.hex 0b011 - Hynix_H9HCNNNCPUMLHR_4GB.spd.hex BUG=b:69011806 BRANCH=none TEST=none Change-Id: Ief07f3de351d01cbc195b785c36e96de0cbf7ddb Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-18cpu/intel: Remove unused CPU codeArthur Heymans
Change-Id: I44574e64e621ea60d559d593694af36c648fb7d7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-18util/blobtool: rename to bincfgDenis 'GNUtoo' Carikli
The name blobtool is confusing as 'blob' is also used to describe nonfree software in binary form. Since this utility deals with binary configurations it makes more sense to call it bincfg. Change-Id: I3339274f1c42df4bb4a6b30b9538d91c3c03d7d0 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: https://review.coreboot.org/23239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-18security/tpm: Move TSS stacks into sub-directoryPhilipp Deppenwiese
Change-Id: I5e20d98665c17d39f3f69772093a062bb905f6f9 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-18security/tpm: Change TPM naming for different layers.Philipp Deppenwiese
* Rename tlcl* to tss* as tpm software stack layer. * Fix inconsistent naming. Change-Id: I206dd6a32dbd303a6d4d987e424407ebf5c518fa Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-18security/tpm: Move tpm TSS and TSPI layer to security sectionPhilipp Deppenwiese
* Move code from src/lib and src/include into src/security/tpm * Split TPM TSS 1.2 and 2.0 * Fix header includes * Add a new directory structure with kconfig and makefile includes Change-Id: Id15a9aa6bd367560318dfcfd450bf5626ea0ec2b Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-17google/fizz: Fix barrel jack values for U42 and U22Shelley Chen
Our current U22 skus (celeron and i3) actually don't support PL2, but making sure that if we do decide in the future to use it to make sure PL2 and PsysPl2 values are set appropriately. BUG=b:71594855 BRANCH=None TEST=Make sure that PsysPL2 value set to 90W with barrel jack for U42 and 65W with barrel jack for U22. Change-Id: I084d0320128a6e05948023520a30c497c41be23b Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-17lenovo/z61t: Update for PNOT changeMarshall Dawson
Change the directory of the included cpu.asl file. This board seems to have been omitted in 0a4e0fd "Fix the PNOT ACPI method". Change-Id: Idc00197b1544006299e720dca59e02f6bf8f683c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23308 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-01-17soc/intel/cannonlake: Reserve PMC IO resourcesSubrata Banik
PMC controller gets hidden during FSP Silicon initialization using sideband interface on CNP-PCH. Hence unable to reserve PMC IO resources during PCI enumeration process. This causes hang issue on non-chrome platform with CNP-PCH due to ABASE corruption. This patch ensures PMC IO resource (ABASE) is getting reserved (IO address 0x1800-0x1900) and ACPI base is not overwritten by other devices. TEST=ABASE range is reserved along with LPC IO range during PCI enumeration. PCI: 00:1f.0 resource base 1800 size 100 align 0 gran 0 limit 0 flags c0000100 index 20 Change-Id: I1fbc4339ae11058fb3daedf4ffedda1904fa52ec Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-17soc/intel/common: Add option to pass SoC IO resourceSubrata Banik
This patch ensures common block has option to reserve IO resources based on SOC requirements. Also add pch_lpc_ prefix to maintain same function nomenclature across all intel common block. Change-Id: Ic00af688104bcea1aff06be6cbb20208a60e5f1d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-17security/vboot: Add two weak methods for vboot2Philipp Deppenwiese
In order to make VBOOT2 independent from the CHROMEOS kconfig option a weak method for get_write_protect_state and get_recovery_mode_switch() is required. Introduce a kconfig option for controlling this behaviour. This is a temporary fix and will be removed afterwards. Change-Id: I3b1555bd93e1605e04d5c3ea6a752eb1459e426e Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-17soc/intel/apollolake/meminit_util_glk.c: Check for NULLRavi Sarawadi
We check for NULL here for memory_info_hob and return if it's NULL so that the future dereferencing is proper. Change-Id: Ie34931504ad92739fdaa68ec7989e76e8eee2595 Found-by: Klockworks Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/23223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-17mb/google/poppy: Set S0ix lazy wake maskJenny TC
Enable S0ix wake mask programming from coreboot using unified host event programming interface. Lazy s0ix wake mask helps to configure s0ix wake mask during boot and EC sets the wake mask during S0ix entry. BRANCH=none BUG=b:63969337 TEST=verify masks with ec hostevent command on S0,S3,S5 and S0ix Change-Id: I65173104fce258d03956bbb0e80073c47fe80fab Signed-off-by: Jenny TC <jenny.tc@intel.com> Reviewed-on: https://review.coreboot.org/21086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-17google/chromeec: Enable unified host event programming interfaceJenny TC
Unified Host Event Programming Interface (UHEPI) enables a unified host command EC_CMD_PROGRAM_HOST_EVENT to set/get/clear different host events. Old host event commands (0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F) is supported for backward compatibility. But newer version of BIOS/OS is expected to use UHEPI command (EC_CMD_PROGRAM_HOST_EVENT) The UHEPI also enables the active and lazy wake masks. Active wake mask is the mask that is programmed in the LPC driver (i.e. the mask that is actively used by LPC driver for waking the host during suspended state). It is same as the current wake mask that is set by the smihandler on host just before entering sleep state S3/S5. On the other hand, lazy wake masks are per-sleep masks (S0ix, S3, S5) so that they can be used by EC to set the active wake mask depending upon the type of sleep that the host has entered. This allows the host BIOS to perform one-time programming of the wake masks for each supported sleep type and then EC can take care of appropriately setting the active mask when host enters a particular sleep state. BRANCH=none BUG=b:63969337 TEST=verify masks with ec hostevent command on S0,S3,S5 and S0ix 1). Verified wake masks with ec hostevent command on S0,S3,S5 and S0ix 2). suspend_stress_test with S3 and S0ix 3). Verified "mosys eventlog list" in S3 and s0ix resume to confirm wake sources (Lid, power buttton and Mode change) 4). Verified "mosys eventlog list" in S5 resume to confirm wake sources (Power Button) 5). Verified above scenarios with combination of Old BIOS + New EC and New BIOS + Old EC Change-Id: I4917a222c79b6aaecb71d7704ffde57bf3bc99d9 Signed-off-by: Jenny TC <jenny.tc@intel.com> Reviewed-on: https://review.coreboot.org/21085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-17cpu/intel/speedstep: Fix the PNOT ACPI methodArthur Heymans
The PNOT method never notifies the CPU to update it's _CST methods due to reliance on inexisting variable (PDCx). Add a method in the speedstep ssdt generator to notify all available CPU nodes and hook this up in this file. The cpu.asl file is moved to cpu/intel/speedstep/acpi since it now relies on code generated in the speedstep ssdt generator. CPUs not using the speedstep code never included this PNOT method so this is a logical place for this code to be. Change-Id: Ie2ba5e07b401d6f7c80c31f2bfcd9ef3ac0c1ad1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-17ec/h8: Store PWRS and notify CPU on AC power plug/unplug eventsArthur Heymans
PWRS is is the power source gnvs. Notifying CPU is needed to change P- and C-states on these events. Change-Id: I0818d10474523fb14f7ba7cfbf61166b89442083 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-17soc/intel/apollolake: Fix prev_sleep_state on G3 exitHannah Williams
If waking up from S5, then prev_sleep_state was correct but not when waking up from G3. Change-Id: I39011a0846f042d224a7cd65f736e749acc8ec75 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/23221 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-17vx900: decode the whole ROMLubomir Rintel
Fixes supports for flash ROMs larger than 512K, such as the 1M one in HP t5550 Thin Client. Change-Id: I4d6287e130809c33dfbd40bce7913a95b4b3a9c7 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/22262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-17arch/x86/acpi_device: Provide macros for GPIO input with polarityFurquan Shaikh
Similar to ACPI_GPIO_OUTPUT, this change provides ACPI_GPIO_INPUT_* macros with ACTIVE_LOW and ACTIVE_HIGH polarity. Change-Id: I77da6ad2f04d7f7bb6774df35105bdbe963d87d3 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-17AGESA f15: Drop CAR teardown without POSTCAR_STAGEKyösti Mälkki
Change-Id: Ie5ff62ee1c7ca193ba841c5b2fb20940ec657625 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-25 18:00:28 +0000