summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2020-03-11cbfs: Remove unused functionsJulius Werner
cbfs_boot_load_stage_by_name() and cbfs_prog_stage_section() are no longer used. Remove them to make refactoring the rest of the CBFS API easier. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ie44a9507c4a03499b06cdf82d9bf9c02a8292d5e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-03-11mb/google/puff: Enable cros_ec_keyb deviceKangheui Won
This is required to transmit button information from EC to kernel. BUG=b:150830342 BRANCH=None TEST=firmware_ECPowerButton test passes on puff Change-Id: I10ba9d55e8997ce2412deb0613cfcaa8f24f271d Signed-off-by: Kangheui Won <khwon@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-03-10soc/intel/common: Add more GPIO definition macrosNico Huber
Make i/o-standby state and termination configurable for GPIs. Change-Id: Id1a3c00aa8a857afa08e745b0b6a578b01fa6d47 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-10soc/intel/dnv: Set INT_LINE accouting for PIRQ routing & swizzlingStephen Douthit
This code also sets unused interrupt lines to the recommended safe value of 0xff instead of ignoring such devices. Change-Id: I7582b41eb3288c400a949e20402e9820f6b72434 Signed-off-by: Stephen Douthit <stephend@silicom-usa.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-10soc/intel/dnv: Add ACPI _PRT methods for virtual root portsStephen Douthit
This eliminates Linux kernel warnings that look like: pcieport 0000:00:17.0: can't derive routing for PCI INT B ixgbe 0000:07:00.1: PCI INT B: no GSI - using ISA IRQ 10 Change-Id: I2029e7a8252b9e48c1df457d8da5adce7d1ac21d Signed-off-by: Stephen Douthit <stephend@silicom-usa.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-10soc/intel/dnv: Fix ACPI reporting of root port interrupt routingStephen Douthit
pcie_port.asl defines an IRQM method that looks up legacy interrupt swizzling based on incoming interrupt "pin" A-D and root port number. Unfortunately the 8-bit root port number stored at offset 0x4F in the config space matches the device number, not the 1-8 scheme used in the LUT reported to the OS. Fix the case values to match the hardware. Change-Id: I103d632a4bc99461f02e05aa0f9a9eb7376770d9 Signed-off-by: Stephen Douthit <stephend@silicom-usa.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34712 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-10mb/intel/{saddlebrook,kunimitsu}: Add macro for SaGv configPraveen Hodagatta Pranesh
Change-Id: Ia31da9997ba46c15cd385bf55e009cf299848b64 Signed-off-by: Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36423 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-10src: Remove unneeded 'include <arch/cache.h>'Elyes HAOUAS
Change-Id: I6374bc2d397800d574c7a0cc44079c09394a0673 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37984 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-10winbond/w83667hg-a: Disable mouse controller also during resumePaul Menzel
There is no reason to not disable the controller during resume. That way, no ASL is needed. Change-Id: I282a03647ee0958abb118fafe306abe5782db71c Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/22286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-10soc/intel/dnv: Don't clobber SATA_MAP while trying to set modeStephen Douthit
SATA Mode Select is bit 16 of the SATA General Configuration register. This code currently incorrectly pokes at the Port Clock Disable bits in the Port Mapping Register, and without clock the affected ports can't link. Change-Id: I37104f520a869bd45a32cfd271d0b893aec3c8ed Signed-off-by: Stephen Douthit <stephend@silicom-usa.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Vanessa Eusebio <vanessa.f.eusebio@intel.com> Reviewed-by: David Guckian Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-10soc/intel: fix eist enablingMatt Delco
There was a bug like this for skylake that seems to have been copied to other SoCs. Signed-off-by: Matt Delco <delco@chromium.org> Change-Id: Ib4651eda46a064dfb59797ac8e1cb8c38bb8e38c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-03-10soc/intel/xeon-sp,mb/ocp/tiogapass: Don't fake binariesNico Huber
If we don't pretend to have binaries, there is no need to add fake ones. This also fixes building the default config. Change-Id: I8f933f24a734a9ce3d82ef57f7f234ee4dfa86e9 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39383 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-10lib/spd_bin: Correct LPDDR3 SPD informationEric Lai
Follow JEDEC 21-C to correct JEDEC LPDDR3 SPD information. Based on JEDEC 21-C, LPDDR3 has the same definition with LPDDR4. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I7c9361caf272ea916a3a618ee2b72a6142ffc80c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39366 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-10mb/libretrend/lt1000: Add Libretrend LT1000 mainboardMichał Żygowski
Change-Id: I32fc8a7d3177ba379d04ad8b87adefcfca2b0fab Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-03-10mb/protectli/vault_kbl: Add FW6 supportMichał Żygowski
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I03e8e8db5d827fe113280f2a6376d364edf42870 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-03-10mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generationSrinidhi N Kaushik
This change uses drivers/intel/wifi chip for CNVi device and adds dynamic SSDT entires for CNVi also export wake gpio for CNVi BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board and check for SSDT entries for CNVi Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Icdbffa0c29c9e0849a6a99f8592b6f35c0bb3207 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39315 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-10soc/intel/tigerlake: Enable Hybrid storage modeWonkyu Kim
To use Optane memory, we need to set 2x2 PCIe lane mode while we need to set 1x4 PCIe lane mode for NVMe. The mode can be selected using the FIT tool at build time. By enabling hybrid storage mode in FSP, FSP will set 2x2 PCIe lane mode if Optane memory is detected and the mode is not 2x2 and set 1x4 PCIe lane mode if Optane memory is not detected and the mode is not 1x4 during boot up. The mode is saved in SPI NOR for next boot. BUG=b:148604250 BRANCH=none TEST=Build and test booting TGLRVP from NVMe and Optane Check PCIe lane configuration. Show all the NVMe devices lspci -d ::0108 Show all the NVMe devices and be really verbose lspci -vvvd ::0108 Print PCIe lane capabilities and configurations for all the NVMe devices. lspci -vvvd ::0108 | grep -e x[124] Print all the PCIe information of the device ae:00.0 lspci -vvvs ae: Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I25bc380697b0774cc30ad1b31ad785ee18822619 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39232 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-10mb/google/volteer: set TcssXhciEn to 1Brandon Breitenstein
BUG=144874778 TEST=Built with Volteer recipe and verified USB functionality Change-Id: I6cbdbd8a4f65a0fe19e3fb8d7b60b8b849f104e7 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-09arch/arm: Use 'print("%s...", __func__)'Elyes HAOUAS
Change-Id: I83fb453344c31f2cfa97bdaf1b8791a7bef97fd7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-03-09mb/google/dedede: Add PCIe Root Port ConfigurationKarthikeyan Ramasubramanian
Add configuration for all the PCIe Root ports and Clock Source. Configure the Root Ports as disabled and clock sources as not used. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I0a1ad7e056907e454a93f51c84e1d99f08b7bdef Reviewed-on: https://review.coreboot.org/c/coreboot/+/39166 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-09mb/google/dedede: Configure EDP_HPD GPIOKarthikeyan Ramasubramanian
This enables display for use by payload. TEST=Build and boot the mainboard. Ensure that the screens displayed by payload are visible. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I5fcd70623b15ae39954242605e75b2c5ce02ff14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-09mb/google/dedede: Configure EC <-> AP GPIOsKarthikeyan Ramasubramanian
BUG=b:150869661 TEST=Build and boot the mainboard. Trigger apreset from EC console. Trigger reboot from AP console. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I0d6dd0b4264c11f7ee0ef436cc819b0bb92974f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39325 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-09mb/google/dedede: Add GPIO listKarthikeyan Ramasubramanian
Leave all the GPIOs in not connected state so that they can be configured depending on the use-case. This is done to park the GPIOs in a known safe state. This will also help to ensure that the required GPIOs are configured when the concerned use-cases are enabled. Below GPIOs are configured in Native Function 1 and are required for boot-up. * VCCIN_AUX_VID0 * VCCIN_AUX_VID1 * AP_SLP_S0_L * PLT_RST_L * CPU_C10_GATE_L * GPDs BUG=None TEST=Build and boot the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I5293536f66a6b08c9c2d2a6281684755a0c0b1b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39114 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-09mb/google/volteer: Enable FPMCU on volteerAlex Levin
BUG=b:147500717 TEST=none Change-Id: I32fa27b399127dbf8608e0556c77431d2dad652d Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-09mb/google/volteer: change two gpio settingsNick Vaccaro
- declare the FPMCU interrupt to be level-triggered - change EC_PCH_WAKE_ODL gpio to native function mode - corrected spelling of a signal name in a comment BUG=b:144933687, b:148179954 BRANCH=none TEST=none Change-Id: I62da900d0b71139e55b52d06ec09ca25106f73cd Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-09mb/protectli/vault: Add FW2B and FW4B Braswell based boards supportMichał Żygowski
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I553fd3a89299314a855f055014ca7645100e12e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-03-09mb/asus/p5g41t-m_lx: Do not set BSEL GPIOs in devicetreeAngel Pons
This mainboard has the FSB BSEL straps wired to SuperIO GPIOs. They are set up in romstage, so it makes no sense to clobber the registers with garbage in ramstage. Tested, my Asus P5G41T-M LX still boots and it does not need a full reset on almost every reboot. Change-Id: I6ea498119df44243ec42e3cb5c2903de32a17373 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39384 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-09mb/asus/p5g41t-m_lx: Correct GPIO directionAngel Pons
Not all GPIO4 pins on the SuperIO are configured as outputs. Change-Id: Idf6350551a91c4c1a25a83e3fb9b1a6722a81c36 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-09mb/asus/p5qpl-am: Do not set BSEL GPIOs in devicetreeAngel Pons
This mainboard has the FSB BSEL straps wired to SuperIO GPIOs. They are set up in romstage, so it makes no sense to rewrite their values in ramstage. Tested, my Asus P5QPL-AM still boots. Change-Id: Ic47f96d12420ebcc70ab5cea940c4c09620c03ca Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-09soc/intel/braswell/chip.h: Include smbios.h for Type9 EntriesMichał Żygowski
In order to add the smbios_slot_desc for the SMBIOS Type9 entries into the devicetree, and not use numbers but strings like "SlotTypePciExpressGen3X4", smbios.h needs to be included in the static.c. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Id15fe4101d14479b02e536fdf63748a241c02bd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-03-09drivers/ipmi: Fix buffer double-freeJacob Garber
If reading the data for the asset_tag fails, that buffer should be freed, not the one for serial_number. Change-Id: I2ecaf7fd0f23f2fb5a6aa0961c7e17fff04847f4 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1419481, 1419485 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-093rdparty/libgfxinit: Update submodule pointerNico Huber
Changes allow to use the integrated panel logic (power sequen- cing and backlight control) for more connectors. The Kconfigs GFX_GMA_PANEL_1_PORT and GFX_GMA_PANEL_2_PORT can now be set to any port, e.g. config GFX_GMA_PANEL_1_PORT default "DP3" Now that the panel logic is not tied to the `Internal` port choice anymore, we can properly split it into `LVDS` and `eDP`. This also adds Comet Lake PCI IDs which should still work the same as Kaby and Coffee Lake. Change-Id: I78b1b458ca00714dcbe7753a7beb4fb05d69986b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38921 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-09mb/intel/tglrvp: Add memory config for Tiger Lake UP4Srinidhi N Kaushik
Add LPDDR4 memory configuration for Tiger Lake UP4 platform which includes 1. DQ/DQs Mapping 2. Board id Support 3. SPD indexing BUG=none BRANCH=none TEST= Build TGL UP4 successfully Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ibbd7036919c1a91ef12049d2af657f0a3597b57e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39365 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-09mb/intel/tglrvp: Add TGL UP4 RVPWonkyu Kim
Add initial TGL UP4 RVP build enviorment BUG=none BRANCH=none TEST= Build TGL UP4 successfully Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Iab7ada0746394539586e7cc159112dc8208fdd7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39363 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-09vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header for Tiger LakeSrinidhi N Kaushik
Update FSPS header to include HybridStorageMode Upd for Tiger Lake platform version 2457. Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ib6ac89163c0f7a11910e56b9804e386f8bcf355d Reviewed-on: https://review.coreboot.org/c/coreboot/+/39364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-03-07mb/google/volteer: add CNVi ASL entry for dynamic SSDT generationSrinidhi N Kaushik
This change uses drivers/intel/wifi chip for CNVi device and adds dynamic SSDT entires for CNVi also export wake gpio for CNVi. BUG=none BRANCH=none TEST=Build and boot volteer Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ia8baf1c7b770db23f31383bda46ae8d090468560 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-03-07lib/spd_bin: Add "number" to log messageEric Lai
Correct the missing log. Should be the part number not just part. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I17ac9c6f9545d84645665d3abe1d1613baef4e14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39353 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-07lib/spd_bin: Extend LPDDR4 SPD informationEric Lai
Follow JEDEC 21-C to extend LPDDR4 SPD information. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I68c9782c543afab4423296fa7ac1c078db5649c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-07mb/intel/tglrvp: Add pin mux for CameraWonkyu Kim
Add additional pin mux for I2C3, I2C5 for Camera. These pin muxes were done in FSPs, these pin muxes are for bypassing pin muxes in FSPs. BUG=none BRANCH=none TEST=Build with pin mux bypass FSP and boot tigerlake rvp board and check camera Simple test method to check camera: capture image by below commands from OS console >media-ctl -V "\"Intel IPU6 CSI-2 5\":0 [fmt:SGRBG10/3280x2464]" >media-ctl -V "\"Intel IPU6 CSI-2 5\":1 [fmt:SGRBG10/3280x2464]" >media-ctl -l "\"ov8856 18-0010\":0 -> \"Intel IPU6 CSI-2 5\":0[1]" >media-ctl -V "\"Intel IPU6 CSI2 BE\":0 [fmt:SGRBG10/3280x2464]" >media-ctl -V "\"Intel IPU6 CSI2 BE\":1 [crop:(0,0)/3280x2464]" >media-ctl -V "\"Intel IPU6 CSI2 BE\":1 [fmt:SGRBG10/3280x2464]" >media-ctl -l "\"Intel IPU6 CSI-2 5\":1 -> \"Intel IPU6 CSI2 BE\":0[1]" >media-ctl -l "\"Intel IPU6 CSI2 BE\":1 -> \"Intel IPU6 CSI2 BE capture\":0[1]" >yavta -u -c5 -n5 -I -s 3280x2464 --file=/tmp/frame-#.bin -f SGRBG10 $(media-ctl -e "Intel IPU6 CSI2 BE capture") Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I9ad0e5ed452d2b2e8c674abe2a647a0a9c59188e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39201 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-07cpu/x86/smm: Add smm_size to relocatable smmstubArthur Heymans
To mitigate against sinkhole in software which is required on pre-sandybridge hardware, the smm entry point needs to check if the LAPIC base is between smbase and smbase + smmsize. The size needs to be available early so add them to the relocatable module parameters. When the smmstub is used to relocate SMM the default SMM size 0x10000 is provided. On the permanent handler the size provided by get_smm_info() is used. Change-Id: I0df6e51bcba284350f1c849ef3d012860757544b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-07src/nb: Use 'print("%s...", __func__)'Elyes HAOUAS
Change-Id: I7dd6dd8e8debe1b6419625fca38670be375ef581 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-07mb: Use 'print("%s...", __func__)'Elyes HAOUAS
Change-Id: I4fa89dc1ad4196a61bb0cdfaa0d59dfe4c6fff12 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39231 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-07drivers/usb: Use 'print("%s...", __func__)'Elyes HAOUAS
Change-Id: Id90496ba54d861157343302c2600adf3b4ccd811 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39230 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-07soc/intel/tigerlake: Avoid NULL pointer dereferenceJohn Zhao
Coverity detects pointer dev as FORWARD_NULL. Add sanity check for dev to prevent NULL pointer dereference if dev did not point to the audio device. BUG=CID 1420208 TEST=Built image successfully. Change-Id: I2a62da44c7044f9dc281eae0949f7f7b612ab238 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-07vboot: Upgrade kernel space to v1.0dnojiri
This patch upgrades the kernel space to v1.0 to accommodate EC hash, which is used for CrOS EC's early firmware selection. BUG=chromium:1045217 BRANCH=none TEST=Boot Helios. Verify software sync works. Cq-Depend: chromium:2041695 Change-Id: I525f1551afd1853cae826e87198057410167b239 Signed-off-by: dnojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-03-07mb/intel/tglrvp: Update display ports for RVPWonkyu Kim
Enable DdiPortBHpd and additional pin muxes for DPs. These pin muxes were done in FSPs, these pin muxes are for bypassing pin muxes in FSPs. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board and check FSP log or DP port pin mux from pinctl driver. Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Id44cfba696b1a21296278f4de2ad6de8f6bbd63b Reviewed-on: https://review.coreboot.org/c/coreboot/+/39229 Reviewed-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-07mb/google/volteer: add samsung-K4UBE3D4AA-MGCR SPDNick Vaccaro
Add samsung K4UBE3D4AA-MGCR SPD as memory sku id 1. BUG=b:148182234 BRANCH=none TEST=none Change-Id: Ie00c45de4d31856109cda13051a75cfa2c2548f7 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-07mb/lenovo/*/devicetree: Declare device in one line if possiblePeter Lemenkov
Change-Id: I708281f7861110e4abc02948c74affad9fa37053 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-07intel/soc: skl,apl,cnl,icl,tgl: add INTRUDER relevant registersMichael Niewöhner
Add registers that are relevant for the case intrusion detection functionality. Intel documents: 332691-003EN, 335193-006, 341081-001, ... Change-Id: If12d21e8e6721abb877cbbfbbba8f0127a86d96b Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39263 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-07intel/soc: skl,apl,cnl,icl,tgl,common: enable TCO SMIs if selectedMichael Niewöhner
Enable TCO SMIs in common code, if selected by Kconfig. This is needed for the follow-up commits regarding INTRUDER interrupt. Tested on X11SSM-F. Change-Id: If63effe74ac59b5d051a6454bc6375bb89605215 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 20:41:26 +0000