summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2013-04-29Google/Snow: Enable suspend/resume.Hung-Te Lin
Add the suspend/resume feature into bootblock and romstage. Note, resuming with X and touchpad driver may be still unstable. Verified by building and booting successfully on Google/Snow, and then executing the "suspend_stress_test" in text mode ("stop ui; suspend_stress_test") in Chromium OS, passed at least 20 iterations. Change-Id: I65681c42eeef2736e55bb906595f42a5b1dfdf11 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3102 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-04-26google/snow: Revise romstage initialization code.Hung-Te Lin
Move board setup procedure to snow_setup_* functions, and Snow board-specific (wakeup) code to snow_* for better function names and comments. Verified by successfully building and booting on Google/Snow. Change-Id: I2942d75064135093eeb1c1da188a005fd255111d Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3130 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-04-26Intel 82801gx: Use 2 << 24 to clarify that I/O APIC ID is 2Paul Menzel
Commit »Support for the Intel ICH7 southbridge.« (debb11fc) [1] used `1 << 25` to set the I/O APIC ID of 2. Instead using `2 << 24`, which is the same value, makes it clear, that the I/O APIC ID is 2. Commit »Intel Panther Point PCH: Use 2 << 24 to clarify that APIC ID is 2« (8c937c7e) [2] is used as a template. [1] http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=debb11fc1fe5f5560015ab9905f1ccc2e08c73e0 [2] http://review.coreboot.org/3100 Change-Id: Ib688500944cd78a1cc1c8082bb138fa9468bdbfb Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3122 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-26exynos5250: uncomment $(INTERMEDIATE)David Hendricks
This makes the intermediate rule visible so BL1 gets automatically placed in the final image. Change-Id: Iffb0268e5bbcbe135f2d39863ed64fa302409a22 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3141 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-04-26armv7: invoke intermediate build rulesDavid Hendricks
This adds $$(INTERMEDIATE) as a pre-requisite for coreboot.rom on armv7. It is modeled after the $(obj)/coreboot.rom rule for x86. Change-Id: I483a88035fa2288829b6e042e51ef932c8c4f23c Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2095 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-25google/snow: Add "wakeup" module for suspend/resume.Hung-Te Lin
The "wakeup" procedure will be shared by bootblock and romstage for different types of resume processes. Note, this commit does not include changes in romstage/bootblock to enable suspend/resume feature. Simply adding functions to handle suspend/resume. Verified by successfully building and booting Google/Snow firmware image. Change-Id: I17a256afb99f2f8b5e0eac3393cdf6959b239341 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3129 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-25arm/exynos: Allow DRAM controller to be initialized without clearing RAM ↵Hung-Te Lin
content. To support suspend/resume, PHY control must be reset only on normal boot path. So add a new param "mem_reset" to specify that. Verified to boot successfully on Google/Snow. Change-Id: Id49bc6c6239cf71a67ba091092dd3ebf18e83e33 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3128 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-23AMD Thatcher: ConnectorTypeDP supports both DP and HDMISiyuan Wang
It seems that ConnectorTypeDP in DdiList supports both DP and HDMI monitors. I tested by DP monitor and HDMI monitor connected by passive DP->HDMI adapter. Video and audio are OK. Hot plugging is also supported. This commit partially reverts commit >AMD Thatcher: Fix PCIE link issues< (7f23aeb0) [1]. [1] http://review.coreboot.org/3011 Change-Id: I23cf1c69a8274f47daf56f1a12aafd88bad4a128 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3088 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-23GOOGLE/SNOW: get graphics workingRonald G. Minnich
This adds support for display bring-up on Snow. It includes framebuffer initialization and LCD enable functions. Change-Id: I16e711c97e9d02c916824f621e2313297448732b Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3116 Tested-by: build bot (Jenkins)
2013-04-23Intel microcode: Return when `microcode_updates` is `NULL`Vladimir Serbinenko
Add a safety check in function `intel_update_microcode` to return when accidentally `NULL` is passed as `microcode_updates`, which would lead to a null pointer dereference later on. for (c = microcode_updates; m->hdrver; m = (const struct microcode *)c) { While at it, use `return NULL` for clarity in function `intel_microcode_find` and include the header file `stddef.h`. for it. The review of this patch had some more discussion on adding more comments and more detailed error messages. But this should be done in a separate patch. For clarity here some history, on how this was found and what caused the discussion and confusion. Originally when Vladimir made this improvement, selecting `CPU_MICROCODE_IN_CBFS` in Kconfig but not having the microcode blob `cpu_microcode_blob.bin` in CBFS resulted in a null pointer dereference later on causing a crash. for (c = microcode_updates; m->hdrver; m = (const struct microcode *)c) { Vladimir fixed this by returning if `microcode_updates` is `NULL`, that means no file is found and successfully tested this on his Lenovo X201. When pushing the patch to Gerrit for review, the code was rewritten though by Aaron in commit »intel microcode: split up microcode loading stages« (98ffb426) [1], which also returns when no file is found. So the other parts of the code were checked and the safety check as described above is added. [1] http://review.coreboot.org/2778 Change-Id: I6e18fd37256910bf047061e4633a66cf29ad7b69 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2990 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2013-04-23exynos5250: ungate the product ID registerDavid Hendricks
This makes sure that the product ID (PRO_ID) register can be read when the OS kernel is figuring out what kind of CPU it's running on. For historical reference, the original U-Boot code seems to have worked basically by accident here. The hardware has a quirk where by reading the value before gating the IP block keeps the value persistent. U-Boot reads the chip ID early on to distinguish between chip family, but we do not mix code the same way so we do not read the chip ID. Since the value has been read before the clock gating happens, the value remains available for the kernel to use during the decompression stage. We don't want to rely on that behavior when using coreboot. Instead the kernel should gate unused IPs. (credit to Gabe for finding symptom in the kernel) Change-Id: Iaa21e6e718b9000b5558f568020f393779fd208e Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3121 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-04-22GOOGLE/SNOW: fix stupid paren errorRonald G. Minnich
This simple error led to corrupted graphics. How annoying. Change-Id: I2295c0df0f1d16014a603dc5d66bd4d72f3fb7c9 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/3120 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2013-04-20AMD SB800 based boards: Use `#include <sb_cimx.h>` instead of `"sb_cimx.h"`Paul Menzel
Due to $ more src/southbridge/amd/cimx/sb800/Makefile.inc […] romstage-y += cfg.c romstage-y += early.c romstage-y += smbus.c ramstage-y += cfg.c ramstage-y += late.c […] `src/southbridge/amd/cimx/sb800/` is passed with the switch `-I` to the compiler, where it is also going to find the header file `sb_cimx.h`. Therefore use `#include <sb_cimx>` everywhere, which is what some AMD SB800 based boards already do. The only effect is, that the compiler will not needlessly look into directories which do not contain the header file [1]. The following command was used for the replacement. $ git grep -l sb_cimx.h src/mainboard/ | xargs sed -i 's/#include "sb_cimx.h"/#include <sb_cimx.h>/' [1] http://gcc.gnu.org/onlinedocs/cpp/Search-Path.html Change-Id: I96ab34bac1524e6c38c85dfe9d99cb6ef55e6d7c Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3118 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-20Eliminate use of pointers in coreboot tableStefan Reinauer
Because pointers can be 32bit or 64bit big, using them in the coreboot table requires the OS and the firmware to operate in the same mode which is not always the case. Hence, use 64bit for all pointers stored in the coreboot table. Guess we'll have to fix this up once we port to the first 128bit machines. Change-Id: I46fc1dad530e5230986f7aa5740595428ede4f93 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3115 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-04-19google/snow: disable unused USB3.0 PLL to save powerDavid Hendricks
This PLL is unused and can be disabled to save about 250mW. Change-Id: I1be37304d6ea5ff78696e05ad1023ce3c57f636c Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3109 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-19exynos5: eliminate lcd_base variableDavid Hendricks
The original imported code used "lcdbase" and "lcd_base" which quite predictably caused confusion and bugs. Let's put an end to this little bit of insanity. Change-Id: I4f995482cfbff5f23bb296a1e6d35beccf5f8a91 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3114 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-04-19google/snow: Minor clean-ups for display setup code in ramstageDavid Hendricks
This just cleans up a few areas: - Removed an unnecessary delay from exynos_dp_bridge_setup() - The delay at the end of exynos_dp_bridge_init() is necessary, so removed the comment suggesting that it might not be. - Simplified exynos_dp_hotplug Change-Id: I44150f5ef3958e333985440c1022b4f1544a93aa Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3113 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-19google/snow: enable clock gating to save powerDavid Hendricks
This enables clock gating to save power on unused IPs. Change-Id: I9ab2a2535ebb91bb4110390a6f055a67146bdbf9 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3110 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-19AMD Parmer: change DdiList to ConnectorTypeDP to support DP and HDMISiyuan Wang
This patch is based on >>AMD Thatcher: ConnectorTypeDP supports both DP and HDMI<< (I23cf1c6) [1] I tested by DP monitor and HDMI monitor connected by passive DP->HDMI adapter. Video and audio are OK. Hot plugging is also supported. [1] http://review.coreboot.org/#/c/3088/ Change-Id: I291beff43609ecb68ece24939f2dbc7c08dd0374 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3090 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-19exynos5250: get xres and yres out of the device tree and into the panel ↵Ronald G. Minnich
descriptor We neglected to copy xres and yres out; now we do. Change-Id: Icc4a8eb35799d156b11274f71bcfb4a1d10e01e3 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/3111 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2013-04-19[3/3] google/snow: enable TMUDavid Hendricks
This enables the thermal management unit (TMU) on Snow. Change-Id: Idd76af40bf0a5408baf61ef2665fd52ae4e260ba Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3108 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-04-19[2/3] exynos5: modify thermal management unit code for corebootDavid Hendricks
This updates the Exynos TMU code for coreboot: - Remove dependency on device tree - Add Makefile entries Change-Id: I55e1b624d7c7b695b1253ec55f6ae3de8dc671bc Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3107 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-04-19[1/3] exynos5: import thermal management unit codeDavid Hendricks
This simply imports the Exynos TMU driver from u-boot. It is not built and thus should not break anything. Change-Id: I7861132fbf97f864e4250ffbda1ef3843f296ddc Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3106 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-04-19exynos5: move power_enable_hw_thermal_trip() prototypeDavid Hendricks
This moves the prototype for power_enable_hw_thermal_trip() to a generic location so it can be used by generalized thermal management code. The implementation will still be CPU-specific. Change-Id: Iae449cb8c72c8441dedaf65b73db9898b4730cef Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3105 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-04-18spkmodem consoleVladimir Serbinenko
Change-Id: Ie497e4c8da05001ffe67c4a541bd24aa859ac0e2 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/2987 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-18AMD/SB800: Define the GPP PCIe lane distributionDave Frodin
Commit 23023a5 correctly enabled the SB800 GPP PCIe ports but didn't distribute the 4 GPP PCIe lanes amongst the enabled PCIe ports. This fix was verified by openvoid on a AsRock E350M1 motherboard. Change-Id: I0116c5f518e0d000be609013446e53da4112f586 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/3104 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-18AMD Fam14: Split out the AMD Fam14 DSDTMike Loptien
Same splitting as done on Persimmon and ASRock. Moving common DSDT code to common areas and adding new files as necessary. Boards updated are: Inagua Union-Station South-Station Change-Id: I8c9eea62996b41cea23a9c16858c4249197f6216 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/3051 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-18Intel i945: ACPI: Add _OSC methodDenis 'GNUtoo' Carikli
Add the ACPI Operating System Capabilities Method and let the operation system control everything. Commit »AMD Fam14 DSDT: Add OSC method« (00a0e76b) [1] is used as a template. The Lenovo X60 [2] running the Parabola GNU/Linux distribution [3] is used for testing. Before that change: $ dmesg | egrep -e OSC -e ASPM [ 0.108036] pci_root PNP0A08:00: ACPI _OSC support notification failed, disabling PCIe ASPM [ 0.108040] pci_root PNP0A08:00: Unable to request _OSC control (_OSC support mask: 0x08) [ 0.118089] ACPI _OSC control for PCIe not granted, disabling ASPM [ 16.874569] e1000e 0000:01:00.0: Disabling ASPM L0s L1 With that change: $ dmesg | egrep -e OSC -e ASPM [ 0.107962] pci_root PNP0A08:00: Requesting ACPI _OSC control (0x1d) [ 0.108003] pci_root PNP0A08:00: ACPI _OSC control (0x1d) granted [ 0.111052] pci 0000:01:00.0: disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force' [ 17.537970] e1000e 0000:01:00.0: Disabling ASPM L0s L1 [1] http://review.coreboot.org/2738 [2] http://www.coreboot.org/Lenovo_x60x [3] https://parabolagnulinux.org/ Change-Id: I1caffa44eea447d553c01caaf431f2db241ea5ea Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2938 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-18ChromeEC: Drop unneeded Kconfig variable EC_GOOGLE_API_ROOTStefan Reinauer
This used to contain the path for the EC include files, but those files are included in coreboot now. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I4fce9831c5e21b0a69a6295dbda2580e1ca83369 Reviewed-on: https://gerrit.chromium.org/gerrit/47606 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3057 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-17armv7/exynos5250: Deprecate sdelay in favor of udelayDavid Hendricks
This gets rid of the clock-tick based sdelay in favor of udelay(). udelay() is more consistent and easier to work with, and this allows us to carry one less variation of timers (and headers and sources...). Every 1 unit in the sdelay() argument was assumed to cause a delay of 2 clock ticks (@1.7GHz). So the conversion factor is roughly: sdelay(N) = udelay(((N * 2) / 1.7 * 10^9) * 10^6) = udelay((N * 2) / (1.7 * 10^3)) The sdelay() periods used were: sdelay(100) --> udelay(1) sdelay(0x10000) --> udelay(78) (rounded up to udelay(100)) There was one instance of sdelay(10000), which looked like sort of a typo since sdelay(0x10000) was used elsewhere. sdelay(10000) should approximate to about 12us, so we'll stick with that for now and leave a note. Change-Id: I5e7407865ceafa701eea1d613bbe50cf4734f33e Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3079 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-17google/snow: enable 32KHz sleep clockDavid Hendricks
Change-Id: I9db91826e4534b8a6eea2b13bcf7c6abd848b4e4 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3075 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-17Samsung/exynos5250: convert unsigned {int,char} to u32/u8Ronald G. Minnich
The types are (esp. int) are confusing at times as to size. Make them definite as to size. Change-Id: Id7808f1f61649ec0a3403c1afc3c2c3d4302b7fb Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/3103 Tested-by: build bot (Jenkins) Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-04-16AMD Parmer: remove unused macros and turn off unused pcie portSiyuan Wang
1) The macros GNB_GPP_PORTx_PORT_PRESENT, GNB_GPP_PORTx_SPEED_MODE, GNB_GPP_PORTx_LINK_ASPM and GNB_GPP_PORTx_CHANNEL_TYPE are not used. This is based on >AMD Thatcher: remove unused macros in PlatformGnbPcieComplex.h< [1]. 2) Disable unused PCIE port in devicetree.cb. PCIE port 3 is not used in Parmer. This is based on item 3 of >AMD Thatcher: Fix PCIE link issues< [2]. [1] http://review.coreboot.org/#/c/3087/ [2] http://review.coreboot.org/#/c/3011/ Change-Id: Id6f00d5e77ce5133d9ef3db07f95ad03a59e061a Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3099 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-16Intel Panther Point PCH: Use 2 << 24 to clarify that APIC ID is 2Vladimir Serbinenko
Commit »Add support for Intel Panther Point PCH« (8e073829) [1] used `1 << 25` to set the APIC ID of 2. Using `2 << 24`, which is the same value, instead makes it clear, that the APIC ID is 2. [1] http://review.coreboot.org/853 Change-Id: I5044dc470120cde2d2cdfc6e9ead17ddb47b6453 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3100 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-04-16snow: Return 0 from get_recovery_mode_from_vbnv.Gabe Black
This function isn't yet used for much, or perhaps anything, but where it appears in the code it's ored with other values. Since we're not actually retrieving anything, it might be best to return 0 so that the other values that are being ored in can be expressed and this function can stay dormant until it actually has something to do. Change-Id: I6edc222a5c2d00ece2ecfad5191a615331eeaf16 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3098 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2013-04-16snow: Report the state of the power button GPIO in the coreboot tables.Gabe Black
Change-Id: Ia7ce2b7342e186c565b92211e3ac15d80ce24b38 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3097 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2013-04-16snow: Configure the power button as an input GPIO.Gabe Black
We need to read it to report its value to the payload. The kernel will reconfigure it as an external interrupt, but we'll make it a regular input for now. Change-Id: I019bd2c2731144d3b7bb53fad0c2c903874f616c Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3096 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-04-16snow: Fix the name of some constants in romstage.c.Gabe Black
These names were inherited from chromeos.c where they've already been fixed. Change-Id: I7ad57b979b7b8f42f6bd68d1ecf887caba3fa3f1 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3095 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2013-04-16snow: Get rid of the oprom loaded GPIO.Gabe Black
ARM doesn't use option ROMs, so this value doesn't make sense. Change-Id: I1a0f0854e1dd4b9594ca0c147e590337520436da Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3094 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2013-04-16snow: Tidy up chromeos.c.Gabe Black
Got rid of a lot of #defines, some of which were converted to enums and the rest which were eliminated entirely. Got rid of cruft in get_developer_mode_switch and started using it for the dev mode GPIO. Instead of a macro defining how many GPIOs are expected, now the code actually counts the GPIOs as they're added. Change-Id: I97b6b9f52a72d1276eb3cf36d7f9dd7b335b4d19 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3093 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2013-04-16snow: Add support for EC based recovery.Gabe Black
Implement the get_recovery_mode_switch function using the newly added I2C based Chrome EC support. Change-Id: I9d0200629887f202edf017cba3222a7d7f5b053e Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3092 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2013-04-16snow: Fix some comments in chromeos.c.Gabe Black
The comment about the lid switch was left over from when this file was copied from another board and was incorrect. Also fixed a capitalization inconsistency. Change-Id: Icefd19047971e13c08f615578e4a181e82a2997f Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3091 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2013-04-16Lenovo ThinkPad X60: Add Native VGA init.Denis 'GNUtoo' Carikli
The code has been taken from the google link mainboard and modified to fit the ThinkPad X60. Change-Id: Ie16e45163acdc651ea46699ecc33055bfd34099c Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/2998 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-16ec/google: Move plug-n-play initialization to LPC protocol.Hung-Te Lin
"Plug-n-play" is not supported on all platforms using Google's Chrome EC. For example, EC on I2C bus will need explicit configuration and initialization. So move the plug-n-play initialization to the LPC implementation. Verified by building Google/Link (with EC/LPC) successfully. Change-Id: I49e5943503fd5301aa2b2f8c1265f3813719d7e3 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3089 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-16ec/google: Support Google's Chrome EC on I2C interface.Hung-Te Lin
Google's Chrome EC can be installed on LPC or I2C bus, using different command protocol. This commit adds I2C support for devices like Google/Snow. Note: I2C interface cannot be automatically probed so the bus and chip number must be explicitly set. Verified by booting Google/Snow, with following console output: Google Chrome EC: Hello got back 11223344 status (0) Google Chrome EC: version: ro: snow_v1.3.108-30f8374 rw: snow_v1.3.128-e35f60e running image: 1 Change-Id: I8023eb96cf477755d277fd7991bdb7d9392f10f7 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3074 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-16AMD AGESA: Fix argument list for `PCIE_DDI_DATA_INITIALIZER` in commentsPaul Menzel
When looking into possible reasons for a proposed revert [1], I noticed that the comments use four arguments for `PCIE_DDI_DATA_INITIALIZER`, but the actual definition only uses three. $ git grep -A1 PCIE_DDI_DATA_INITIALIZER # manually squeeze whitespace in output […] -- src/vendorcode/amd/agesa/f10/AGESA.h:#define PCIE_DDI_DATA_INITIALIZER(mConnectorType, mAuxIndex, mHpdIndex ) \ src/vendorcode/amd/agesa/f10/AGESA.h-{mConnectorType, mAuxIndex, mHpdIndex} -- src/vendorcode/amd/agesa/f10/AGESA.h: * PCIE_DDI_DATA_INITIALIZER (ConnectorType src/vendorcode/amd/agesa/f10/AGESA.h- * }, -- src/vendorcode/amd/agesa/f10/AGESA.h: * PCIE_DDI_DATA_INITIALIZER (ConnectorType src/vendorcode/amd/agesa/f10/AGESA.h- * } -- […] So remove the fourth argument in the comments. Luckily the compiler, at least gcc, warns about a wrong number of arguments, and therefore no incorrect code resulted from the wrong documentation. [1] http://review.coreboot.org/#/c/3077/ Change-Id: I3e5a02c66a23af1eb2d86be8dbc7aaa3e5cea05e Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3080 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-15Fam14 DSDT: Also return for unrecognized UUID in _OSCMike Loptien
Fixing warnings introduced by the following patches: http://review.coreboot.org/#/c/2684/ http://review.coreboot.org/#/c/2739/ http://review.coreboot.org/#/c/2714/ These patches were meant to fix the dmesg warning about the OSC method not granting control appropriately. These patches then introduced warnings during the coreboot build process which were missed during the patch submission process. These warnings are below: Intel ACPI Component Architecture ASL Optimizing Compiler version 20100528 [Oct 15 2010] Copyright (c) 2000 - 2010 Intel Corporation Supports ACPI Specification Revision 4.0a dsdt.ramstage.asl 1143: Method(_OSC,4) Warning 1088 - ^ Not all control paths return a value (_OSC) dsdt.ramstage.asl 1143: Method(_OSC,4) Warning 1081 - ^ Reserved method must return a value (Buffer required for _OSC) ASL Input: dsdt.ramstage.asl - 1724 lines, 34917 bytes, 889 keywords AML Output: dsdt.ramstage.aml - 10470 bytes, 409 named objects, 480 executable opcodes Compilation complete. 0 Errors, 2 Warnings, 0 Remarks, 494 Optimizations This patch gives the following compilation status: Intel ACPI Component Architecture ASL Optimizing Compiler version 20100528 [Oct 1 2012] Copyright (c) 2000 - 2010 Intel Corporation Supports ACPI Specification Revision 4.0a ASL Input: dsdt.ramstage.asl - 1732 lines, 33295 bytes, 941 keywords AML Output: dsdt.ramstage.aml - 10152 bytes, 406 named objects, 535 executable opcodes Compilation complete. 0 Errors, 0 Warnings, 0 Remarks, 432 Optimizations The fix is simply adding an Else statement to the If which checks for the proper UUID. This way, all outcomes will return a full control package. This patch has no effect on the dmesg output. Change-Id: I8fa246400310b26679ffa3aa278069d2e9507160 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/3052 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-15Drop add_mainboard_resources and HAVE_MAINBOARD_RESOURCES againKyösti Mälkki
These are not defined since commit »Drop HAVE_MAINBOARD_RESOURCES« (1c5071d1) [1] but were unfortunately introduced again in new ports. [1] http://review.coreboot.org/1414 Change-Id: I5eb61628141aefd08779615702d51ca155fa632a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/2707 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-04-14AMD CIMx sb800/SATA.c, sb900/Sata.c: Fix R*AI*D typo in commentsPaul Menzel
Spell RAID correctly in comments. Found with the following command. $ git grep -i riad Change-Id: I68e8476d885a88df589d25f88cc158d71eb04e07 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3081 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-14link/graphics: Remove the inclusion of an AMD header.Denis 'GNUtoo' Carikli
link(google chromebook pixel) is an intel machine. Change-Id: I9d40f1e945021d8e190879477cd12be7d0262733 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/3085 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-03 10:13:15 +0000