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2017-08-04mainboard/google/soraka: Add gpio.c to bootblockFurquan Shaikh
Add gpio.c to bootblock so that the variant early_gpio_table can be used for configuration in bootblock. BUG=b:64181150,b:62726961 Change-Id: I77181334257f2fd19982ecafc1f58afe912f4280 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-04southbridge/pi/hudson: Fix GPIO bank1 control definitionMarshall Dawson
Change-Id: I3ef3ea3ea22faa0152d99923da2e57517ab3d0be Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-04soc/intel/common: Add Cannonlake pci ids for commonLijian Zhao
Add Cannonlake pci device ids for all the merged intel common code. As of now only have CNL-U and CNL-Y pci ids. Change-Id: Iee5087cdeba53919d83ff665d0c417075279294c Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-08-04google/kahlee: Add ChromeOS SMBIOS Board IDMarc Jones
Kahlee uses 3 GPIO(144, 140, 135) pins to identify the board revision. Change-Id: Ia9693db6d6506af7ff40db0b3ce4cc6c1469f6ef Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-04soc/amd/stoneyridge: Use generic gpio libraryMarc Jones
Use the genric GPIO library. Add the required functions. Also, update the Kahlee mainboard dependency to match. Change-Id: I2ea562b052401efff3101f736788ca77d21e6de6 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20543 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-04lib/cbmem: provide optional cbmem top initialization hookAaron Durbin
Provide a hook to allow an optional one-time cbmem_top() initialization. The new function, cbmem_top_init(), is called on the first expected initialization of cbmem based on the Kconfig options LATE_CBMEM_INIT and EARLY_CBMEM_INIT. Change-Id: I89edd2d11f226217c8e2aaca829b4f375a2cff28 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-08-03lib/cbmem: use globals for non CAR global migration platformsAaron Durbin
For CAR platforms which don't migrate globals real globals can be directly used. This alleviates the need to peform partial recovery on every cbmem access which in turn acts like all non-CAR platforms or any stages which execute entirely out of RAM. Change-Id: I31c08dd6473324424d5d42fe6b56d42fe635929e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-08-03soc/intel/apollolake: Skip disabled IGD deviceSubrata Banik
If IGD PCI device is disabled: 1. BAR for the device will be 0. 2. There is no need to allocate framebuffer for this device. Some early SOCs don't have GFX model fuse by default hence we need to add a check to ensure PCI device is enable. This code to avoid die inside coreboot for missing resources. Change-Id: Ied677e8c77fa7b166b016da458caad0e4702b5d8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-03soc/intel/skylake: Skip disabled IGD deviceSubrata Banik
If IGD PCI device is disabled: 1. BAR for the device will be 0. 2. There is no need to allocate framebuffer for this device. Some early SOCs don't have GFX model fuse by default hence we need to add a check to ensure PCI device is enable. This code to avoid die inside coreboot for missing resources. Change-Id: Ic31d3e57ba730f6b569bf2cc3bdc54cb369b8caf Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-03soc/intel/cannonlake: Sort Kconfig for CannonlakeLijian Zhao
Look and feel update, sort the sequence in Kconfig. Change-Id: I41d99979d9c7d081086aac8bfef27186b37a6e70 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-03soc/intel/braswell/Kconfig: select RELOCATABLE_RAMSTAGEMatt DeVillier
Without RELOCATABLE_RAMSTAGE selected, S3 resume will hang under Linux and Windows. All other Intel SoCs have this selected by default, so this change simply corrects an omission on Braswell. TEST: boot Linux on google/cyan with and without RELOCATABLE_RAMSTAGE selected; observe that S3 resume fails without and succeeds with. Change-Id: I9071d9b4e3e3a156281d95fae059947c4c26f744 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/20819 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-03google/kahlee: Add Realtek audio codec ASLIvy Jian
Add the RT5650 codec ASL for proper Linux driver loading. Devices visible to OS: /sys/bus/acpi/devices/AMDI1002:00 /sys/bus/acpi/devices/I2SC1002:00 Change-Id: I60b256f68372c9d17d67c9cb2accaca616a0b9a5 Signed-off-by: Ivy Jian <ivy_jian@compal.com> Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-03intel/bd82x6x: Replace magic IOBP constants with known namesFelix Held
IOBP (I/O Buffer Programming) is an interface (indirect addresses space) in the RCBA that is used to configure the high speed serial lanes on the PCH, that are used for PCIe, USB3 and SATA. This patch replaces the offsets in RCBA with the defines from pch.h, gives the access functions and their parameters useful names and replaces two magic addresses in IOBP space with their defines. Change-Id: I91a828ed076ca10733b47db876fabf5adaa63638 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/16214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-03lib/cbmem: remove cbmem_region_used()Aaron Durbin
The cbmem_region_used() function wasn't being utilized outside this module. Threfore, reduce the surface area. Change-Id: I28a9d02221048ab0aa4cd3d986d17ee7692ce636 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-08-03lib/imd_cbmem: remove unused #includeAaron Durbin
Change-Id: I18a08faa5f9f5330cdb509c27a8ab7a3aa8e5b73 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-08-03lib/imd_cbmem: remove unused funcitonAaron Durbin
The cbmem_fail_recovery() function was no longer used. I'm not sure why the compiler never complained. Regardless, delete it. Change-Id: I7d94118068064c61252d1b5ca9d8e92658a699e0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-08-02soc/nvidia/tegra*: force using our headers instead of compiler's/system'sPatrick Georgi
The code doesn't include much, but when compiled outside the coreboot build (what the shipped Makefile is made for), we want to make sure that the few files it includes are controlled by us. TEST=`cd src/soc/nvidia/tegra124/lp0; make CC=arm-eabi-gcc` works Change-Id: Ic2f1e4aa4047617b048ef7ef98d71f9d540ccd74 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/20860 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-02AGESA: Correct PCI function number for MEM_GET(SET)REG outputsKonstantin Aladyshev
PCI function number takes only 3 bits, therefore correct bitmask for it is 0x7. Change-Id: Id41700be0474eecc4d5b5173c4d5686c421735e3 Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com> Reviewed-on: https://review.coreboot.org/20837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-02AGESA f15: Support DMI generation for Opteron 63XX familyKonstantin Aladyshev
Add support of DMI tables for AMD Opteron 6300 Series Processors. Correct value for CPU family is taken from SMBIOS reference specification. Change-Id: I8c5d487c0f45f61deb081be50c6701a42fbf9111 Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com> Reviewed-on: https://review.coreboot.org/20838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-02binaryPI: Introduce BINARYPI_LEGACY_WRAPPER and its counterpartKyösti Mälkki
We define BINARYPI_LEGACY_WRAPPER a method of calling AGESA via functions in agesawrapper.c file. The approach implemented there makes it very inconvenient to do board-specific customisation or present common platform-specific features. Seems like it also causes assertion errors on AGESA side. The flag is applied here to all boards and then individually removed one at a time, as things get tested. New method is not to call AGESA internal functions directly, but via the dispatcher. AGESA call parameters are routed to hooks in both platform and board -directories, to allow for easy capture or modification as needed. For each AGESA dispatcher call made, eventlog entries are replayed to the console log. Also relocations of AGESA heap that took place are recorded. New method is expected to be compatible with binaryPI. Change-Id: I2900249e60f21a13dc231f4a8a04835e090109d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02binaryPI: Add dispatcher for PI blobKyösti Mälkki
Change-Id: I622d155fce3fa56cd5e24282e22de060fed560c3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02AGESA f15tn f16kb: Implement common FCH calloutKyösti Mälkki
This FCH_OEM_CALLOUT bypasses API and uses structures that are private to AGESA. Attempt to clean it up by first clarifying when it is used. Change-Id: I63aa0f586f73e97d615b8596d73728edbaeb0a2d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02binaryPI: Enable RELOCATABLE_RAMSTAGEKyösti Mälkki
Change-Id: I0c0058be002e409bd16d2d75fd404df94407df4e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02binaryPI: Enable EARLY_CBMEM_INITKyösti Mälkki
Also moves postcar stack to CBMEM. Change-Id: I0263af9561e0367bbbde4d5c3190039f4c3047a0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19347 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-08-02AGESA: Conditionally enable RELOCATABLE_RAMSTAGEKyösti Mälkki
Change-Id: Id199322db077fc5f112dfa45f8e9f72b9142a8fb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02AGESA: Add romstage timestampsKyösti Mälkki
Experiments on f14 f15tn and 16kb suggest that TSC counter value shifts at end of raminit. To account for this all previously stored values in timestamp table are also divided by 4. Change-Id: I47584997bf456e35cf0aeb97ef255748745c30ee Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02AGESA: Implement EARLY_CBMEM_INITKyösti Mälkki
Boards without AGESA_LEGACY_WRAPPER gain EARLY_CBMEM_INIT. This does not apply to family12 and family14 just yet, as they do invalidate without write-back on CAR teardown. Change-Id: I008356efa2bc3df0ed1f0720e225ecc7e9995127 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02AGESA: Split dispatcher to stagesKyösti Mälkki
Change-Id: Ide49e46c0b6aa5e1bf09354435a847a46bc797c9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02AGESA: Move romstage-ramstage splitlineKyösti Mälkki
In AGESA specification AmdInitEnv() is to be called once host memory allocator has started. In coreboot context this could mean either availability of CBMEM or malloc heap. As for AmdS3LateRestore(), there is no requirement to have it run as part of the romstage either. Change-Id: Icc8d97b82df89e2480e601d5c2e094de0365b0a5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02AGESA binaryPI: Unify agesawrapper headerKyösti Mälkki
Change-Id: I54c8553bc057798e595b28f6cbc07f7125ae074f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02AGESA: Consolidate platform_once() callKyösti Mälkki
Change-Id: I13d8df330db925b2eced7c123ca9926fb259646d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20621 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-08-02AGESA: Consolidate early_all_cores() callKyösti Mälkki
Change-Id: I7c3af493b9189bb75a58eb322646694b5a712745 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02AGESA: Introduce AGESA_LEGACY_WRAPPER and its counterpartKyösti Mälkki
We define AGESA_LEGACY_WRAPPER a method of calling AGESA via functions in agesawrapper.c file. The approach implemented there makes it very inconvenient to do board-specific customisation or present common platform-specific features. Seems like it also causes assertion errors on AGESA side. The flag is applied here to all boards and then individually removed one at a time, as things get tested. New method is not to call AGESA internal functions directly, but via the dispatcher. AGESA call parameters are routed to hooks in both platform and board -directories, to allow for easy capture or modification as needed. For each AGESA dispatcher call made, eventlog entries are replayed to the console log. Also relocations of AGESA heap that took place are recorded. New method is expected to be compatible with binaryPI. Change-Id: Iac3d7f8b0354e9f02c2625576f36fe06b05eb4ce Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02AGESA: Move agesawrapper_laterunaptask()Kyösti Mälkki
Change-Id: I916d808d1b2ecc4b70b5dfebff62c4a18119f157 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02AGESA: Refactor eventlog read loopKyösti Mälkki
Also avoid infinite loop. Change-Id: I7571f9efdc2bf0335788136b8c56e9290581d748 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02AGESA: Use common handler for ACPI tablesKyösti Mälkki
Change-Id: I2d6ab1026f1105f1fea97682442a169409248c39 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02AGESA: Sync ACPI table definitionsKyösti Mälkki
Change-Id: I09b094b3f129ac3e32608bcbe56f4b3f90c8946b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-01src/northbridge: Add guards on all header filesMartin Roth
Change-Id: I93b939478615f22f2c078b1efb7999ad4f3a4c28 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-08-01src/device: Add guards on all header filesMartin Roth
Change-Id: I8641f32ed2221f1d6e6dac884912251f64424f4d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-08-01src/acpi: Add guards on all header filesMartin Roth
Change-Id: I1b2d82a85194df6660bc041af8a690acc5469d02 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-08-01src/include: Add guards on all header filesMartin Roth
Change-Id: I2d7d4e0b25f2cf3eef2040f89d5ebc711909cdd7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-08-01src/cpu/amd/quadcore: Fix checkpatch errors/warningsEvelyn Huang
Fix over 80 character line warnings, unncessary braces for single statement blocks warnings, include space before and after =, <, > warnings, spaces after open parantheses warnings Change-Id: Ib0a28c12e209547b3625f4ca1696f9c26dc2b6d0 Signed-off-by: Evelyn Huang <evhuang@google.com> Reviewed-on: https://review.coreboot.org/19987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-08-01cpu/amd/pi: Fix checkpatch warnings and errorsEvelyn Huang
Fix remaining space prohibited between function name and open parenthesis, line over 80 characters, unnecessary braces for single statement blocks, space required before open brace errors and warnings in subdirectories of src/cpu/amd/pi Change-Id: I177ffe98a3674bd700a39eb8073db34adf9499b4 Signed-off-by: Evelyn Huang <evhuang@google.com> Reviewed-on: https://review.coreboot.org/20098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-08-01google/gru: Correct Scarlet pwm regulator minimum value and maximum valueLin Huang
In Scarlet pwm regulatoror minimum value and maximum value differs from other board variants, Correct it so we can get the right voltage. Change-Id: I1f722eabb697b3438d9f4aa29c205b0161eb442a Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/20831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-08-01google/gru: Correct the Sdcard control gpio setting for ScarletLin Huang
in Scarlet the Sdcard control gpio differs from other board variants, So set the GPIO to high on Scarlet. Change-Id: I5fa19b212a716213462eea58b6242392d32a2c5c Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/20803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-01google/gru: Use 1.8V powerdomain for gpio4cd on ScarletLin Huang
Scarlet gpio4cd use 1.8V powerdomain, let's make a correct register setting, otherwise even the uart does not work. Change-Id: Ib5a8b2a4d92502fb829688d0a3e1b645d53cd7fc Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/20802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-08-01soc/dmp/vortex86: Fix CMOS read and random RTC resetMartin Roth
The array of CMOS values that was passed into the read routine was never getting updated. GCC 7.1 gives a warning on this: error: may be used uninitialized in this function Change-Id: I2f7c9b6455761a38598467b001efb0603fd14c32 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-07-31google/kahlee: Add mainboard GPIOs to ACPIMarc Jones
Add the Google mainboard GPIOs to the ACPI table. Change-Id: I9b5952ed3934b938cb50650890a7b434e6306fd1 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-31google/kahlee: Fix CTRL+U USB bootMarc Jones
The EC KBC controller was not initialized, so the EC wouldn't put keys in the output buffer. With nothing in the buffer, vboot didn't try to boot the USB stick. Add the driver to setup the KBC called by EC init. BUG=b:62066405 BRANCH=none TEST=Boot Kahlee with USB stick and CTRL+U boots the stick. Change-Id: If9346fda558e802536c7de38da5b21fd25320e40 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20480 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-31google/kahlee: Move mainboard_ec_init to chip init phaseMarc Jones
Move mainboard_ec_init out of mainboard enable to the more appropriate mainboard init phase. Change-Id: Ieabcecf70e4de0b42fc639d031755b6d0b66f08a Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-13 06:17:33 +0000