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SATA is currently turned on in the Dalboz and Trembyle base board
variant devicetrees, even though no Google/Zork device uses SATA; for
mass storage they either use eMMC or NVME PCIe SSDs. This patch disables
both the SATA PCIe device and the bus where it was the only enabled
device on. The next patch in this patch train sets a new FSP-M UPD
setting
BUG=b:162302027
Change-Id: Ie7773d9dcb0518c3e01bdd0af23b62268ab64694
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44068
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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FSP has recently added support for a UPD switch to power gate SATA. This
change adds the coreboot side of the feature. To avoid having two SATA
enable options, the value of the sata_enable UPD is determined by the
enable state of the AHCI controller in the platform devicetree.
BUG=b:162302027
BRANCH=zork
TEST=Verify AHCI controller can be hidden/disabled.
Change-Id: I48bf94a7e6249db6079a6e3de7456a536d54a242
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44067
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:162302027
BRANCH=zork
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Change-Id: I4b5c3b351b6232f8b0418ead47d87aaddd350668
Cq-Depend: chrome-internal:3201648
Cq-Depend: chrome-internal:3202602
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44863
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tested on OCP Delta Lake, with FSP WW34 DCI can be connected if enabled.
Change-Id: I8e0dff921cef02dfc66467a2b8fa3e196fb36ac2
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Intel CPX-SP FSP ww34 release added some features:
a. change DDR frequency limit.
b. define MRC debug message verbosity level.
c. enable/disablee of PCH DCI.
In addition, there are some changes to HOB data structures.
Update UPD and HOB header files and adapt soc accordingly.
TESTED=booted on YV3 DVT to target OS command line. Also rebooted okay.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Iadbf5dc850c445f988bc7f07a24165abed2298c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44685
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These parts have not been used in any woomax devices. Removing
so IDs can be assigned more efficiently.
Command to generate files:
go build gen_part_id.go
local variant=woomax
./gen_part_id ../../../src/mainboard/google/zork/spd ../../../src/mainboard/google/zork/variants/${variant}/spd/ ../../../src/mainboard/google/zork/variants/${variant}/spd/mem_parts_used.txt
BUG=b:165611555
TEST=none
Change-Id: I651539c2df8e6d817582573d45b9e77156ece7d4
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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These parts have not been used in any berknip devices. Removing
so IDs can be assigned more efficiently.
Command to generate files:
go build gen_part_id.go
local variant=berknip
./gen_part_id ../../../src/mainboard/google/zork/spd ../../../src/mainboard/google/zork/variants/${variant}/spd/ ../../../src/mainboard/google/zork/variants/${variant}/spd/mem_parts_used.txt
BUG=b:165611704
TEST=none
Change-Id: I9020fc9cbbb4a97664b0c969dd841c5696a4d60f
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44871
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These parts have not been used in any dirinboz devices. Removing
so IDs can be assigned more efficiently.
Command to generate files:
go build gen_part_id.go
local variant=dirinboz
./gen_part_id ../../../src/mainboard/google/zork/spd ../../../src/mainboard/google/zork/variants/${variant}/spd/ ../../../src/mainboard/google/zork/variants/${variant}/spd/mem_parts_used.txt
BUG=b:165611271
TEST=none
Change-Id: I605550d44ba57d979df1bd5bef114f8ecc94fa3a
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44846
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In generating the potential spds the ddr4-spd-empty.hex was
accidentally omitted.
Generated from:
go run util/spd_tools/ddr4/gen_spd.go src/soc/intel/tigerlake/spd/ \
util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt TGL
Change-Id: Ic8b9449830fb5405ebf138ebd54f41b0f76ba584
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44908
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Switch all zork boards to use generated generic SPDs from spd_tools.
HMAA1GS6CMR6N-VK is unused by Ezkinil, and all other boards, so it was
removed.
picasso/Makefile.inc was updated to populate the 2nd APCB channel based
on APCB_POPULATE_2ND_CHANNEL. This removes the need to suffix spd
entires with _x1/_x2.
Command to generate files:
$ find src/mainboard/google/zork/variants/ -maxdepth 1 -type d | grep -v '/$' | while read b; do
n=$(basename ${b});
if [ "${n}" = "baseboard" ]; then
continue
fi
go run util/spd_tools/ddr4/gen_part_id.go src/mainboard/google/zork/spd \
src/mainboard/google/zork/variants/${n}/spd \
src/mainboard/google/zork/variants/${n}/spd/mem_parts_used.txt
done
BUG=b:162939176
TEST=Boot ezkinil and dalboz check dmidecod -t17
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I0553858f83d3d1e90cf35bece108768f004a29a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44480
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add mem_list_variant.txt, a list of memory parts used by elemi SKUs.
Add dram_id.generated.txt, a list of dram id's to use for each memory part.
Add Makefile.inc, to specify DDR4 and build the SPD file list.
BUG=b:165461530
TEST=none
Change-Id: I6dbcccf577161cc0c787775e2ac03e0c7039baef
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44650
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add memory parts needed by zork boards. Attributes are derived from data
sheets.
BUG=b:162939176
TEST=Compared generated SPDs with data sheets and checked in SPDs
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I67f205f9af24bbc5c12656be1f363a15fe975955
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44447
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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If a memory part is a x16 part that has two dies and only a single
rank, then the x16 describes the part width (since this solution will
need to be a stacked solution) and as such, we must translate the
DeviceBusWidth to the "die bus width" instead.
Change DeviceBusWidth variable name to PackageBusWidth to be more
descriptive
BUG=b:166645306, b:160157545
TEST=run gen_spd and verify that spds for parts matching description
above changed appropriately.
Change-Id: Ia6f3ca109d344b7a015da28125a94ce10d2bdfb8
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The TS_DONE_LOADING timestamp description had "(ignore for x86)", but
the implementation in vboot_logic.c will read every bytes, so the
timestamp is correct even for devices with memory mapped boot device
(e.g., x86).
To prevent confusion we should remove the 'ignore for x86' message.
BUG=None
TEST=make -j
BRANCH=None
Change-Id: I01d11dd3dd0e65f3a17adf9a472175752c2b62bc
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44800
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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I noticed that re-running the lpddr4x SPD parts id tool that generates
the variants/VARIANT_NAME/memory/Makefile.inc changed the SPD that is
used for the H9HCNNNCPMMLXR-NEE part.
$ go run ./util/spd_tools/lp4x/gen_part_id.go \
src/soc/intel/tigerlake/spd src/mainboard/google/volteer/variants/delbin/memory
src/mainboard/google/volteer/variants/delbin/memory/mem_list_variant.txt
Based on the currently checked in generic SPDs for LPDDR4x, this
operation changes the Makefile.inc to use lp4x-spd-3.hex for the
H9HCNNNCPMMLXR-NEE part instead of lp4x-spd-2.hex.
This change updates that discrepancy in Delbin's memory Makefile.inc.
BUG=none
TEST=none
Change-Id: I9a19ab7b1bcdc3814fdd9c462ca2f590c8ed2935
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44785
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a SPI-NOR flash controller which supports pio mode.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: I1e38672a532dd8234b3ef24c84113888c8795810
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Change lp4x spd names to include lp4x memory type (eg. lp4x-spd-1.hex).
BUG=b:160157545
TEST=run gen_part_id for volteer variants and verify that it changed
spd names to prepend the "lp4x-" to the filename..
Change-Id: I0c59da7eb78f34640aad2e852ca725d3e8571a8e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44784
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Now that generic SPD files have the memory type prepended to the
filename, they can be stored in the same location. This CL moves
the generic SPDs to the new location.
Change the ddr4 gen_part_id.go and gen_spd.go tools to use
"ddr4_spd_manifest.generated" instead of "spd_manifest.generated".
Change the lpddr4x gen_part_id.go and gen_spd.go tools to use
"lp4x_spd_manifest.generated" instead of "spd_manifest.generated".
Move TGL DDR4 and LPDDR4x generic SPDs into a common location.
Move JSL DDR4 and LPDDR4x generic SPDs into a common location.
Change the volteer/spd/Makefile.inc to use the new path for the spds.
Change the dedede/spd/Makefile.inc to use the new path for the spds.
BUG=b:165854055
TEST="emerge-volteer coreboot" and verify all variants build correctly.
Change-Id: I83b088cb718d15ffd3012c84a12b5231ae84a3e4
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44648
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It seems that GCC's LTO doesn't like the way we implement
DECLARE_OPTIONAL_REGION(). This patch changes it so that rather than
having a normal DECLARE_REGION() in <symbols.h> and then an extra
DECLARE_OPTIONAL_REGION() in the C file using it, you just say
DECLARE_OPTIONAL_REGION() directly in <symbols.h> (in place and instead
of the usual DECLARE_REGION()). This basically looks the same way in the
resulting object file but somehow LTO seems to like it better.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I6096207b311d70c8e9956cd9406bec45be04a4a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Enable IPU for Volteer and Volteer2 variants for MIPI camera.
BUG=165340186
BRANCH=None
TEST=IPU is enabled and shows in lspci.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I66d60474e16c7a9aa8006d42b22510c1495dbd84
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44628
Reviewed-by: Daniel H Kang <daniel.h.kang@intel.corp-partner.google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set psyspl2 to 97% of adapter rating, based on our experiment results.
BUG=b:160676773
TEST=Built and check firmware log.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I4b621a8cc1749ee52a9f16a7ad2ae7a7aa0f7a5a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
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Add additional Elkhart Lake specific SA IDs.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I41af9b17b8121f3b47f2242d9beeec297893b378
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40854
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Praveen HP <praveen.hodagatta.pranesh@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add Elkhart Lake B0 CPU ID.
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I90fab9a6392443005ee7224049931c687cb77c0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
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DRIVERS_WIFI_GENERIC is a dependency for these SAR settings.
However, coreboot.org builders are not failing, but chromium
builders are only for serial configurations. It's not clear as
to why. Either way correct this.
BUG=b:159304570
Change-Id: I978b622a3a5a2490b0e3aaa14c24807d5afdff9a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44825
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The gpio_common.h needs EINT_BASE from addressmap.h.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: I20834e38343410526da0a489fed907acbf479d02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Most of the code is generated using autoport.
Working:
* booting Arch Linux from SeaBIOS
* PCIe/SATA/USB ports (see overridetree and early_init for lists)
* LVDS, DisplayPort, VGA, 3.5 mm jacks, RJ-45
* keyboard, touchpad
* C-States, S3 suspend
Not working:
* rfkill hotkey
* color of the mute hotkey
* sleep f-key
Untested:
* internal speakers and microphone (defective on my machine)
* FireWire
* docking station
* TPM (SeaBIOS detects it, no further test done)
Signed-off-by: Pablo Stebler <pablo@stebler.xyz>
Change-Id: I916583fad375f16e5b02388cbcad2e8a993e042f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Based on schematic and gpio table of lindar, generate gpio and
overridetree.cb settings for lindar.
BUG=b:161089195
TEST=FW_NAME=lindar emerge-volteer coreboot chromeos-bootimage
Signed-off-by: Julia Tsai <julia.tsai@lcfc.corp-partner.google.com>
Change-Id: Ib869eef08433dab367edd46b3dc577190b6673d8
Signed-off-by: rasheed.hsueh <rasheed.hsueh@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
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Rename the pch_init function to bootblock_pch_init and romstage_pch_init
according to the stage it is defined in.
TEST=successfully built and booted TGLRVP
Signed-off-by: Alexey Buyanov <alexey.buyanov@intel.com>
Change-Id: Ib7450fcdc3024dfb5e375a54f9bdcdca9bc373d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: I2cc38115c27cbbe157fc850bbd88b10ae8001f52
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Returning a const uint32_t doesn't do anything, and it conflicts with the
declaration of sku_id() in include/boardid.h.
Change-Id: I2719e5782c9977f8ca4ce8f1dd781f092aa73d64
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1428708
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44746
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TS:
ELAN 5015M
G2 GTCH7503 HID TS
TP:
ELAN i2c-hid touchpad
BUG=b:161579679
BRANCH=master
TEST=1. emerge-zork coreboot chromeos-bootimage
2. power on proto board successfully
3. TP/TS are functional
Change-Id: I54aa16d433b6d71a39cca2ddd026a33e4741320f
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Follow HW schematic to correct DDSP_HPD1/2/3 and USB_OC3 pin.
BUG=b:165175296
BRANCH=none
TEST=Check all USB ports USB2 and USB3 both functional
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I2f941141d761b1b69bc8f9ef0b0c4516062fec4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Removing entry covering root region leads to situation where
num_entries counter is set to 0. This counter is further decremented
in function obtaining address to last entry (see root_last_entry()).
Such negative number may be further used as an index to the table.
Current implementation may lead to crash, when user removes last entry
with imd_entry_remove() and then calls for example imd_entry_add().
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I6ff54cce55bf10c82a5093f47c7f788fd7c12d3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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One of the checks inside imdr_recover() was written with the
assumption that imdr limit is always aligned to LIMIT_ALIGN. This is
true only for large allocations, thus may fail for small regions.
It's not necessary to check if root_pointer is under the limit, since
this is implicitly verified by imdr_get_root_pointer().
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I25d6291301797d10c6a267b5f6e56ac38b995b7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Previously it was allowed to create an imd_entry with size 0, however
algorithm sets the offset of such entry to the exact same address as
the last registered entry.
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: Ifa2cdc887381fb0d268e2c199e868b038aafff5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Add a check that root_size provided by the caller accounts for one
imd_entry necessary for covering imd_root region. Without this, we
may end up with writing on unallocated memory.
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I0a39d56f7a2a6fa026d259c5b5b78def4f115095
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I8261c7d933435ba9f29fc3172cdfe8bcae5c1af9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Get rid of the second check whether r is NULL (this is already done by imdr_has_entry()).
Signed-off-by: Anna Karas <aka@semihalf.com>
Change-Id: Ibee1664ee45b29d36e2eaaa7dff4c7cc1942010b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Remove the repetition from the comment.
Signed-off-by: Anna Karas <aka@semihalf.com>
Change-Id: Ibe6e38636b96b6d8af702b05a822995fd576b2fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44662
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Includes changes related to GPIO pad to configure I2C4 required for UFC
Change-Id: Ica3ac31f10214b8aff3bb64a2c3b42ccfa28bdcd
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
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This change updates devicetree to enable I2C4 bus required for the UFC
Change-Id: Iade1b64fa3dc890a896fb987fdc8d68db7db5e5f
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
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This unlocks 1866 MHz frequency for AMD boards of f15tn family.
Tested on ASUS A88XM-E with A10-6700 and Crucial BLT8G3D1869DT1TX0.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I547d7e9ca89524d66ee0ee307de41699d991f9fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40490
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit 81066b7ce7192432389578fc0f15b3a46da84bad.
Reason for revert: The hang observed when not exposing the reset GPIOs was root caused to zork sharing the same I2C bus between touchscreen and touchpad and interleaving of messages during probe which resulted in incorrect information returned back by touchscreen firmware. Exposing the reset GPIO changed the timing of probe and hence helped workaround the hang issue. The touchscreen driver is now fixed to perform I2C transactions in a single transfer and so the hang is no longer observed when reset GPIO isn't exposed.
BUG=b:162596241
BRANCH=zork
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ica11c33d542dd2324bb0b8905c5de06047cee301
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This will ensure that the cold reset is performed when CSE Lite jumps
from RO to RW.
BUG=b:162977697
TEST=Verify CSE reset is cold (sits in S5 for PCH Min Slp Duration time)
Change-Id: Ib1173e219ba46ee3275824220c8cf790b1d497fa
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Serial Presence Detect (SPD) data for memory modules is used by Memory
Reference Code (MRC) for training the memory. This SPD data is
typically obtained from part vendors but has to be massaged to format
it correctly as per JEDEC and MRC expectations. There have been
numerous times in the past where the SPD data used is not always
correct.
In order to reduce the manual effort of creating SPDs and generating
DRAM IDs, this change adds tools for generating SPD files for DDR4
memory used in memory down configurations on Intel Tiger Lake (TGL)
based platforms. These tools generate SPDs following JESD79-4C and
Jedec "4.1.2.L-5 R29 v103" specification.
Two tools are provided:
* gen_spd.go: Generates de-duplicated SPD files using a global memory
part list provided by the mainboard in JSON format. Additionally,
generates a SPD manifest file (in CSV format) with information about
what memory part from the global list uses which of the generated
SPD files.
* gen_part_id.go: Allocates DRAM strap IDs for different DDR4
memory parts used by the board. Takes as input list of memory parts
used by the board (with one memory part on each line) and the SPD
manifest file generated by gen_spd.go. Generates Makefile.inc for
integrating the generated SPD files in the coreboot build.
BUG=b:160157545
Change-Id: I263f936b332520753a6791c8d892fc148cb6f103
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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If there's already been an error and PSP_verstage is booting to RO,
don't reset the system. It may be that the error is fatal, but if the
system is stuck, don't intentionally force it into a reboot loop.
BUG=None
TEST=Force an error, still boots to RO instead of going into a boot loop
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ibb6794fefe9d482850ca31b1d3b0d145fcd8bb8f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: I3bae57e6777ab6fc46c771a034f814dd1175be95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Jasper Lake does not have any use case for multiphase SI init so
Disable it.
BUG=b:162184827
BRANCH=None
TEST=Build and boot JSLRVP
Cq-Depend: chrome-internal:3221772
Change-Id: I2d591b46c403e68ff0b41ac8f87c742ae774111e
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
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Add support for FSP 2.2 for jasperlake by selecting
PLATFORM_USES_FSP2_2 config.
BUG=b:162184827
BRANCH=None
TEST=Build and boot JSLRVP
Cq-Depend: chrome-internal:3221772
Change-Id: Ia606ec26da93242ecdd602a9b3badbece5dcd034
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
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The FSP-M/S headers added are generated as per FSP v2295.
Previous FSP version was 2194.
Changes Include:
- Update comments
- UPD offset updates
- add FSPS_ARCH_UPD
BUG=b:162184827
BRANCH=None
TEST=Build and boot JSLRVP
Cq-Depend: chrome-internal:3221772
Change-Id: I569987427cccefc1c5015bdabb10b41f29f2624a
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
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