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2020-03-24drivers/intel/gma/acpi: Use SPDX license identifiersNico Huber
Change-Id: I9012394e553211abe4b225beb9150d997d0c2e38 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-24drivers/intel/gma/acpi: Let the compiler initialize counters[]Nico Huber
TEST=Booted ThinkPad X201s, backlight control still works. Change-Id: I8ff3493be4dc8d640a511358a5324eb73eb35db9 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-24drivers/intel/gma/acpi: Use snprintf() to construct device nameNico Huber
TEST=Booted ThinkPad X201s, backlight control still works. Change-Id: Ieee02f698879ba6b60d863dd63ef9107c0d502b5 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39728 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-24drivers/intel/gma/acpi: Refine some cosmeticsNico Huber
TEST=Booted ThinkPad X201s, backlight control still works. Change-Id: Ie3b00daedc9de05abef0cae9cea99dc7acf1ff62 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39727 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-24drivers/intel/gma/acpi: Reduce display switching stubsNico Huber
_DCS, _DGS and _DSS are required by specification. However, we never implemented them properly, and no OS driver com- plained yet. So we stub them out and keep the traditional behavior in case an OS driver checks for their existence. The old implementations also only returned static values as there never was any write to their GNVS variables. The TRAP() that was called in one place is actually implemented by some ThinkPad's SMI handler as docking event. However, as the call precedes these SMI handlers in coreboot history, it's most likely an accident. Change-Id: Ib0b9fcdd58df254d3b2290900e3bc206a7abd92d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-03-24mb/google/hatch: Give first NIC in Puff idx 1 for vpdEdward O'Callaghan
The format for VPD has changed s.t. the first NIC should always have a zero concat to the end. drivers/net supports this with the workaround of setting the idx to 1. The longer term fix is to adjust all the respective boards to shift back by one and adjust drivers/net friends to remove the 'special casing' of idx == 0. Background: https://chromeos.google.com/partner/dlm/docs/factory/vpd.html#field-ethernet_macn BUG=b:152157720 BRANCH=none TEST=none Change-Id: I510428c555b92398a5199b346dffb85d38495d74 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-23soc/intel/tigerlake: Update DCACHE_BSP_STACK_SIZETim Wawrzynczak
According to the latest Tigerlake Platform FSP Integration Guide, the minimum amount of stack needed for FSP-M is 256KiB. Change DCACHE_BSP_STACK_SIZE to reflect that (plus 1KB previously determined empirically). JSL requires 192KiB. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ic9be6446c4db7f62479deab06ebeba2c7326e681 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-03-23mb/pcengines/apu2/mptable.c: add GNB IOAPIC to MP TableMichał Żygowski
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I385339761b3e1b5dcadb67b8ca29b1518c2db408 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-23nb/amd/pi/00730F01/state_machine.c: unhardcode IOAPIC2 addressMichał Żygowski
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I95964ac6b5939f66c40bd56939bdf532a72d75ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/39701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-23nb/amd/pi/00730F01: initialize GNB IOAPICMichał Żygowski
Northbridge IOAPIC was not being initialized which caused its APIC ID to be set to 0 (the same APIC ID as BSP). TEST=boot Debian Linux on PC Engines apu2 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Id06ad4c22a56eb3559e1d584fd0fcac1f95f13e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-23nb/intel/sandybridge: Use cached CPUIDAngel Pons
Now that we have it, we might as well pass it around. Tested on Asus P8Z77-V LX2, still boots fine. Change-Id: Ia5aa2f932321983f11d2f8869aa624832afe9347 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39721 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-23nb/intel/sandybridge: Void MRC cache if CPUID differsAngel Pons
Native raminit asserts that the DIMMs haven't been replaced before reusing the saved training data. However, it does not check if the CPU is still the same, so it can end up happily reusing data from an Ivy Bridge CPU onto a Sandy Bridge CPU, which runs the raminit_ivy.c code path. This can make the CPU run in unsupported configurations, which may result in an unstable system, or a failure to boot. To prevent that, ensure that the stored CPUID matches the CPUID of the installed CPU. If they differ, print a message and do not use the saved data. As it does not pose a problem for a regular boot, but precludes resuming from S3, use different loglevels depending on the bootpath. Tested on Asus P8Z77-V LX2 with an i7-2600 and an i5-3330, works well. Change-Id: Ib0691f1f849b567579f6afa845c9460e14f8fa27 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-23nb/intel/sandybridge: Store CPUID in ctrl structAngel Pons
Instead of storing an int with a single bit of information taken from the CPUID, we might as well store the actual CPUID. And since we are changing the definition of the saved data, bump the version number. Tested on Asus P8Z77-V LX2, still boots fine. Change-Id: I6ac435fb83900a52890f823e7614055061299e23 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39720 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-23nb/intel/sandybridge: Add warning to saved structsAngel Pons
When changing any of the structures that are cached in non-volatile storage, it is necessary to bump MRC_CACHE_VERSION so that the old information is not misinterpreted. Change-Id: Idefbc38b3a8198b1b5909e775b3c289db689fc0c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39756 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-23nb/intel/sandybridge: Remove unnecessary declarationAngel Pons
Change-Id: If99fd6511fcea474a1398d2b680e0df4bb1a229b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39755 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-23nb/intel/sandybridge: Do not define tables in a headerAngel Pons
Header files are supposed to not make allocations from .bss. Builds fail if said file is included multiple times. To prevent this from happening, move the definitions to a C file. Also, rename raminit_patterns to raminit_tables. This is because more tables that are not patterns will be added here in subsequent changes. Tested on Asus P8Z77-V LX2, still boots fine. Change-Id: If8e3a285ecdc4df9e978ae156be915ced6e1750b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39754 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-23nb/intel/sandybridge: Reflow raminit tablesAngel Pons
Make them fit in 96 characters, so that Jenkins does not complain. With BUILD_TIMELESS=1, the binary of ASUS P8Z77-V LX2 remains identical. Change-Id: I4a763f6050593e9d4db9211bfeedb442724e1ace Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39719 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-23acpi: Change Processor ACPI Name (Intel only)Christian Walter
The ACPI Spec 2.0 states, that Processor declarations should be made within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated and is removed here for Intel CPUs only. Tested on: * X11SSH (Kabylake) * CFL Platform * Asus P8Z77-V LX2 and Windows 10 FWTS does not return FAIL anymore on ACPI tests Tested-by: Angel Pons <th3fanbus@gmail.com> Change-Id: Ib101ed718f90f9056d2ecbc31b13b749ed1fc438 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-23nb/amd/{agesa,pi}/acpi: include thermal zoneMichał Żygowski
According to BKDGs these northbridges should support the K10 compatible temperature sensors. TEST=boot FreeBSD on PC Engines apu2 and check the thermal zone temperature using sysctl Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Icbdf44508085964452d74e084b133f1baa39e1a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-23nb/amd/agesa/family14: Improve HTC threshold handlingMichał Żygowski
According to BKDGs HTC temperature limit field indicates the threshold where HTC becomes active. HTC active state means that processor is limiting its power consumption and maximum P-State. Using this threshold as _CRT is incorrect, since HTC active is designed to prevent overheating, not causing immediate shutdown. Change the behavior of temperature limit to act as a passive cooling threshold. Make the passive cooling threshold a reference value for critical and hot temperature with 5 degrees step. TEST=boot FreeBSD on PC Engines apu2 and check the thermal zone temperature using sysctl Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ife64c3aab76f8e125493ecc8183a6e87fb012e3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/39697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-23nb/intel/sandybridge: Remove oddball `- 1` in tRFCAngel Pons
Fixes a blunder in commit 50db9c99be7e09aafb7cfd353bd0ac9878b76fca (nb/intel/sandybridge: Use DIV_ROUND_UP macro to select timings). Tested on Asus P8Z77-V LX2, still boots fine with an i7-2600. Change-Id: I73436b9f7df9f3a065469fb89bcd0cc6183bb774 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-23mb/gigabyte/ga-h61m-ds2v: Fix PCIe port numbersAngel Pons
A certain somebody (that would be me) forgot how to count, it seems. Change-Id: Iac0ac5827ca242c465a2e8be92a823c8fc9b2935 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39741 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-23mb/gigabyte/ga-h61ma-d3v: Correct PCIe port setupAngel Pons
Coalescing is not needed, as all PCIe ports are used. Change-Id: Icf31f6672e0a54d119a6537da1b52c42f9cee823 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39740 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-23mb/gigabyte/ga-h61m-*/devicetree.cb: Add missing IRQAngel Pons
IRQ 0x70 was not declared for device 2e.7, and coreboot whined about it. Change-Id: If40aa390722cf253169003129b31f20543fde5dd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39739 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-23mb/gigabyte/ga-h61ma-d3v: Correct subsystem IDAngel Pons
Linux does not handle either value in any special way, though. Change-Id: I833cb94e65b9ddfb79edbcdd0216c70740aa4a16 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-23soc/intel/braswell: Clean upAngel Pons
Tested with BUILD_TIMELESS=1, Facebook FBG1701 remains unaffected. Change-Id: I784a5ddc1a8dcbfb960ce970b28b850244a47773 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39663 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-23src/mb/google/volteer: Add camera ACPI configurationDaniel Kang
Add camera ACPI configuration for Ripto/Volteer BUG=None BRANCH=None TEST=Build and boot Ripto or Volteer. Start camera app and able to capture images. Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Change-Id: I2b47ccd989192273a29f09bf097e12e357929334 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-03-23mb/google/volteer: Enable PD_MCU devicePrashant Malani
This is required for PD notifications on the cros_ec driver. BUG=b:150649744 TEST=Boot volteer with this patch and verify that PD notifier events are being generated. Signed-off-by: Prashant Malani <pmalani@chromium.org> Change-Id: I2e72320b025a3dfa7412181586cb142a4503eda5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-23mb/pcengines/apu1/mainboard.c: Add SMBIOS type 16 and 17 entriesMichał Żygowski
Use information provided by AGESA to fill the SMBIOS memory tables. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Id73de7c2b23c6eb71722f1c78dbf0d246f429c63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-23soc/intel/cfl/vr_config: Add 8-core desktop CPU supportPatrick Rudolph
Add 8-core desktop CPU support by adding the corresponding PCI IDs. Tested using "Intel Core(TM) i7-9700E". Change-Id: I7a2e2e5fd1796deff81b032450242fb58031526d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-23mb/tglrvp: Update Audio AIC settings for Tiger LakeSrinidhi N Kaushik
Update Audio AIC UPD settings and gpio pad configs for Tiger Lake. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I45935b79f6fa4ad66238eead9258a4f15feec508 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39466 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-03-23src/mb/intel/tglrvp: Fix board config flag for TGL-UP4 camera ACPIDaniel Kang
Camera ACPI had an incorrect board config flag for TGL-UP4. BUG=None BRANCH=None TEST=Build and boot TGLRVP-UP3 or UP4. Start camera app and able to capture images. Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Change-Id: Ided0e146a9240169d3f1f27a86218ac1a942b899 Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-03-23mb/google/dedede: Update SPD index for waddledeeKarthikeyan Ramasubramanian
Micron memory part uses SPD Index 0. BUG=b:152005386 TEST=Build the mainboard. Change-Id: I990a95b13d636148f0f922fd5c6d4e489d35ed2c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-23src: capitalize 'APIC'Elyes HAOUAS
Change-Id: I487fb53bb2b011d214f002fc200ade2f128a4cc6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-22nb/intel/sandybridge: Drop spurious register writeAngel Pons
It does not make sense to disable an optimization that was not enabled before, especially if that optimization only applies to Ivy Bridge. Tested, still boots and can suspend correctly with: - Asus P8Z77-V LX2 with i5-3330 and Windows 10 - Gigabyte GA-H61MA-D3V with i5-2400 and Arch Linux Change-Id: I9f3eb545585824bbdf51e33f0592e7daa1c425af Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-22device/pci_id: Maintain consistent tab in pci_ids.hSubrata Banik
This patch converts inconsistent white space into tab. Change-Id: Ibc9d614eabbeb819bfff075e66b2277df4c070dc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-21soc/intel/tigerlake: Make PCH_DEV_UART3 macro definition properSubrata Banik
This patch makes PCH_DEV_UART3 macro referring to _PCH_DEV() rather calling _PCH_DEVFN(). Change-Id: I7bc060c3c5f1e0a0fed194704b4940db73f46985 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-21cpu/x86: Fix typoSubrata Banik
CIRTICAL -> CRITICAL Change-Id: Ie2c1427b197dbfebdc7f0c6ffd85f768845ff1bd Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-03-20sb/ibexpeak: Use macros instead of hard-coded IDsFelix Singer
This patch replaces hard-coded PCI IDs with macros from pci_ids.h and adds the related IDs to it. The resulting binary doesn't differ from the one without this patch. Used documents: - Intel 322170 Change-Id: I3326f142d483f5008fb2ac878f30c1a3a72f500f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michael Niewöhner
2020-03-20nb/intel/sandybridge: Deduplicate report_memory_configAngel Pons
Use the version from native raminit, as it takes the reference clock into account. Change-Id: I00e979bec236167d22561e3eb44b30b4a34ad663 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39622 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-20mb/google/dedede Add Audio support for waddledooAamir Bohra
1. Configure Audio GPIOs. 2. Set i2c4 configuration. 3. Update PCH HDA configuration TEST=Verify codecs gets listed with aplay -l command. Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Signed-off-by: Yong Zhi <yong.zhi@intel.com> Change-Id: Ic0516c7a8fee79ce17343a7f42895d6ef534fec9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-03-20drivers/generic/max98357a: Allow custom _HID from configAamir Bohra
Add HID field in max98357a_config and allow mainboards to set it. Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Change-Id: I22d2d078a9a4eb6ab330da8439737ff5133086d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39286 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-20soc/intel: Enable GPIO functions in verstageBora Guvendik
Enable GPIO functionality in verstage so platforms can read a PCH GPIO in verstage to determine recovery mode. BUG=b:151102807 TEST=make build successful Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I4e3b9da307dcf59ab251d8a6a5e09c2a3cfc59fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/39501 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-20ec/google/chromeec: don't put empty block in SSDTMatt DeVillier
Check that there are actually USB-PD ports for which to add data to SSDT, before actually generating SSDT data. This prevents an empty scope from being generated on devices without any USB-PD ports, which was breaking parsing/decompilation on some older platforms (eg, Braswell). Test: build/boot google/edgar, verify SSDT table able to be parsed via iasl after dumping. Change-Id: Ia213e5815e9160e9b36b2501eeccb6385abef47e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39665 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-20nb/intel/sandybridge: Always write to PEGCTLAngel Pons
This register needs to be written to once to lock it down. Do so. Change-Id: I04bd496d064940b51cb9aa1ded6f5b8853ea7334 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39624 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-20mb/**/gma-mainboard.ads: Use SPDX for GPL-2.0-onlyAngel Pons
Change-Id: I005bf205142d4d8c5e12378f33d2100d278fa174 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-03-20mb/**/gma-mainboard.ads: Use SPDX for GPL-2.0-or-laterAngel Pons
Change-Id: I78f06b54a6a03d565cf86f1d7bdf37965c3f6ad0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-03-20mb/**/gma-mainboard.ads: Remove copyright statementsAngel Pons
They are already in AUTHORS. Change-Id: I315c0c57babfa239e3d7c501a4183b8996999e6e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-03-20soc/intel/denverton_ns: Implement AES-NI LockJulien Viard de Galbert
Change-Id: I6cf3484e46eebd3dc753d0903ea8555712b99b7e Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/25440 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Steve Mooney Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-20mb/google/nightfury: Update overridetree.cbSeunghwan Kim
Updating devicetree to enable ELAN touchpad and ELAN touchscreen on nightfury BUG=none BRANCH=firmware-hatch-12672.B TEST=built and verified touchpad and touchscreen worked Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Change-Id: Ieba6558ce3897ce2f95f51ed667465d84b4ab189 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-06 17:29:29 +0000