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2016-01-17google/lars: Enable 20K PU on LPC_LAD 0-3david
At S0, S0ix and S3 LPC LAD signals are floated at 400~500mV. BRANCH=none BUG=chrome-os-partner:48331 TEST=Build and boot on lars Change-Id: I5582007e5caaf444740fa71c9761c27614aafee2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b855fd5834056a3f7d4aef91d634066006990a38 Original-Change-Id: I3a54f9f83f055e433cc1fea38169437ee7f9188f Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/317071 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12965 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-17intel/sandybridge/raminit: fix ODT settingPatrick Rudolph
Count DIMMs on current memory channel instead of all memory channels. The current code is only able to correctly handle the following memory configurations: One DIMM installed in either channel. Four DIMMs installed, two in each channel. Two DIMMs installed, both in the same channel. For systems that have any other configuration the DRAM On-Die-Termination setting is wrong. For example: Two DIMMs installed, one in each channel. Test system: * Gigabyte GA-B75M-D3H (Intel Pentium CPU G2130) Change-Id: I0e8e1a47a2c33a326926c6aac1ec4d8ffaf57bb6 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/12892 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-01-17google/lars: Remove/Disable Wake on landavid
Remove the WakeConfigWolEnableOverride to disable WOL override configuration in the General PM Configuration B (GEN_PMCON_B) register BRANCH=none BUG=none TEST=Build and boot on lars Change-Id: I48d3b706517b6ea6bda44800f61bb11da64503fb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: eab69f2d725df739e5e0e5901a581ad58732cdf9 Original-Change-Id: I42c5a87150638171526ee67f194c1cd9d155203b Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/317080 Original-Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12962 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-16google/lars: add nhlt supportSubrata Banik
Provide an option for including the NHLT blobs within the lars mainboard directory while also adding the ACPI NHLT table generation that the current hardware supports. BUG=chrome-os-partner:44481 BRANCH=None TEST=Built and booted lars board. Audio worked with MAXIM audio card. Change-Id: I1b7836c685ebbe1498f3dbaa2eb64d5e0d4faabb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 401f1a7b23dca19712517ed1588e1390769d1271 Original-Change-Id: I6a937872a9e10d2c5ea15d5952d23e98416df092 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/316092 Original-Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12961 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-16vendorcode/intel/.../skylake: Update FspUpdVpd.h to v1.8.1Martin Roth
This corresponds with the changes that have already gone into the soc/intel/skylake chip.h file and is needed to get skylake platforms building again. Change-Id: I15bfee4eff50d6632659953ec8f97a39d8810db3 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13022 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-16intel/skylake: Fix uninitialized variable warningMartin Roth
I don't think the warning is valid, because we already verify that num_channels is 2 or 4 as soon as we enter the function. Adding the default case makes the compiler happy. Fixes warning: src/soc/intel/skylake/nhlt/dmic.c: In function 'nhlt_soc_add_dmic_array': src/soc/intel/skylake/nhlt/dmic.c:100:2: error: 'formats' may be used uninitialized in this function [-Werror=maybe-uninitialized] return nhlt_endpoint_add_formats(endp, formats, num_formats); ^ Change-Id: Idc22c8478ff666af8915d780d7553909c3163690 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13021 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-16mainboard: Drop abuild.disabled files for Skylake boardsStefan Reinauer
Make sure the latest & greatest Intel targets actually build in our build system. intel/sklrvp is still failing for reasons unrelated to the rest of the skylake boards. Leaving that disabled for now. Change-Id: Ie784628a57257cea30e5e47074648198b884f6db Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12857 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2016-01-16intel/kunimitsu: remove/disable Wake on lanRizwan Qureshi
remove the WakeConfigWolEnableOverride to disable WOL override configuration in the General PM Configuration B (GEN_PMCON_B) register BRANCH=none BUG=none TEST=Build and booted in kunimitsu Change-Id: Ia523e7956c06c9f4a60e0a2296f771cc3c70bc25 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 12a07eebfb8fa4ee8013fbbb12283a0b429cacfd Original-Change-Id: I2be6c5b0114e4c7d8a7b9ceb59ee32f28f61769f Original-Reviewed-on: https://chromium-review.googlesource.com/316717 Original-Commit-Ready: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Tested-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12958 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-16google/lars: Add new configuration parametersdavid
Follow kunimitsu setting of https://chromium-review.googlesource.com/#/c/313309/ BRANCH=none BUG=none TEST=Build and boot on lars. Change-Id: I77a4454b3702dc58dc70a7b981b25a656e97f534 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9c390322b4c770a0206549257dd34d1ef1242cc3 Original-Change-Id: I612e799433a396a6cce5742adb6de72a305b5df1 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/316270 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/12954 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-16google/lars: Disable SD 3.0 Controller [D30:F6]Subrata Banik
LARs design don't have SD Connector over native SD Controller. BUG=chrome-os-partner:48190 BRANCH=None TEST=Build & boot LARs. Use "lspci" doesn't list 0x1E:06 device in list. CQ-DEPEND=CL:315420 Change-Id: Idff7243a6aaf4b8d5f49e4bf215a77131f716485 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ca769138b97b404598c4a6bfa6c2ff5c1c3ec896 Original-Change-Id: I71416ac89a8c91ab272d6737d1b46c8045567e17 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/315423 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12947 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-16intel/skylake: Add kconfig option to skip Native SD ControllerSubrata Banik
Skylake Core boot should have configurable option to skip PCH based SD 3.0 Controller from customer/reference design. Addition to that no unused or unnecessary should list under device view. BUG=chrome-os-partner:48190 BRANCH=None TEST=Build & boot Kunimitsu and LARs. Change-Id: Ie17fd6db01e0cabcdf605017509d809b54509a0d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 99ac17b723125822368539d0562aa35119e520fb Original-Change-Id: I98a48f45ef442246227fd54ea021b53f824954c5 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/315420 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12946 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-16intel/kunimitsu: Add VrConfig UPD parametersRizwan Qureshi
Cofigure VR settings for kunimitsu BRANCH=none BUG=chrome-os-partner:45387 TEST=Build and booted in kunimitsu CQ-DEPEND=CL:311317 Change-Id: Ib2afe7694d2a807cea1befa73349bd21a3e7d909 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c3548d7cb3a00826377e819f20d07167b4eb2c65 Original-Change-Id: I6b80f509bc0ab6f65f26eec0651a3b44fb38fbf9 Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313068 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12945 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-16intel/skylake: Add VrConfig UPD parameters from corebootRizwan Qureshi
Adding VrConfig UPDs and assign values to those from devicetree BRANCH=none BUG=chrome-os-partner:45387 TEST=Build and booted in kunimitsu CQ-DEPEND=CL:310192 Change-Id: Ifce9dfacabc742b55266c48459c56c69b1f22236 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b34a3cc77afc8795abb64972f8169986c30c2acd Original-Change-Id: Ifa960e718ed77db729f1fc4e2c00c9b305093e04 Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311317 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12944 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-01-16intel/skylake: Enable SkipMpInit tokenRizwan Qureshi
This patch helps to enable SkipMpInit token of FSP SiliconInit UPD BRANCH=none BUG=chrome-os-partner:44805 TEST=Build and booted in kunimitsu with SkipMpInit enabled from CB. CQ-DEPEND=CL:310869 Change-Id: I43377e4b8adadf42091a9387883363fdfbab4c1b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b7962273fd1a591cfe9a658f49ebc7d23bcad577 Original-Change-Id: I977d2d39c283d74f1aa9033c8aa60dc652735019 Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/310192 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12943 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15intel/skylake: Init variable so GCC knows it's setMartin Roth
Even though the data32 variable was getting written by pch_pcr_read(), GCC still flagged it as being used while uninitialized and failed the build. Note that pch_pcr_read() may only set 1 or 2 bytes of data32 in the successful path, depending on the size of the read. Change-Id: Icd6e80d06b9bf4af506d62d55ffe4c5e98634b2b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12860 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Ben Gardner <gardner.ben@gmail.com>
2016-01-15sb/intel/i82801gx: Fix sata AHCI for desktop NM10/ICH7Damien Zammit
Tested on Intel D510MO Before this patch, I was unable to get the SATA controller into AHCI mode. That is, I could never see PCI ID 8086:27c1 appearing on the bus. With sata_ahci set, controller now goes into AHCI mode and works. 8086:27c1 Tested on X60 with AHCI enabled 8086:27c5 (AHCI mode for mobile ich7) No regressions detected. Change-Id: I4a3eabb5773106a0825fa2f30ee400fbfe636c7f Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/12923 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-01-15intel/kunimitsu: Add new configuration parametersRizwan Qureshi
Add new configuration parameters eg. #SLP_S3 assert width BRANCH=none BUG=chrome-os-partner:44075 TEST=Build and booted on kunimitsu, verified that CB is doing the Lockdowns which were previously done by FSP. CQ-DEPEND=CL:310869 Change-Id: I782df49bbf73c121b191f0661907173c4fd29b64 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: de0742869b1b148597d3714a3bc29a0dc08642aa Original-Change-Id: I2b4041cdc22a29e79d2ff7f2cc49f51f80da5567 Original-Reviewed-on: https://chromium-review.googlesource.com/313309 Original-Commit-Ready: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Tested-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12942 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15intel/skylake: More UPD params are added for PCH policy in FSPRizwan Qureshi
Some more PCH Policy UPD Parameters are added in FSP. Lockdown config moved from FSP to coreboot. Removing settings in devicetree.cb which are zero. BRANCH=none BUG=none TEST=Build and booted on kunimitsu, verified that CB is doing the Lockdowns which were previously done by FSP. CQ-DEPEND=CL:*237842, CL:310191 Change-Id: I3dcf3a5340f3c5ef2fece2de5390cde48db4d327 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e8bdb35897b640d271adcaed266030367f060553 Original-Change-Id: Ia201672565c07b2e03d972b2718512cd4fcbb95c Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Signed-off-by: Naresh G Solanki <Naresh.Solanki@intel.com> Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/310869 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12941 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-01-15intel/skylake: Update UPD parameters as per FSP 1.8.0Barnali Sarkar
Some MemoryInit UPD parameters have been moved to SiliconInit in FSP 1.8.0. This patch has the respective changes in coreboot for this. BRANCH=none BUG=none TEST=Build and booted in kunimitsu CQ-DEPEND=CL:*237423, CL:*237424 Change-Id: Ic008d22f96fb5f14965e5b5db15e05fb39dd52d3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 573c1d8325cd504213528030ecf99559402b5118 Original-Change-Id: I71b893aa7788519ed2ef15f3247945ffcbbbcf4d Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/310191 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12940 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15intel/kunimitsu: Enable 20K PU on LPC_LAD 0-3pchandri
At S0, S0ix and S3 LPC LAD signals are are floated at 400~500mV. BRANCH=chrome-os-partner:48331 BUG=None TEST=Build and Boot kunimitsu Change-Id: I2e2654ac89f8e0c8d6ab1af31d0bd5a0d4c43db8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6f4b902e220dcde73df56970208c45fe3148b70e Original-Change-Id: I597d4816d09d0cfd9b0ec183a9273551aed8688a Original-Signed-off-by: pchandri <preetham.chandrian@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/316529 Original-Commit-Ready: Preetham Chandrian <preetham.chandrian@intel.com> Original-Tested-by: Preetham Chandrian <preetham.chandrian@intel.com> Original-Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Preetham Chandrian <preetham.chandrian@intel.com> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-on: https://review.coreboot.org/12957 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15intel/skylake: Add GPIO ACPI Apis.Subrata Banik
GPIO ASL APIs to get GPIO Value. Need such APIs to read GPIO config settings. Example: Kunimitsu need to read AUDIO_DB GPIO to identify codec select. BUG=chrome-os-partner:44481 BRANCH=none TEST=build and boot on Kunimitsu. Change-Id: If56bb7b3eae08e1949d372850a6426dfde5aadd0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4983ba835a8da2baf578b035ae482755983c1ecb Original-Change-Id: Ia40d86c8d4b14857fa8822677b3f7d393a35b677 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/316352 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12956 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15google/lars: Set DPTF critical temperature to 99Cdavid
DPTF may power off the system when it starts if the CPU temp is >90C. Since TJmax is 100C set the critical threshold to just below that value. BRANCH=none BUG=none TEST=Build and boot on lars. Change-Id: I3abf946ae09c3c691480e468d0c1d74730dc6c06 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7c2230009edb840e88a20c2d8a87f942c09b6bf3 Original-Change-Id: Iee1a3596dbbe934f68637f012c02c078c3751eeb Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/316102 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/12955 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15google/lars: Disable kepler devicedavid
Disable kepler device, it is removed and was not used on proto anyway. BUG=none BRANCH=none TEST=build and boot on lars proto Change-Id: I137b82b8dca23f5b40adcc6a056e77a4ff54d4d5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 44d63453a9b31331d13d05f8f86d4218af0f0aa1 Original-Change-Id: Ib0892bf93b1d0cda1c0143d2b16cd58aeda83131 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/315950 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/12950 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15google/lars: Add support for MAX98357A audio amplifierSubrata Banik
Adding support for Maxim 98357A audio amplifier. Removed SSM4567 support from LARs. BUG=chrome-os-partner:44481 BRANCH=None TEST=Build & boot on LARs. Verify audio playback works using MAXIM amplifiers. Change-Id: I2cd8b20e936319b434017b6dd73d4739684d21d3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 76cbc20826c884194a144f6b6bc644900e5d475d Original-Change-Id: I1156096b6aa367c0b8d8e3952d92f0eb5cf2820f Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/314543 Original-Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12960 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15intel/kunimitsu: Correct the output for crossystem wpsw_bootArindam Roy
The write protect GPIO is not being configured early enough. This is leading to coreboot reading incorrect value, and writing the incorrect value in vboot shared file. This is leading to "crossystem wpsw_boot" always returning 0 even with the write protect screw in place during boot. BUG=chrome-os-partner:48292 BRANCH=None TEST=Boot with the write protect screw in place. Issue crossystem wpsw_boot. It should show 1. Change-Id: I3a333a4dcce31be9afe28cf11b127090cc7b9421 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 462dd0229c2d3b81cd34bdd2e36bea844f58586c Original-Change-Id: Ib7e0539845575b32322e243e89b81ffee077eb81 Original-Signed-off-by: Arindam Roy <arindam.roy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/316009 Original-Commit-Ready: Arindam Roy <rarindam@gmail.com> Original-Tested-by: Arindam Roy <rarindam@gmail.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12952 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15google/lars: Update the PL1 value as TDPdavid
Currently, the Power Limit 1 (PL1) value is 6W which is low for high performance KPIs. This patch updates PL1 value as TDP. SKL-U has 15W TDP. BRANCH=none BUG=none TEST=Build and booted on lars. Change-Id: Ic1313385e0aa1760b473a34c853a95c76257eecf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a47faee53e08da81602b485937621fd49eb2ddbf Original-Change-Id: I7c91dcdc82525a6d2b706f8f504ba48601097ef7 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/316370 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/12953 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15google/chell: Fix the P/N number for samsung K4E6E304EE-EGCFWisley
modify the P/N in samsung K4E6E304EE-EGCF SPD from K4E6E304ED-EGCE to K4E6E304EE-EGCF BRANCH=none BUG=chrome-os-partner:48299 TEST=build chell and use gooftool to probe and P/N match Change-Id: Ie560e5c0d4b9a3cfb34c3856911930fb8159764e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: dabe5eaa8abf54f4e4a5492062adca6ef9b4634d Original-Change-Id: Ie8d44ac6032e5213928bfae2a2ac5877d4193d62 Original-Signed-off-by: Wisley <wisley.chen@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/316100 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/12951 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15intel/kunimitsu: Add support for MAX98357A audio amplifierRohit Ainapure
Adding support for Maxim 98357A audio amplifier. BUG=chrome-os-partner:44481 BRANCH=None TEST=Build & boot on Skylake kunimitsu Fab4 with MAXIM codec. Verify audio playback works using MAXIM. Change-Id: I4f020ccae540b02d5d533704a52cebb7805715fe Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c0a81300e02e917500fa3c0241c95dd795abaf04 Original-Change-Id: I8875c9a55f09b1ec353203cfcb2186dc5fd66542 Original-Signed-off-by: Rohit Ainapure <rohit.m.ainapure@intel.com> Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/309894 Original-Tested-by: Rohit M Ainapure <rohit.m.ainapure@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12949 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15google/chell: add nhlt supportAaron Durbin
Provide an option for including the NHLT blobs within the glados mainboard directory while also adding the ACPI NHLT table generation that the current hardware supports. BUG=chrome-os-partner:44481 BRANCH=None TEST=Built and booted. Headphones, speakers, and mic on camera emits and creates sound albeit not the greatest. Change-Id: Iaf910041453695b7125b254ca5d71e8ccbd0b02f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ea77d326ba1c33b100c34066ed361a55dfa14ce3 Original-Change-Id: I5d93c3a7fa4cf68ba91f1398b4bd04504a28fef2 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/315520 Original-Tested-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/12948 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15google/glados: add nhlt supportAaron Durbin
Provide an option for including the NHLT blobs within the glados mainboard directory while also adding the ACPI NHLT table generation that the current hardware supports. BUG=chrome-os-partner:44481 BRANCH=None TEST=Built and booted. Headphones, speakers, and mic on camera emits and creates sound albeit not the greatest. Change-Id: I6e36c0a99a73cdcb2bf6ccfbfc886a594f989a39 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5b0383a93f054011dd7c18519ece4e6f1944366d Original-Change-Id: I6f8bd15c72fa89756382af99bddb6cb6abe89905 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/313794 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/12939 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15intel/skylake: add nhlt supportAaron Durbin
The use of a NHLT table is required to make audio work on the skylake SoCs employing the internal DSP. The table describes the audo endpoints (render vs capture) along with their supported formats. These formats are not only dependent on the audio peripheral but also hardware interfaces. As such each format has an associated blob of DSP settings to make the peripheral work. Lastly, each of these settings are provided by Intel and need to be generated for each device's hardware connection plus mode/format it supports. This patch does not include the dsp setting blobs. The current supported connections: - digital mic array 2 channel - digital mic array 4 channel - Maxim 98357 amplifier - ADI ssm4567 - NAU88L25 headset codec BUG=chrome-os-partner:44481 BRANCH=None TEST=Built glados. Speakers, headphones, and mic on camera decently worked. CQ-DEPEND=CL:*239598 Change-Id: If1a9be97573b9b160893944661790cac7df26fca Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1f5514e27811c500732de97e1cc7edeced2607e7 Original-Change-Id: Ib42e895f00e7605cb30ce24d9b8dd00bf68a7477 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/313998 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/12938 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15lib: NHLT ACPI table supportAaron Durbin
Intel's SST (Smart Sound Technology) employs audio support which may not consist of HDA. In order to define the topology of the audio devices (mics, amps, codecs) connected to the platform a NHLT specification was created to pass this information from the firmware to the OS/userland. BUG=chrome-os-partner:44481 BRANCH=None TEST=Tested on glados. Audio does get emitted and some mic recording works. Change-Id: I8a9c2f4f76a0d129be44070f09d938c28a73fd27 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2472af5793dcffd2607a7b95521ddd25b4be0e8c Original-Change-Id: If469f99ed1a958364101078263afb27761236421 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/312264 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/12935 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15intel/kunimitsu: Update the PL1 value as TDPSumeet Pawnikar
Currently, the Power Limit 1 (PL1) value is 6W which is low for high performance KPIs. This patch updates PL1 value as TDP. SKL-U has 15W TDP. BRANCH=None BUG=None TEST=Built and boot on kunimitsu. Check for the PL1 value over sysfs interface "/sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw". Load the system with Aquarium 1000 Fish, average FPS should be meeting target 60 with this change. Change-Id: I8e083192e8018edc2cf8b88530df1e05ede10bde Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: eb9aa00a4271875b5471c33883aa7da022f1cb0e Original-Change-Id: I0c61fe1a9f76a9cf9a306240fb66d4c081d2bb5e Original-Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/314416 Original-Commit-Ready: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Original-Tested-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/12934 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15google/lars: Disable eMMC HS400 capabilitydavid
BUG=chrome-os-partner:48017 BRANCH=none TEST=Verify eMMC is working fine. Change-Id: If02d969029a9eb8d05148ee958fd34225c8a88fe Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: dca385c2bbf11c9eb79fd0761b2b335f8fdff491 Original-Change-Id: I371036426f17530409b46af285b18f4522739ee7 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313912 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/12618 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-14arch/x86: add missing license headersMartin Roth
These were mostly written as part of the coreboot project, so get the standard coreboot license header. memmove.c came from the linux kernel, so also gets the standard coreboot v2 license header, but gets the added attribution that it was derived from the linux kernel. Unlike many coreboot files, this file may not be re-licensed as GPL V3. Change-Id: I1fdc26b543e059f7a42d4b886f7222f4c74b959d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12916 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-14soc/braswell: Add CPUID for D0 steppingDivya Sasidharan
Original-Reviewed-on: https://chromium-review.googlesource.com/309122 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Change-Id: Ia24dbeb6b23ccbbb380843a4684def578cde168a Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://review.coreboot.org/12727 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-14ec/: add missing license headersMartin Roth
thermal.asl was written as part of the coreboot project, so gets the standard coreboot license header. ec_commands.h came from the chrome ec tree, so gets the BSD license from that tree as mentioned in the header that has been replaced. Change-Id: I514138fd4ed236105998b25d1d2d8eb8441cf91d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12918 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-14acpi/: add missing license headerMartin Roth
These were mostly written as part of the coreboot project, so get the standard coreboot license header. Change-Id: Ief13339647d3172e65bb18e6dcb54312a5c9472e Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12917 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-14arch/x86/include: add missing license headersMartin Roth
These were all written as part of the coreboot project, so get the standard coreboot license header. Change-Id: I51e1e504b3bc7be2a00c9356d8775b87f2a1db5a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12912 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-14soc/braswell: Fix P-state tableSubrata Banik
Incorrect bus-core-ratio been used to generate P-state table Original-Reviewed-on: https://chromium-review.googlesource.com/290681 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I4a34ec80ff3f2ed46dc074c9f8fe06756db8b357 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/12731 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-14intel/skylake/pcr.c: error out on invalid size in pcr read/writeMartin Roth
The read and write routines take a number of bytes to write, which should be 1,2, or 4. We now return an error if an invalid size is specified. Change-Id: I93344bc0837c3715fc7660503f405c8878eb711c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12936 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-01-14mb/lenovo/x200: Add panel power sequence valuesNico Huber
Values are taken from the vendor BIOS of my X200s. Notable effect: Stops display from flashing during native graphics init / Linux mode setting. Change-Id: Ie5d9efc010a78dd46317b6bbdb7bfacc2c9d2cbf Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/12886 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-14nb/intel/gm45: Backport configuration of panel power timingsNico Huber
Register settings are the same as on newer chips (compare sandy- bridge), just at different locations. Change-Id: Iea0359165074298a376e0e2ca8f37f71b83ac335 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/12885 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-14nb/intel/gm45: Drop unnecessary panel power handlingNico Huber
Skip everything but the final setting of PP_CONTROL, i.e. triggering the power up. The settings with PANEL_UNLOCK_REGS are useless as no lockable registers were touched in between. Also the loop waiting for the panel power up to finish was a no-op as the registers with the power timings were never filled (see follow-up commits). Change-Id: Ife27dcafdf197b2246c4e69f2bf7a3a6765d1d82 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/12884 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-14mainboard/lenovo: reserve century byteAlexander Couzens
The century byte is used by most RTC (default 0x32@nvram). Even the century byte can disabled via ACPI it's more safe to reserve it's space. Because some RTC will act with that byte anyhow. Some OS overwrite it when syncronize the RTC. Change-Id: I078c0c57215ccb925afa85b9d067f15268801ec9 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/11853 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-01-13arch/arm64: add missing license headersMartin Roth
These were all written as part of the coreboot project, so get the standard coreboot license header. Change-Id: I4fccc8055755816be64e9e1a185f1e6fcb2b89ae Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12911 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-13arch/arm: add missing license headersMartin Roth
These were all written as part of the coreboot project, so get the standard coreboot license header. Change-Id: I74438e8032c84f4190ef49f306969f7157234001 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12910 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-13tree: drop last paragraph of GPL copyright header from new filesMartin Roth
This continues what was done in commit a73b93157f2 (tree: drop last paragraph of GPL copyright header) Change-Id: Ifb8d2d13f7787657445817bdde8dc15df375e173 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12914 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-13intel/skylake platforms: Add MAINBOARD_HAS_LPC_TPM in KconfigMartin Roth
Because these platforms haven't been getting build testing, they've missed out on some of the improvements that the other platforms have gotten. Enable MAINBOARD_HAS_LPC_TPM so that they will build. Change-Id: I5e44135b6dfa800fa14e5b08c3e3e5921d50b082 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12865 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-13intel/northbridge/sandy: raminit code cleanupPatrick Rudolph
Remove redundant call to dram_mrscommands(). Change-Id: I157915b4432093c556b538433e3337db1e9c525f Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/12891 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-09 04:38:01 +0000