summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Expand)Author
2016-05-01nb/amd/mct_ddr3: Fix x4 DIMM receiver enable training on Fam15hTimothy Pearson
2016-04-30lib/reg_script: Allow multiple independent handlersLee Leahy
2016-04-30lib/regscript: Add exclusive-or (xor) supportLee Leahy
2016-04-30soc/apollolake: Prevent PMC BAR reassignment during resource allocationHannah Williams
2016-04-29soc/intel/apollolake: clarify Fast SPI CS2 pad configurationAaron Durbin
2016-04-29nb/intel/sandybridge/raminit: fix regression "always use mrccache"Patrick Rudolph
2016-04-29siemens/mc_bdx1: Add new mainboard.Werner Zeh
2016-04-28nb/amd/mct_ddr3: Restart system on training failure instead of using die()Timothy Pearson
2016-04-28Add board URLs for the RISC-V boardsJonathan Neuschäfer
2016-04-28Fix "Spike RISCV" board nameJonathan Neuschäfer
2016-04-28fsp_baytrail: Fix missing "$" when using Kconfig switchWerner Zeh
2016-04-28drivers/intel/i210: Use uint8_t and friends instead of u8Werner Zeh
2016-04-28mc_tcu3: Switch to hwilib instead of own hwinfo implementationWerner Zeh
2016-04-28vendorcode/siemens: Add hwilib for Siemens specific info structWerner Zeh
2016-04-28soc/intel/apollolake: Add handling of GNVS ACPI entry for CHROMEOS buildsLance Zhao
2016-04-28soc/intel/apollolake: Add GPIO devicesZhao, Lijian
2016-04-28soc/intel/apollolake: Add cache for BIOS ROMAndrey Petrov
2016-04-28soc/intel/apollolake: Enable LPC bus interfaceAndrey Petrov
2016-04-28soc/intel/apollolake: Enable RAM cache for cbmem region in ramstageAndrey Petrov
2016-04-28soc/intel/apollolake: Fix northbridge _crs scopeZhao, Lijian
2016-04-28mainboard/amenia: Enable Chrome EC Interface/KeyboardDivya Sasidharan
2016-04-28soc/intel/apollolake: Configure a GPIO for TPM in bootblockAndrey Petrov
2016-04-28soc/intel/apollolake: Avoid marking 0xe0000-0xfffff region usableAndrey Petrov
2016-04-28soc/intel/apollolake: Actually include ACPI PCI IRQ definitionsAndrey Petrov
2016-04-26mainboard/kgpe-d16|kcma-d8: Update memory test to include second PRNG stageTimothy Pearson
2016-04-26nb/amd/mct_ddr3: Report correct DIMM in MRS setup routinesTimothy Pearson
2016-04-26nb/amd/mct_ddr3: Fix a number of minor errors in RDIMM setupTimothy Pearson
2016-04-25ensure correct byte ordering for cbfs segment listGeorge Trudeau
2016-04-25nb/amd/mct_ddr3: Scale lane delays for each DIMM after MEMCLK changeTimothy Pearson
2016-04-22drivers/ricoh: Fully switch to src/drivers/[X]/[Y]/ schemeStefan Reinauer
2016-04-22soc/intel/quark: Fix MTRR readsLee Leahy
2016-04-22soc/intel/quark: Fix uninitialized variable d_variantLee Leahy
2016-04-22Revert "nb/amd/mct_ddr3: Disable MCE framework during DRAM training"Timothy Pearson
2016-04-22nb/amd/mct_ddr3: Enhance debugging around MEMCLK frequency changeTimothy Pearson
2016-04-22nb/amd/mct_ddr3: Fix RDIMM training on certain DIMMsTimothy Pearson
2016-04-22nb/amd/mct_ddr3: Run fence training on each node after memory clock changeTimothy Pearson
2016-04-22soc/intel/apollolake: Flush L1D to L2 only if loaded segment is in CARFurquan Shaikh
2016-04-22intel/i82801ax: Fix IDE setup console logPatrick Georgi
2016-04-21lib: add common write_tables() implementationAaron Durbin
2016-04-21lib/coreboot_table: add architecture hooks for adding tablesAaron Durbin
2016-04-21lib/bootmem: allow architecture specific bootmem rangesAaron Durbin
2016-04-21lib: add helper for constructing coreboot forwarding tableAaron Durbin
2016-04-21arch/x86: remove low coreboot table supportAaron Durbin
2016-04-21arch/x86: clean up write_tables()Aaron Durbin
2016-04-21arch: only print cbmem entries in one placeAaron Durbin
2016-04-21arch: use Kconfig variable for coreboot table sizeAaron Durbin
2016-04-21arch/riscv/tables: remove confusion over write_tables()Aaron Durbin
2016-04-21arch/power8/tables: remove confusion over write_tables()Aaron Durbin
2016-04-21soc/intel/apollolake: Set default memory type to uncacheableFurquan Shaikh
2016-04-21AGESA vendorcode: Fix type mismatchKyösti Mälkki
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-15 06:56:09 +0000