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2020-05-29AGESA boards: Fix typo in *OVERRIDES* in commentPaul Menzel
Run the command below to fix all occurrences. git grep -l OVERIDES | xargs sed -i 's/OVERIDES/OVERRIDES/g' Change-Id: I5ca237500a0ecff59203480ecc3c992991f08130 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2020-05-29Puff: Disable EFS1 for variantsDaisuke Nojiri
VBOOT_EC_EFS is for EFS1 and EFS1 is deprecated. Puff uses EFS2 and its variants should follow. BUG=b:157372086 BRANCH=none TEST=emerge-puff coreboot Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I581f137b506a96df45e5bed21833856bb4f6aaa3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-05-28ec/google/chromeec: Switch to use new acpigen_usb moduleTim Wawrzynczak
Implementation of the ACPI objects for the Type-C Connector Class was added in the previous patch. This patch removes the functionality from the ChromeEC's SSDT generator, and uses acpigen_usb instead. TEST=Verified contents of SSDT are the same. Change-Id: Icdbcee1f989ee3146f7495e08fc13f9386791858 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-05-28acpi: Add new file for implementing Type-C Connector classTim Wawrzynczak
The USB Type-C Connector Class in the Linux kernel is not specific to the ChromeOS EC, so this functionality is now split out into a separate file, acpigen_usb.c. Documentation about the kernel side is available at https://www.kernel.org/doc/html/latest/driver-api/usb/typec.html. Change-Id: Ife5b8b517b261e7c0068c862ea65039c20382c5a Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41539 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28ec/google/chromeec: Add new *-switch properties to USBC.CONx devicesTim Wawrzynczak
The Linux ChromeOS EC driver now looks for 3 new properties under each USBC.CONx device contained within the ChromeOS EC device. These properties are just a reference to the device that controls the switches for USB 2/3 muxing, SBU lines, and CC lines. It uses the new function, soc_get_pmc_mux_device() to retrieve the device. Change-Id: I03cd83f9b2901b5583053fac8ab6eab64717a07d Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40618 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28soc/intel/tigerlake: Implement soc_get_pmc_mux_device()Tim Wawrzynczak
The ChromeOS EC is adding new entries to its USBC.CONx devices (see later patch), and it needs to get access to the PMC.MUX device so that its ACPI path can be retrieved. This provides a weak function to return NULL for all Intel SoCs except for Tiger Lake, which locates the device if it is found in the devicetree. Change-Id: I3fe3ef25e9fac8748142f5b1bd870c9bc70b97ff Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40948 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28mb/google/volteer: Add PMC.MUX.CONx devices to devicetree for VolteerTim Wawrzynczak
Volteer's MUX connections are known, and can now be described in ACPI tables. Port 1 has the only oddity, with SBU lines staying fixed in the CC1 orientation. TEST=Dump SSDT tables on Volteer, and confirm (coalesced for brevity): Scope (\_SB.PCI0.PMC) { Device (MUX) { Name (_HID, "INTC105C") Device (CON0) { Name (_ADR, 0) Name (_DSD, Package() { Package () { "usb2-port-number", 9 }, Package () { "usb3-port-number", 1 }, }) } Device (CON1) { Name (_ADR, 1) Name (_DSD, Package() { Package () { "usb2-port-number", 4 }, Package () { "usb3-port-number", 2 }, Package () { "sbu-orientation", "normal" }, ... } } } Change-Id: Id361b2df07e87ad72b6a59a686977b3f424e8ecf Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-05-28soc/amd/picasso/soc_util: add comment on socket detection problemsFelix Held
At least some Pollock engineering samples return FP5 socket type while they are in fact FT5 socket type. Change-Id: I06a19c19374532bfb367fc15c734707d8c7f65a3 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41796 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28soc/amd/picasso/soc_util: remove unused functionsFelix Held
soc_is_pollock() and soc_is_picasso() aren't used by any mainboard or soc code. The same fuctionality is still provided by get_soc_type(). Change-Id: I046b4925bfeb4b31d11e2548ac87b7bbca0f6475 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41795 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28drivers/intel/fsp2_0: add option to compress FSP-M in cbfsAaron Durbin
Allow the ability for chipset or mainboard to choose to compress FSP-M in cbfs using LZMA or LZ4 routines. However, only non-XIP platforms will support FSP-M compression. Since the main cbfs decompression paths are utilized add the appropriate checks for including compression algorithms under the FSP-M compression options. On picasso FSP-M (debug builds) the following savings were measured: no-compression: fspm.bin 720896 none FSP_COMPRESS_FSP_M_LZ4: fspm.bin 138379 LZ4 (720896 decompressed) -80% FSP_COMPRESS_FSP_M_LZMA: fspm.bin 98921 LZMA (720896 decompressed) -86% BUG=b:155322763,b:150746858,b:152909132 Change-Id: I5c88510c134b56a36ff1cd97a64b51ab2fea0ab0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-28soc/intel/tigerlake: Generate PMC ACPI device at runtimeTim Wawrzynczak
In an attempt to help reduce the amount of static ASL files that are littered throughout the codebase, pmc.asl was converted to runtime SSDT generation instead. If future SoCs reuse the same PMC, then this function can be moved to soc/intel/common/block/pmc for example. TEST=Verified the following was in the decompiled SSDT: Scope (\_SB.PCI0) { Device (PMC) { Name (_HID, "INTC1026") // _HID: Hardware ID Name (_DDN, "Intel(R) Tiger Lake IPC Controller") Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xFE000000, // Address Base 0x00010000, // Address Length ) }) } } Also the following found in linux's /var/log/messages: "acpi INTC1026:00: GPIO: looking up 0 in _CRS", indicating the PMC ACPI device was found and its _CRS was locatable. Change-Id: I665c873d8a80bd503acc4a9f0241c7a6ea425e16 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/41408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-05-28mb/google/dragonegg: remove abandoned projectAaron Durbin
Dragonegg is no longer in development nor used. Remove it. Change-Id: Ida30dba662bc517671824f8b70b73b4856836e97 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41783 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28drivers/intel/fsp2_0: add option to compress FSP-S in cbfsAaron Durbin
Allow the ability for chipset or mainboard to choose to compress FSP-S in cbfs using LZMA or LZ4 routines. To accomplish this fsp_load_component() is added as an assist for performing the necessary logic and allow the caller to provide the destination selection. Since the main cbfs decompression paths are utilized add the appropriate checks for including compression algorithms under the FSP-S compression options. On picasso FSP-S (debug builds) the following savings were measured: no-compression: fsps.bin 327680 none FSP_COMPRESS_FSP_S_LZ4: fsps.bin 98339 LZ4 (327680 decompressed) -70% FSP_COMPRESS_FSP_S_LZMA: fsps.bin 71275 LZMA (327680 decompressed) -78% BUG=b:155322763,b:150746858,b:152909132 Change-Id: I8aa5d8c1cbaf4d08f38a918a9031a2570bc5247e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-28lib/cbfs: add cbfs_stage_load_and_decompress helperAaron Durbin
The LZ4 compressed stages assume in-place decompression. The constraints are validated in cbfstool for _stages_ such that they can be decompressed in place. However, that is only true for stages. As such, add a wrapper, cbfs_stage_load_and_decompress(), that handles the LZ4 stage loading case. BUG=b:155322763,b:150746858,b:152909132 Change-Id: I9525a266250aa6c775283b598c09d4f40692db55 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41755 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28include/uuid.h: Add missing includeRaul E Rangel
uuid.h uses uint8_t which is provided by stdint.h. BUG=b:153675915 TEST=Fixed my compiler error. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Idbec40f444d9df7587b9066faac65499415dae6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/41803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-28mb/google/zork/berknip: Replace full GPL header with SPDX linePatrick Georgi
Change-Id: I858f870db0babcb51c594570e8136436ecbb0d1d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41823 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28lib: Add strtok() and strtok_r()harshit
Add strtok() and strtok_r() to the library. Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com> Change-Id: Ic855b31669be1c274cbf247c53ffa6f74ec5bf35 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-05-28arch/x86: Fix id section in linker scriptKyösti Mälkki
Builds where RESET_X86_VECTOR is adjusted would create unintentionally large bootblock files since id section can move far away from .reset and .text. Some builds segfault or may try to create close to 4 GB large intermediate build objects. For cases where build is successful, id section would not reside within REGION(program) or REGION(bootblock). A proper fix to always place the ID data at the end of the coreboot.rom file is left as follow-up work. For now, just place id section below .reset. Change-Id: Idf0e4defcde6d5e264d4752cc93f4ffb6749d287 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-05-28arch/x86: Remove more romcc leftoversKyösti Mälkki
The sections .rom.* were for romcc and no longer used. Some romcc comments were left behind when guards were removed. Change-Id: I060ad7af2f03c67946f9796e625c072b887280c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-05-28soc/intel/jasperlake: Disable PAVP UPDRonak Kanabar
This patch will disable PAVP UPD, which is by default enabled in FSP. BUG=b:155595624 BRANCH=None TEST=Build, boot JSLRVP, Verified UPD values from FSP log Change-Id: I8e103ad11ae6ffa6b9efe4bf249bbe344bc10a30 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41763 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28soc/intel/jasperlake: Correct GPIO community PID configurationAamir Bohra
Current implementation returns the incorrect GPIO community PID. The GPIO community index 3 should return PID for COMM_4 and index 4 should return PID for COMM_5. TEST=Verify GPIO PM bits are correctly set through MS0x ACPI method. Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Change-Id: I3da4945e93605a297baff076295433164fdf613d Reviewed-on: https://review.coreboot.org/c/coreboot/+/41721 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28drivers/vpd: Fix VPD speed regressions on non-x86 devicesJulius Werner
CB:34634 expanded the VPD code to also be usable from romstage, shuffling a few things around and adding some extra infrastructure in the process. Unfortunately, the changes seem to have only been written with x86 devices in mind and make coreboot always load the whole VPD FMAP section (not just the used part) on devices where rdev_mmap() is not a no-op. This patch rewrites the VPD code to be based on region_device structures that only represent the VPD area actually used (rather than the whole FMAP section), and that only get mapped when accessed. (It would be even better to pull this concept into the VPD decoder itself, but since that is taken from third-party code and accesses in early stages aren't very common, let's not go there for now.) It also moves the copying into CBMEM to romstage so that late romstage accesses can already benefit from it, and makes early decoding available in all stages because at this point, why not. Also fix a long-standing bug where the 'consumed' counter was not reset between vpd_decode_string() calls to the RO and the RW VPD. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I55a103180b290c1563e35a25496188b6a82e49ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/41757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-05-28soc/intel/tigerlake: Configure THCWonkyu Kim
Enable/Disable THCx though devicetree BUG=None BRANCH=None TEST=Boot and check FSP log for THC setting Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: If7683969161be67f68f441c28c80503de39079b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41571 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28device/resource_allocator_v4: Improve the logging in resource allocatorFurquan Shaikh
This change makes the following improvements to debug logging in resource allocator: 1. Print depth is added to functions in pass 1 to better represent how the resource requirements of child devices impact the resource windows for parent bridge. 2. Device path is added to resource ranges to make it easier to understand what device the resouce ranges are associated with. 3. Prints in pass 2 (update constraints, resource ranges, resource assignment) are shifted left by 1 to make it easier to visualize resource allocation for each bridge including domain. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I3356a7278060e281d1a57d253537b097472827a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41478 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28device/resource_allocator_v4: Change BIOS_SPEW to BIOS_DEBUGFurquan Shaikh
This change updates the log level for prints in resource allocator v4 to BIOS_DEBUG instead of BIOS_SPEW. These are critical in debugging issues and should be enabled at log level BIOS_DEBUG. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ib863619f5e1214e4fe6f05c52be6fa2de36e6c3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/41477 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28Revert "Revert "mb/google/volteer: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ↵Furquan Shaikh
ports"" This reverts commit 1726fa1f0ce474cde32e8b32be34a212aff3ffba. Reason for revert: Resource allocator is split into old(v3) and new(v4). So, this change to enable hotplug resource allocator for volteer can land back. BUG=b:149186922 Change-Id: Ib6a4df610b045fbc885c70bff3698a032b79f770 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-28Revert "Revert "pciexp_device: Add option to allocate prefetch memory above ↵Furquan Shaikh
4G boundary"" This reverts commit e15f352039a371156ceef37f0434003228166e99. Reason for revert: Resource allocator is split into old(v3) and new(v4). So, this change to provide an option to allocate prefetch memory above 4G boundary can be added back. Since the support for allocating above 4G boundary is available only in resource allocator v4, Kconfig option is accordingly updated to add depends on RESOURCE_ALLOCATOR_V4. Change-Id: I94e5866458c79c2719fd780f336fb5da71a7df66 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41467 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28device: Enable resource allocation above 4G boundary with allocator v4Furquan Shaikh
This change adds back CB:39487 which was reverted as part of CB:41412. Now that the resource allocator is split into old(v3) and new(v4), this change adds support for allocating resources above 4G boundary with the new allocator v4. Original commit message: This change adds support for allocating resources above the 4G boundary by making use of memranges for resource windows enabled in the previous CL. It adds a new resource flag IORESOURCE_ABOVE_4G which is used in the following ways: a) Downstream device resources can set this flag to indicate that they would like to have their resource allocation above the 4G boundary. These semantics will have to be enabled in the drivers managing the devices. It can also be extended to be enabled via devicetree. This flag is automatically propagated by the resource allocator from downstream devices to the upstream bridges in pass 1. It is done to ensure that the resource allocator has a global view of downstream requirements during pass 2 at domain level. b) Bridges have a single resource window for each of mem and prefmem resource types. Thus, if any downstream resource of the bridge requests allocation above 4G boundary, all the other downstream resources of the same type under the bridge will be allocated above 4G boundary. c) During pass 2, resource allocator at domain level splits IORESOURCE_MEM into two different memory ranges -- one for the window below 4G and other above 4G. Resource allocation happens separately for each of these windows. d) At the bridge level, there is no extra logic required since the resource will live entirely above or below the 4G boundary. Hence, all downstream devices of any bridge will fall within the window allocated to the bridge resource. To handle this case separately from that of domain, initializing of memranges for a bridge is done differently than the domain. Limitation: Resources of a given type at the bridge or downstream devices cannot live both above and below 4G boundary. Thus, if a bridge has some downstream resources requesting allocation for a given type above 4G boundary and other resources of the same type requesting allocation below 4G boundary, then all these resources of the same type get allocated above 4G boundary. Change-Id: I92a5cf7cd1457f2f713e1ffd8ea31796ce3d0cce Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41466 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-28soc/intel/tigerlake: Correct GPIO community PID configurationEric Lai
Current implementation returns the incorrect GPIO community PID. The GPIO community index 3 should return PID for COMM_4 and index 4 should return PID for COMM_5. TEST=Verify PCR port id is correct for each community. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I5dc48e5b31f43853b3a613c17f13f7df71f1fbfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/41725 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28Remove new additions of "this file is part of" linesElyes HAOUAS
Change-Id: I6c69dcad82ee217ed4760dea1792dd1a6612cd8b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-28mb/google/volteer: Create terrador variantDavid Wu
Create the terrador variant of the volteer reference board BUG=b:156435028 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_TERRADOR Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I088861d1f8b7b4ee8de1e5ab6c7d3109ffd0531b Reviewed-on: https://review.coreboot.org/c/coreboot/+/41718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-05-28drivers/smmstore/Kconfig: Add a proper dependencyArthur Heymans
This feature is only available if properly hooked up to an smihandler. Change-Id: I99baef07b0623f9a6b41e8b8e000a89589c298d0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41730 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28mb/lenovo/t440p: Include ACPI for battery thresholdAmit Caleechurn
This fixes ACPI errors below when invoking tlp-stat and allows setting battery thresholds as natacpi is now enabled. thinkpad_acpi: acpi_evalf(BCTG, dd, ...) failed: AE_NOT_FOUND thinkpad_acpi: acpi_evalf(BCTG, dd, ...) failed: AE_NOT_FOUND Test: Fedora 32 [also on Fedora 31 before the upgrade] Kernel 5.6.12-300 Signed-off-by: Amit Caleechurn <acaleechurn@gmail.com> Change-Id: Ie345cdd05e38a8b7f646f44d814446543baeed3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/41472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-28mb/google/deltaur: Remove devicetree chip drivers/netKyösti Mälkki
Change-Id: Ia56305e9554b666f8eaf590a91be84e5cac4c75c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41701 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28soc/sifive/fu540: Add chip_operations stubKyösti Mälkki
Change-Id: If06695745bb72f883314e5514c616223b0210a2f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Philipp Hug <philipp@hug.cx>
2020-05-28soc/ucb/riscv: Add chip_operations stubKyösti Mälkki
Change-Id: Ie4f70429c516fff613d372fec7c1c955645f1c6d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Philipp Hug <philipp@hug.cx>
2020-05-28mb/biostar/a68n_5200: Remove spurious SPD eeprom entriesKyösti Mälkki
Change-Id: I1996c1b57310c4c0542c9ed47d1638ddd9c55680 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41713 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28mb/emulation: Remove fake devicetree.cb componentsKyösti Mälkki
Change-Id: I31853e3ede786eb9e10704674e42dd56c3a48688 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Philipp Hug <philipp@hug.cx>
2020-05-28soc/intel/xeon_sp/skx: Remove invalid declarationKyösti Mälkki
The declaration is autogenerated inside static.c file from the pathname. The declaration here also lacked _skx_ part from the name. Change-Id: I3adce9147e9376f6d73e410fdd4c0ee800178b58 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-28soc/intel/xeon_sp/cpx: Remove redundant declarationKyösti Mälkki
The declaration is autogenerated inside static.c file from the pathname. Change-Id: I6eda101a69522d6d526da7c174aa3085ca0fb221 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-28mb/google/hatch: Drop rt8168 Kconfigs for baseboard hatchFurquan Shaikh
This change drops rt8168 ethernet Kconfig options for baseboard hatch since it does not really support an ethernet device. Change-Id: I7c19dbeb2f64b0643b082a9c588f8b14db4dfb8a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41661 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28mb/google/hatch: Split Kconfigs into BASEBOARD_HATCH and BASEBOARD_PUFFFurquan Shaikh
mb/google/hatch supports two different reference platforms - Hatch and Puff. This change adds Kconfigs BOARD_GOOGLE_BASEBOARD_PUFF in addition to BOARD_GOOGLE_BASEBOARD_HATCH to better organize the Kconfig selections and reduce redundancy. In addition to this, a new config BOARD_GOOGLE_HATCH_COMMON is added that selects all the common configs for both baseboards. TEST=Verified using abuild --timeless option that all hatch variants generate the same coreboot.rom image with and without this change. Change-Id: I46f8b2ed924c10228fa55e5168bf4fe6b41ec36c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41660 Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28mb/google/volteer: Select SX9310 driver in KconfigDuncan Laurie
There are SX9310 devices present in devicetree.cb but the driver is not enabled so it is not getting used. Change-Id: I625233013a2e14eaf758e56027774fbf5df3bc83 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41700 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28cpu/intel/common: Fix typo in commentElyes HAOUAS
Change-Id: I9ff49adebc1156d33c648efb8e9854b13c0ef859 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-28soc/intel/common: Improve Type16 SMBIOS tablesPatrick Rudolph
Use CAPID0_A to provide information closer to reality. * Correctly advertise ECC support, max DIMM count and max capacity * CAPID0_A hasn't changed since SNB, but most EDS mark the bits as reserved even though they are still used by FSP. * Assume the same bits for Tiger Lake as for Ice Lake * Assume the same bits for Skylake as for Coffee Lake * Add CAPID0_A to Icelake headers The lastest complete documentation can be found in Document: 341078-002. Change-Id: I0d8fbb512fccbd99a6cfdacadc496d8266ae4cc7 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-05-28sb/intel/{bd82x6x|ibexpeak}: Clear flush_* in FADTPatrick Rudolph
Both fields are ignored if WBINVD is set, which is true for all processors since i486. Change-Id: Ibad56046e2c1b8595dc31e5861b9fd1fd7d2d6f3 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-05-28lib/cbfs: refactor code culling compression checksAaron Durbin
Provide helper functions to determine if a compression algorithm is supported in a given stage. Future patches can use those functions to amend which algorithms to include in the final link. BUG=b:155322763,b:150746858,b:152909132 Change-Id: I898c939cec73d1f300ea38b165f379038877f05e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-28soc/intel/jasperlake: Use coreboot lock down configAamir Bohra
Allow lockdown configuration from using CHIPSET_LOCKDOWN_COREBOOT config. TEST=Build and boot waddledoo board Change-Id: I3abaa737580ef45b98cabfa23edd84162037dd70 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41534 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28mb/google/dedede: Enable Intel Speed Shift TechnologyKarthikeyan Ramasubramanian
Enable Intel Speed Shift Technology (ISST) by default. Disable ISST in waddledee and waddledoo variants on early phases. BUG=b:151281860 TEST=Build and boot the mainboard. Ensure that cpufreq driver to configure P-states is enabled in kernel on boards where board version is provisioned. Change-Id: Id65d7981501c2f282e564bfc140f8d499d5713e8 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2020-05-27mb/google/zork: Add Picasso based Zork mainboard and variantsRaul E Rangel
This is a copy of the mb/google/zork directory from the chromiumos coreboot-zork branch. This was from commit 29308ac8606. See https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/29308ac8606/src/mainboard/google/zork Changes: * Minor changes to make the board build. * Add bootblock.c. * Modify romstage.c * Removed the FSP_X configs from zork/Kconfig since they should be set in picasso/Kconfig. picasso/Kconfig doesn't currently define the binaries since they haven't been published. To get a working build a custom config that sets FSP_X_FILE is required. BUG=b:157140753 TEST=Build trembyle and boot to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3933fa54e3f603985a0818852a1c77d8e248484f Reviewed-on: https://review.coreboot.org/c/coreboot/+/41581 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-07 11:32:49 +0000