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2015-09-16riscv-memlayout: fix existing memlayout issues, add sbi interfaceThaminda Edirisooriya
Existing memlayout code placed sections in overlapping areas, and would overwrite the payload if it was large enough. Update memlayout.ld in src/mainboard/emulation/spike-riscv to represent the spike emulator, and add sbi interface which now has room into src/arch/riscv/bootblock.S. Add utility code to qemu-riscv, but emulator itself has yet to be updated to new ISA and as such should not be used. Update Makefile to include all the files necessary for sbi interface. Clean up unused include in src/arch/riscv/include/atomic.h and whitespace in src/mainboard/emulation/spike-riscv/memlayout.ld Fixed whitespace issues in spike_util.c Change-Id: Id97fe75e45ac1361005bec6d421756ee3f98a508 Signed-off-by: Thaminda Edirisooriya <thaminda@google.com> Reviewed-on: http://review.coreboot.org/11370 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-09-16kunimitsu: Enable ALS connected to ECDuncan Laurie
Kunimitsu has an ambient light sensor connected to the EC which is presented to the OS as a standard ACPI0008 device. BUG=chrome-os-partner:43493 BRANCH=none TEST=emerge-kunimitsu coreboot Change-Id: I7998c19e5514eda781cc20888cdb0732f81389ae Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a67e5ddfccea0776841fabe04be55c1854bf31f2 Original-Change-Id: I381dc9c5777370df2ea4c41c9e153b3277082718 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298252 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11645 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-16glados: Enable ALS connected to ECDuncan Laurie
Glados has an ambient light sensor connected to the EC which is presented to the OS as a standard ACPI0008 device. BUG=chrome-os-partner:43493 BRANCH=none TEST=test ALS functionality on glados P2 board Change-Id: I4a4913a1b407720d85f6e630b674e550bf5e36df Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: aee2b2446ca45039f1b4866feb83754861dba054 Original-Change-Id: I61f3f31ba077f63b36aa0cd9707e128e65c9ea7d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298251 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11644 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-16kunimitsu: Disable Deep S3 on kunimitsu platformSubrata Banik
This patch will reset Deep S3 flag, hence S3 will work. BUG=chrome-os-partner:40635 BRANCH=None TEST=Build and Boot Kunimitsu and verify S3 is working. Change-Id: Iad87b7a8f7bf560861a270a8c19153cfc3850bc4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fbfaa29041be49e4c39d19cb94f01ad10d12c7d5 Original-Change-Id: I5ae1738c5de1bee1ad9a45ebde074a6a378492af Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/297903 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11643 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-16Move final Intel chipsets with ME to intel/common/firmwareMartin Roth
This switches the final 4 Intel platforms that use ME firmware from using code specific to the platform to the common IFD Kconfig and Makefile. braswell, broadwell, bd82x6x (cougar point & panther point) and ibexpeak Change-Id: Id3bec6dbe2e1a8a90f51d9378150dbb44258b596 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10876 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-09-16x86: remove double link step for romstageAaron Durbin
Now that cbfstool supports XIP for romstage utilize it. This removes the double link steps with the cbfstool locate and add-stage sandwich. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted on glados. Change-Id: I1ec555f523a94dd4b15fe8186cbe530520c622c0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11670 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-16AMD Merlin Falcon: update vendorcode header files to CarrizoPI 1.1.0.0WANG Siyuan
This is required the BLOB change Icb7a4f07 "AMD Merlin Falcon: Update to CarrizoPI 1.1.0.0 (Binary PI 1.4)" This is tested on Bettong Alfa(DDR3) and Beta(DDR4). Both of the boards can boot to Windows 8.1. PCIe slots, USB and NIC work. Change-Id: Ibe141c16f8f9eac2adc5d5f45a1f354fb2a7f33c Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/11148 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2015-09-16AMD Steppe Eagle: update vendorcode header files to MullinsPI 1.0.0.AWANG Siyuan
This is required the BLOB change I67817dc59 AMD Steppe Eagle: Update to MullinsPI 1.0.0.A (Binary PI 1.1). This is tested on Olive Hill Plus. The board can boot to Windows 7. PCIe slot, USB and NIC work. Change-Id: I605df26b61bdffabd74846206ad0b7bf677ebed1 Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/11225 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-09-15riscv-trap-handling: Add functionality, prevent stack corruptionThaminda Edirisooriya
Trap handling code was bugged in that it loaded in the wrong stack pointer, overwriting the space the processor uses to talk to its host for doing device requests. Fix this issue, as well as add support for handling misaligned loads the same way we handle misaligned stores. Change-Id: I68ba3a114b7167b3212bb0bed181a7595f0b97d8 Signed-off-by: Thaminda Edirisooriya <thaminda@google.com> Reviewed-on: http://review.coreboot.org/11620 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-09-14qemu: initialize lapicGerd Hoffmann
Recently qemu stopped doing a basic lapic setup and expects the firmware to handle this properly (like on real hardware). So let's do that so coreboot works properly on qemu 2.4+. Here is the qemu commit message for the change: <quote> commit b8eb5512fd8a115f164edbbe897cdf8884920ccb Author: Nadav Amit <namit@cs.technion.ac.il> Date: Mon Apr 13 02:32:08 2015 +0300 target-i386: disable LINT0 after reset Due to old Seabios bug, QEMU reenable LINT0 after reset. This bug is long gone and therefore this hack is no longer needed. Since it violates the specifications, it is removed. Signed-off-by: Nadav Amit <namit@cs.technion.ac.il> Message-Id: <1428881529-29459-2-git-send-email-namit@cs.technion.ac.il> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> </quote> Change-Id: I022f3742475d3f3477fc838b1e2bce69287b6b8e Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/11611 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-14AGESA S3 support: Fix excessive stack usageKyösti Mälkki
Commit 300caced9 introduced stack overflow when HAVE_ACPI_RESUME is selected as the temporary storage for MTRRs is 4KiB. Change-Id: I993df6abc04436fb135822729c4931c5c7496e5a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/11633 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-11endian: fix le64toh()Aaron Durbin
This change was sitting in my git index, and I failed to push it in the original patch. Change-Id: If6f49c3c2b7908f93a99c23a80536ad5937959c7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11622 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-09-10endian: add portable endian functionsAaron Durbin
The current endian API support in coreboot doesn't follow any known API that can be shared in userland as well as coreboot proper. To that end provide big and little endian helper functions that can be used in code that can be shared within coreboot proper and userland tools. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi Change-Id: I737facab0c849cb4b95756eefbf3ffd69e558b32 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11618 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-09-10fsp1_1: provide binding to UEFI versionAaron Durbin
FSP has some unique attributes which makes integration cumbersome: 1. FSP header files do not include the types they need. Like EDKII development it's expected types are provided by the build system. Therefore, one needs to include the proper files to avoid compilation issues. 2. An implementation of FSP for a chipset may use different versions of the UEFI PI spec implementation. EDKII is a proxy for all of UEFI specifications. In order to provide flexibility one needs to binding a set of types and structures from an UEFI PI implementation. 3. Each chipset FSP 1.1 implementation has a FspUpdVpd.h file which defines it's own types. Commonality between FSP chipset implementations are only named typedef structs. The fields within are not consistent. And because of FSP's insistence on typedefs it makes it near impossible to forward declare structs. The above 3 means one needs to include the correct UEFI type bindings when working with FSP. The current implementation had the SoC picking include paths in the edk2 directory and using a bare <uefi_types.h> include. Also, with the prior fsp_util.h implementation the SoC's FSP FspUpdVpd.h header file was required since for providing all the types at once (Generic FSP 1.1 and SoC types). The binding has been changed in the following manner: 1. CONFIG_UEFI_2_4_BINDING option added which FSP 1.1 selects. No other bindings are currently available, but this provides the policy. 2. Based on CONFIG_UEFI_2_4_BINDING the proper include paths are added to the CPPFLAGS_common. 3. SoC Makefile.inc does not bind UEFI types nor does it adjust CPPFLAGS_common in any way. 4. Provide a include/fsp directory under fsp1_1 and expose src/drivers/intel/fsp1_1/include in the include path. This split can allow a version 2, for example, FSP to provide its own include files. Yes, that means there needs to be consistency in APIs, however that's not this patch. 5. Provide a way for code to differentiate the FSP spec types (fsp/api.h) from the chipset FSP types (fsp/soc_binding.h). This allows for code re-use that doesn't need the chipset types to be defined such as the FSP relocation code. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted on glados. Signed-off-by: Aaron Durbin <adubin@chromium.org> Change-Id: I894165942cfe36936e186af5221efa810be8bb29 Reviewed-on: http://review.coreboot.org/11606 Reviewed-by: Duncan Laurie <dlaurie@google.com> Tested-by: build bot (Jenkins)
2015-09-10riscv-trap-handling: Add implementation for trap calls in riscvThaminda Edirisooriya
RISCV requires the bios/bootloader to set up an interface by which it can get information about memory, talk to host devices, etc. Put implementation for spike in src/mainboard/emulation/spike-riscv/spike_util.c, and src/arch/riscv/trap_handler.c Change-Id: Ie1d5f361595e48fa6cc1fac25485ad623ecdc717 Signed-off-by: Thaminda Edirisooriya <thaminda@google.com> Reviewed-on: http://review.coreboot.org/11368 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-09-10riscv-virtual-memory: Add virtual memory setupThaminda Edirisooriya
Execution in supervisor level code in RISCV requires early setup of virtual memory. Add initialization calls in src/arch/riscv/virtual_memory.c to implement the required page table setup, and helper functions to use when jumping to the payload correctly in riscv. Change-Id: I46e080e0ee8dc13277d567dcd4bf0f61a4507b76 Signed-off-by: Thaminda Edirisooriya <thaminda@google.com> Reviewed-on: http://review.coreboot.org/11369 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-09-10intel/skylake: HAVE_UART_MEMORY_MAPPED doesn't exist anymorePatrick Georgi
... the configuration is handled further below in the file by virtue of select DRIVERS_UART_8250MEM Change-Id: Ie5481d23cd3ac3561958fd100bd05c0e4b03ce00 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11612 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-09-10skylake: Move ACPI init to SOC instead of mainboardDuncan Laurie
Move some remaining ACPI init code to the SOC instead of being done in each mainboard: - acpi_create_gnvs is now a local function - add a weak acpi_mainboard_gnvs() that can be used for mainboards to override or set additional NVS - add acpi_fill_madt() function for skylake - remove acpi_create_serialio_ssdt() function as it is unused BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I52225e8d38ed846c29d44872e3f4d6ebaf4a7e52 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c717bb418a0cb6002582572632e42b44b473f718 Original-Change-Id: I0910ac8ef25de265ae1fde16b68f6cbacedb4462 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297800 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11581 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10kunimitsu: Remove functions from acpi_tables.cDuncan Laurie
Remove the acpi_tables.c functions so these functions can move to SOC init code. The file itself is included by x86/arch code and must exist for the build to succeed. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-kunimitsu coreboot Change-Id: Ia9657f4a39c30ed7a0fd7ca4815bb2614f049911 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 93ae87f2429af5cb9d497f8b5ef8b8dffe370df4 Original-Change-Id: Ifc2f64dc1693e7bd3f5a43144d84ff033b2cfe8b Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297759 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11580 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10glados: Remove functions from acpi_tables.cDuncan Laurie
Remove the acpi_tables.c functions so these functions can move to SOC init code. The file itself is included by x86/arch code and must exist for the build to succeed. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I18e6a0be5eac053598b613b30b622c4963417919 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: af04eb112adf58578c8d2c9d3d182d4c2024abb2 Original-Change-Id: Ibe026d493c25d771357ea39e4b956629fbb799ac Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297758 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11579 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10sklrvp: Remove thermal.h and functions from acpi_tables.cDuncan Laurie
Remove thermal.h as it is not used by this board. Remove functions from acpi_tables.c so they can move to SOC. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-sklrvp coreboot (does not compile due to GPIO changes) Change-Id: I934fcc451a722f853034c0970074ee3259cc704f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7e3b5c0ed8295091d3d5761b8456f3c13c6bd8bc Original-Change-Id: If855f598e895e38c58657af17130158b2f73de81 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297757 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11578 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10intel/common: Print board ID if enabledDuncan Laurie
Read and print the board ID if it is enabled in the mainboard. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I9d50089242b3a2f461dff2b1039adc8f0347179e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f245854b30c40eda38453c1b0ae5d3b8b18c010f Original-Change-Id: Ifbd7c2666820ea146dc44fbc42bfe201cb227ff6 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297756 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11577 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10kunimitsu: Clean up mainboard code to match gladosDuncan Laurie
Clean up the intel/kunimitsu mainboard code to match the code and cleanups in glados. Many of these are trivial changes that do not impact things in a meaningful way but will make it easier to diff the code and keep the mainboards in sync. - use relative path for mainboard includes to make porting easier - fix trivial style issues to match glados so diffs are clean - pull GPIO configuration into gpio.h and use from there - remove thermal.h as it is not used on this board - make info message BIOS_INFO instead of BIOS_ERR - add support for SPD manufacturer and part number in SMBIOS BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-kunimitsu coreboot Change-Id: I64a053bcec0e0ff25a57f65659f391ab64d9a11a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e47f0fd3e00a665f07098c7ea0018d51b105d1be Original-Change-Id: Ib787f3ccc63115de48c4d608ca2bd81b58d24b6c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297752 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11576 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10kunimitsu: Select EC PD and software sync and do early initDuncan Laurie
Select the EC PD and software sync kconfig options so they are supported by the mainboard and call the EC early init function to reboot into RO in recovery mode. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-kunimitsu coreboot Change-Id: I48316df99b796c568c2481c72588b41f7147bec0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c7507470f82848062bc98da809d3c5fe1ca31998 Original-Change-Id: I822aac9c24718f226819e5d3fcc82a4024b7c5a7 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297751 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11575 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10kunimitsu: Select BOARD_ID_AUTO and clean up boardid codeDuncan Laurie
Select the BOARD_ID_AUTO kconfig option to have the coreboot tables populated with the board ID and print it early in romstage as well. Also clean up the code for it. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-kunimitsu coreboot Change-Id: I90bd85ef14543717287cbeaaab77e6c54b94df97 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1fed7de4a0650a497a240b091fd2eb99d59e1433 Original-Change-Id: I82e9d17ab618b1aae1fd874d9247b7d52b42334d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297750 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11574 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10glados: Add Board ID supportDuncan Laurie
Add support for reading board id and populating it in the coreboot tables so it is exposed to payloads. BUG=chrome-os-partner:40635 BRANCH=none TEST=boot on glados and look for reported board ID Change-Id: Iba93a913b67e3b3230aded289c2e25585dec1195 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 472cb7bc84136a1a8b284d661868e64eca4ec004 Original-Change-Id: I478dc0b2f96310b7adbd84701e70598a57306628 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297746 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11570 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10glados: Enable DPTFDuncan Laurie
- Add ACPI code for DPTF support with placeholder thresholds - Do not have custom PDL for mainboard - Do not have enable charger control for DPTF as there is already a complicated charge profile in the EC. We may still want to enable this but it would need to be tuned to work well with the EC profile. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I8cd2e0ea9c322ea92c101995e8e706f063428a45 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 55d3614441d6701a6d6f0f9d1ade94364ef2594a Original-Change-Id: Ie4587572742d3bcdba7c008fc195213ac50c9d9e Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297745 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11569 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10glados: Misc code cleanupsDuncan Laurie
- romstage.c is using gpio_configure_pads so it should really include soc/gpio.h instead of relying on it to come from "gpio.h" - consistent formatting of array initializers in pei_data.c - remove pei_data->ec_present flag as this is unused in skylake - fix printk level in spd/spd.c to be BIOS_INFO instead of BIOS_ERR - clean up acpi_slp_type usage in ec.c, remove unnecessary post codes, and cleaner console output message. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I0f76a560dc2c4197e66999752c52573ff0278430 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 67c29f900b7709b73bd0d1e0da26f96cca32828b Original-Change-Id: Ia2a320acf879fa85e9f6b06265cfe38e50e51e46 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297744 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11568 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10glados: Remove thermal.hDuncan Laurie
The constants defined in thermal.h are never used since there is no defined thermal zone. Remove it to result in less code to worry about in board ports. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: Idb716b47875b20e2110741ae9c154cc52307fbcf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 01be180b14b5381a8d339dab6c28428c7ac40c10 Original-Change-Id: Ibb710abc301b18d5632f4e01765ea0374b2fe787 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297743 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11567 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10glados: Change include headers to relative pathDuncan Laurie
To make it easier to port glados to a new board name change the include headers to use relative path name instead of including the mainboard name. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I6d184adab5b6b2df970ddd3998d3413f1330c12e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 11dd6b73f298cf4867f4a089478132d5e543ea90 Original-Change-Id: Ia8de127fb176784acbbee975e8b950f8c9824c5c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297742 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11566 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10skylake: Enable DPTF based on devicetree settingDuncan Laurie
Enable DPTF flag in ACPI NVS based on devicetree setting for the mainboard. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glaods coreboot Change-Id: I06ec6b050eb83c6a7ee1e48f2bd9f5920f7bfa51 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5728a8a37b1a50a483aa211563fb7ad312002ce5 Original-Change-Id: I08d61416c24b3c8857205cf88931f0bb2b38896c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297755 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11565 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10Skylake: Print GPIO MMIO base and pad config using gpio_debug tokenSubrata Banik
This will help development activity. Default GPIO print settings is disable, need to set gpio_debug = 1 to get GPIO MMIO dump. BUG=None BRANCH=None TEST=build coreboot and boot on Kunimitsu. Change-Id: I70c0a7bee1593cbc8e9fe1599f45bb50e3fc0f42 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 19102612ea40184307ecb0ce8b165b5b989f6911 Original-Change-Id: I4ea6349866c108382de9787bb9ed09fc78d9c770 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/296280 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11552 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10FSP: Pass FSP image base address to find_fspLee Leahy
Add a parameter to find_fsp which is the image base address. Adjust the fake stack in cache_as_ram.inc to pass in the read-only FSP image base address. In fsp_notify, pass in the read-only FSP image base address when the FSP header pointer is NULL. In find_fsp, validate the FSP binary image starting from the specified image base address. BRANCH=none BUG=None TEST=Build and run on Skylake Change-Id: Iac43c8aac8491390479af551765b514ca919928a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 592dae53f3b32694190cc5cb0fa6ca94df68aa95 Original-Change-Id: I7d6a415458a81f3b6bcdcfc9a90eceb2ac22144e Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/295593 Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11545 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-09glados: Select EC PD and call early EC initDuncan Laurie
Select the EC PD support in kconfig and call the EC early init code that will reboot into RO for recovery mode. BUG=chrome-os-partner:40635 BRANCH=none TEST=boot on glados in recovery mode Change-Id: Ifa1e2afd91a247c3830d8e705d9d34fb02239fe4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 135ef6e0e2c4864be1c25a9761e04cfe17aec51e Original-Change-Id: Iac8c092453bfbd94210462be0b377fb77410941d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297749 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11573 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-09samus: Use EC PD kconfig instead of manual PD rebootDuncan Laurie
Use the new kconfig entry to select the EC PD chip and have it be rebooted before the EC automatically insetad of being done manually by the board. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-samus coreboot Change-Id: I9e7baffec500a83af1fcf9b1e43d418489172918 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 53b086725d9d595e8eff7e1e35b9ba8db17ca199 Original-Change-Id: I9c9a7dd2ba2b78d681b448839f2c5d15ba9dfe60 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297748 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11572 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-09chromeec: Add kconfig entry for EC PD supportDuncan Laurie
Add a kconfig entry to indicate that a board has a PD chip and try to put it in RO mode before the EC during early init. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I170271de9b929fcb73d6b0e09171385a6d23f153 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 17e2d13261f4e35a8148039e324e22ec1da64b3c Original-Change-Id: I44eed5401beb1dc286e316cf0cc958da791580a5 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297747 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11571 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-09skylake: dptf: Add TSR3 thermal sensor and CPU code cleanupDuncan Laurie
- glados has more thermal sensors that could be used so add another entry in the DTPF thermal sensor ACPI code. - fix indentation block in cpu.asl. - declare \_SB.MPDL as external (it is already CondRefOf) so it does not need to be present in mainboard config if the mainboard does not want to override the default. BUG=chrome-os-partner:44622 BRANCH=none TEST=emerge-glados coreboot Change-Id: I1afe7013a24ee1215f5e968e25594f746bbdd17c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8d357437d06349039a94869b088c3c50b32933c0 Original-Change-Id: Ie87d52e735bf930a003e525cf1918789920922a5 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297335 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11558 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-09braswell: acpi: Allow DPTF thresholds to be defined at board-levelShawn Nematbakhsh
Similar to Skylake, allow braswell mainboards to override the default DPTF thresholds. BUG=chrome-os-partner:43884 TEST=Build for Strago BRANCH=Strago Change-Id: Id2574e98c444b8bf4da8ca36f3eeeb06568e78e0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 799a7006e8fcacfea8e8e0de5c99c3ce3c4ac34f Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Change-Id: If69627163237674a28fb8a26b4ce1886e5dbfc17 Original-Reviewed-on: https://chromium-review.googlesource.com/296033 Original-Commit-Ready: Shawn N <shawnn@chromium.org> Original-Tested-by: Shawn N <shawnn@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11546 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-09intel/skylake: ACPI: Clean up formatting in and fix ASL codeDuncan Laurie
Clean up the formatting in various ASL files and remove unused and/or incorrect field definitions. Add back the methods to set the USB power in S3 field in NVS as it is called by the chromium kernel at boot and is currently complaining that the method is not found. BUG=chrome-os-partner:44622 BRANCH=none TEST=emerge-glados coreboot Change-Id: I9726fb337bf53fa7dce72c5f30524b58abb4cab6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3a47eeba2792c3abed07be175034c709dbf60879 Original-Change-Id: I8e8388c9b834fd060990f8e069929ba829e29ab6 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295952 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11539 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-09x86: link ramstage the same way regardless of RELOCATABLE_RAMSTAGEAaron Durbin
Previously there were 2 paths in linking ramstage. One was used for RELOCATABLE_RAMSTAGE while the other was fixed location. Now that rmodtool can handle multiple secitons for a single proram segment there's no need for linking ramstage using lib/rmodule.ld. That also means true rmodules don't have symbols required for ramstage purposes so fix memlayout.h. Lastly add default rules for creating rmod files from the known file names and locations. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi. Inspected ramstage.debug as well as rmodules created during the build. Change-Id: I98d249036c27cb4847512ab8bca5ea7b02ce04bd Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11524 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09linking: add and use LDFLAGS_commonAaron Durbin
Add an LDFLAGS_common variable and use that for each stage during linking within all the architectures. All the architectures support gc-sections, and as such they should be linking in the same way. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi and analyzed the relocatable ramstage. Change-Id: I41fbded54055455889b297b9e8738db4dda0aad0 Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11522 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-09-09x86: link romstage and ramstage with 1 fileAaron Durbin
To reduce file clutter merge romstage.ld and ramstage.ld into a single memlayout.ld. The naming is consistent with other architectures and chipsets for their linker script names. The cache-as-ram linking rules are put into a separate file such that other rules can be applied for future verstage support. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi and dmp/vortex86ex. Change-Id: I1e8982a6a28027566ddd42a71b7e24e2397e68d2 Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11521 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09rmodule: use program.ld for linkingAaron Durbin
Bring rmodule linking into the common linking method. The __rmodule_entry symbol was removed while using a more common _start symbol. The rmodtool will honor the entry point found within the ELF header. Add ENV_RMODULE so that one can distinguish the environment when generating linker scripts for rmodules. Lastly, directly use program.ld for the rmodule.ld linker script. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi and analyzed the relocatable ramstage, sipi_vector, and smm rmodules. Change-Id: Iaa499eb229d8171272add9ee6d27cff75e7534ac Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11517 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09verstage: use common program.ld for linkingAaron Durbin
There's no reason to have a separate verstage.ld now that there is a unified stage linking strategy. Moreover verstage support is throughout the code base as it is so bring in those link script macros into the common memlayout.h as that removes one more specific thing a board/chipset needs to do in order to turn on verstage. BUG=chrome-os-partner:44827 BRANCH=None TEST=None Change-Id: I1195e06e06c1f81a758f68a026167689c19589dd Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11516 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09x86: link romstage like the other architecturesAaron Durbin
All the other architectures are using the memlayout for linking romstage. Use that same method on x86 as well for consistency. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Analyzed readelf output. Change-Id: I016666c4b01410df112e588c2949e3fc64540c2e Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11510 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09linking: move romstage and bootblock to use program.ldAaron Durbin
Instead of having separate <stage>.ld files in src/lib one file can be used: program.ld. There's now only one touch point for stage layout. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Analyzed readelf output. Change-Id: I4c3e3671d696caa2c7601065a85fab803e86f971 Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11509 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09x86: link ramstage like the other architecturesAaron Durbin
All the other architectures are using the memlayout for linking ramstage. The last piece to align x86 is to use arch/header.ld and the macros within memlayout.h to automaticaly generate the necessary linker script. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Analyzed readelf output. Change-Id: I012c9b88c178b43bf6a6dde0bab821e066728139 Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11508 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09linking: lay the groundwork for a unified linking approachAaron Durbin
Though coreboot started as x86 only, the current approach to x86 linking is out of the norm with respect to other architectures. To start alleviating that the way ramstage is linked is partially unified. A new file, program.ld, was added to provide a common way to link stages by deferring to per-stage architectural overrides. The previous ramstage.ld is no longer required. Note that this change doesn't handle RELOCATABLE_RAMSTAGE because that is handled by rmodule.ld. Future convergence can be achieved, but for the time being that's being left out. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Change-Id: I5d689bfa7e0e9aff3a148178515ef241b5f70661 Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11507 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-09-09x86: provide minimum alignment for romstageAaron Durbin
The current way the XIP address of romstage is calculated is by doing a 'cbfstool locate' using a bin file of romstage linked at address 0. That address is then used for re-linking romstage at the address spit out by cbfstool. Currently, the linker actually sets minimum alignment on the text sections as 32 bytes, but it doesn't actually honor that value. Instead, provide a minimum alignment for romstage so as not to fight the linker. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built asus/kfsn4-dre. Confirmed ROMSTAGE_BASE == gdtptr. Change-Id: Id6ec65d257df9ede78c720b0d7d4b56acfbb3f15 Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11588 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09rules.h: add fall through where no ENV_<STAGE> is setAaron Durbin
There are cases where rules.h can be pulled in, but the usage is not associated with a particular stage. For example, the cpu/ti/am335x build creates an opmap header. That is a case where there is no stage associated with the process. Therefore, provide a case of no ENV_>STAGE> being set. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Analyzed readelf output. Change-Id: Ia9688886d445c961f4a448fc7bfcb28f691609db Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11513 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-05 03:14:13 +0000