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2020-07-26skylake boards: Factor out copy-pasted PIRQ routesAngel Pons
Put them in common code just in case something depends on the values. Change-Id: Ief526efcbd5ba5546572da1bc6bb6d86729f4e54 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43851 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26mb/intel/saddlebrook/devicetree.cb: Use PCH_IRQ* macrosAngel Pons
Tested with BUILD_TIMELESS=1, its coreboot.rom does not change. Change-Id: I6375f97bc2a30beba5882792328f26e0675621cc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43867 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26device/device.h: Add `is_dev_enabled` functionAngel Pons
There are many places where we do this. Put it inside an inline function for convenience reasons. Change-Id: I5515a52458b6c78c1a723cb08e6471eb9bac9cd6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43871 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26cpu/intel/model_206ax: Clean up includesElyes HAOUAS
Change-Id: I5dc2e7b327278c281087c7461e62569aab3fe450 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26src: Remove unused include <cpu/x86/smm.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <cpu/x86/smm.h>' -- src/) <(git grep -l 'SMM_DEFAULT_BASE\|SMM_DEFAULT_SIZE\|SMM_BASE\|SMM_ENTRY_OFFSET\|SMM_SAVE_STATE_BEGIN\|APM_CNT\|APM_STS\|apm_control\|set_smm_gnvs_ptr\|set_acpi_mode_on_exit\|io_trap_handler\|southbridge_io_trap_handler\|mainboard_io_trap_handler\|southbridge_smi_set_eos\|smm_southbridge_clear_state\|global_smi_enable\|global_smi_enable_no_pwrbtn\|cpu_smi_handler\|northbridge_smi_handler\|southbridge_smi_handler\|mainboard_smi_gpi\|mainboard_smi_apmc\|mainboard_smi_sleep\|smramc_dev\|smramc_reg\|run_smm_relocate\|smm_is_really_enabled\|is_smm_enabled\|smram_open\|smram_close\|smram_lock\|smm_open\|smm_close\|smm_lock\|_binary_smm_start\|_binary_smm_end\|smm_runtime\|smm_module_params\|smm_handler_start\|smm_get_save_state\|smm_handler_t\|smm_loader_params\|smm_setup_relocation_handler\|smm_load_module\|backup_default_smm_area\|restore_default_smm_area\|smm_region\|SMM_SUBREGION_HANDLER\|SMM_SUBREGION_CACHE\|SMM_SUBREGION_CHIPSET\|SMM_SUBREGION_NUM\|smm_subregion\|smm_list_regions' -- src/)|grep '<' Change-Id: Id96ddad974a1460a6e6580cee1e45c863761af06 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26src: Remove unused 'include <cpu/intel/common/common.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <cpu/intel/common/common.h>' -- src/) <(git grep -l 'set_vmx_and_lock\|set_feature_ctrl_vmx\|set_feature_ctrl_lock\|cppc_config\|cpu_init_cppc_config\|intel_ht_sibling' -- src/) |grep '<' Change-Id: I4d749a32aa50fa2f005e8496983013977742a99b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42394 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26mb/google/zork: remove ACPI_FADT_RESET_REGISTER from fadt_flagsFelix Held
This applies what commit 79572e4f32f844f60338d1aafdba6b94f4111a5c does to the devicetree settings of the zork devices. Change-Id: Ife94818d771f137e56c51ad1598148f60fcf5345 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43820 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26mb/amd/mandolin: add default USB2 PHY tune parameters to devicetreeFelix Held
Change-Id: I4ea2fb83522d8810fe84e0a3f42bf44f2f911461 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43819 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26amd/picasso: rework USB2 PHY tune parameter handlingFelix Held
BUG=b:161923068 Change-Id: I67f23c0602e345fbd806e661a4462cf07f93ef64 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43783 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26soc/skylake: Configure SATA options only if SATA is enabledFelix Singer
Change-Id: I2860375c8ec4f9cda7709ee26db4c132a3b252b9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner
2020-07-25soc/amd/picasso: don't apply unconfigured USB2 PHY tune parametersFelix Held
Since FSP pre-populates the UPD struct with the non-zero default values, coreboot shouldn't set them to zero in the case that they aren't configured in the board's devicetree. Since all parameters being zero is a valid case, this patch adds another devicetree option that applying the devicetree settings for the USB2 PHY tuning depends on being set. BUG=b:161923068 Change-Id: I66e5811ce64298b0644d2881420634a8ce1379d7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43781 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25soc/intel/baytrail/southcluster.c: Align with BraswellAngel Pons
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: I49e9cef1dfaa62dcfbd1260cec459ff5910ad5da Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43202 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25soc/intel/baytrail/include/soc/irq.h: Add bracesAngel Pons
This reduces the differences between Bay Trail and Braswell, and avoids unlikely but potential bugs regarding missing braces in macros. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: Ic341fe70e7d6fb4751f2fefbdedbee5c90dd8d1f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43201 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25soc/intel/baytrail: Simplify pattrs definitionsAngel Pons
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: I90632909cd7d632d80739b3762e4ccba51624b75 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43200 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25soc/intel/baytrail/smm.c: Align with BraswellAngel Pons
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: Iaf557caac16b36e356a4fb1b05416718d86093bf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43199 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25soc/intel/baytrail/smihandler.c: Align with BraswellAngel Pons
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: Iaa6d5d72cd0368342205a9b98552c1e0762abbce Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43198 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25soc/intel/baytrail/cpu.c: Align with BraswellAngel Pons
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: I9d9edd774143b0a98773b6d5de630d116cb6f0b1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43197 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25soc/intel/baytrail/sd.c: Align with BraswellAngel Pons
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: I08ccbc70744a17d589450e321a3ed77d9a56492f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43196 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25soc/intel/baytrail/lpss.c: Align with BraswellAngel Pons
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: I98d17fc470149b181e8d92b8bcc5d99c68299212 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43195 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25soc/intel/baytrail/lpe.c: Align with BraswellAngel Pons
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: If75b4299918f5bee3cc68bc662d03f1a819aef68 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43194 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25mb/intel/cedarisland: undo set trig and bufdis for NF padsMaxim Polyakov
According to the documentation [1], RX Level/Edge Configuration (trig) and GPIO Tx/Rx Buffer Disable (bufdis) [2] settings are not applicable in native mode and BIOS does not need to configure them. Therefore, there is no need to configure this in gpio.h using PAD_CFG_NF_BUF_TRIG macros. Use PAD_CFG_NF instead and set this fields to 0. [1] Intel document #549921 [2] Intel document #336067-007US This is part of the patch set "src/mb/*, src/soc/intel/common/gpio: Remove PAD_CFG_NF_BUF_TRIG ": CB:43455 - cedarisland: undo set trig and bufdis for NF pads CB:43454 - tiogapass: undo set trig and bufdis for NF pads CB:43561 - h110m: undo set trig and bufdis for NF pads CB:43569 - soc/intel/common/gpio_defs: Remove PAD_CFG_NF_BUF_TRIG Change-Id: Ie3ee2eadc08826d49e8517c83ab6831398e3aa93 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43455 Reviewed-by: Michael Niewöhner Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25soc/intel/{baytrail,braswell}: Drop unneeded `return`Angel Pons
There's no reason to return the result of a void function. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: I677dec1622768874a51effd6d73f0b2329f27aed Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43193 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25soc/intel/baytrail/iosf.c: Add missing bracesAngel Pons
This reduces the differences between Bay Trail and Braswell, and prevents possible bugs when using these macros. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: I18e9a750901f1bf8d3b61f4b64bbed907bc1fa15 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43192 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25soc/intel/baytrail/elog.c: Align with BraswellAngel Pons
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: Ifd71881e3924dca3add1e788852e7eb078405d00 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43191 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25soc/intel/baytrail/cpu.c: Align with BraswellAngel Pons
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: I52d58c6b77cd870b5d3f5892521e4c82027c4cac Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43190 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25soc/intel/baytrail/acpi.c: Align with BraswellAngel Pons
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: I0b07f8d52203c0a6d20b747f36d4d22cf53c791c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-25soc/intel/baytrail/bootblock/bootblock.c: Move functionsAngel Pons
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: I34079985e165ce8d10c7a2b4f0dde15060132208 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43188 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25soc/intel/baytrail: Retype some pointersAngel Pons
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: Ia21b588a3ce07e33a7a8d36e1464c0ff5e456c3e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43187 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25soc/intel/tigerlake: Update Pkg C-State latenciesRavi Sarawadi
Update to recommended C-state entry/exit latencies as per BWG(611569) Rev 0.8: section 4.5.3.2.2 BUG=none TEST=Boot to OS and check C-State latencies "cat /sys/devices/system/cpu/cpu0/cpuidle/state*/{name,latency}" Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: Ic1258ecbb355b94889b30d01bceca586525bbe5e Reviewed-on: https://review.coreboot.org/c/coreboot/+/43316 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25src/include/ramdetect.h: Add missing includesElyes HAOUAS
Change-Id: I142f88aae67237ce6777f7f9e8849bae589beeb5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-25nb/intel/ironlake/raminit.c: initialize 'reply.command'Elyes HAOUAS
This to silent a bug found using gcc-10. src/northbridge/intel/ironlake/raminit.c: In function 'setup_heci_uma': src/northbridge/intel/ironlake/raminit.c:1805:11: error: 'reply.command' may be used uninitialized in this function [-Werror=maybe-uninitialized] 1805 | if (reply.command != (MKHI_SET_UMA | (1 << 7))) | ~~~~~^~~~~~~~ cc1: all warnings being treated as errors Change-Id: I0d13de549b6d428ac3675ee3f91eb5e42aeb25e8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42461 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25nb/intel/haswell/hostbridge_regs.h: Clean up registersAngel Pons
Add missing registers and sort them by ascending offsets. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change. Change-Id: I98f836668144032d920b56afff878acc0a58ed82 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-25mb/getac/p470/acpi_tables.c: Remove wrong commentElyes HAOUAS
Change-Id: I85c20d282949b51efd7cdd6f6e79b0b84ff62e2b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-25sb/intel/bd82x6x: Use common irqlinks.aslAngel Pons
Both files are identical, so we only need one copy in the tree. Change-Id: I07d7429caca7f6211a186b770c3608f642d4f269 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43159 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25soc/intel/tigerlake: Set power limits for Tiger Lake Y-SKUSumeet R Pawnikar
Set power limits in devicetree for Tiger Lake Y-SKU based volteer variant boards. BUG=b:152639350 BRANCH=None TEST=Built and tested power limits on volteer variant board. Change-Id: If4f1226473b48365e5962df9fff29910c99007fc Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43607 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25soc/intel/tigerlake: Update Tiger Lake SA IDsDerek Huang
This patch updates Tiger Lake SA DID and report platform. According to doc #613584, remove PCI_DEVICE_ID_INTEL_TGL_ID_U_1 and add below definitions of SA ID for TGL-UP4 skus: TGL-UP4(Y) (4+2): PCI_DEVICE_ID_INTEL_TGL_ID_Y_4_2 0x9A12h TGL-UP4(Y) (2+2): PCI_DEVICE_ID_INTEL_TGL_ID_Y_2_2 0x9A02h Change-Id: Id9d9c9ac3bf39582b0da610e6ef912031939c763 Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43061 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24soc/amd/picasso: mark usb2_phy_tune struct as packedFelix Held
Since the binary layout of this struct matters, it should be marked as packed. Since all struct elements are uint8_t, this shouldn't result in a different layout though. BUG=b:161923068 Change-Id: I6a390c3a3f35eaf8a72928b4cef0e9f405770619 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43780 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24mb/supermicro/x11-lga1151: Clean up gpio.hMaxim Polyakov
- remove comments (except the GPIO group), because it does not contain useful information that helps to understand the circuit, which we do not have; - remove empty lines between macros; - use a shorter PAD_CFG_GPI_INT() macro instead of PAD_CFG_GPI_TRIG_OWN() to set DRIVER mode. Change-Id: Ia7111341aab6f400da70d936849e4d4c9406905b Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-07-24supermicro/x11-lga1151/gpio: 4/4 Convert field macros to PAD_CFGMaxim Polyakov
Converts bit field macros to target PAD_CFG_*() macros, which were hidden in the comments. To do this, the following command was used: ./intelp2m -n -t 1 -p snr -file ../../src/mainboard/supermicro/ x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h ./intelp2m -n -t 1 -p snr -file ../../src/mainboard/supermicro/ x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h This is part of the patch set "mb/supermicro/x11-lga1151: Rewrite pad config using intelp2m": CB:42916 - 1/4 Decode raw register values CB:42917 - 2/4 Exclude fields for PAD_CFG CB:42918 - 3/4 Fixes some field macro CB:35679 - 4/4 Convert field macros to PAD_CFG Tested with BUILD_TIMELESS=1, Supermicro X11SSH-TF and X11SSM-F, remains identical. Change-Id: Idad7536854d4b1ae7dcf7934e81de438478fe059 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35679 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24supermicro/x11-lga1151/gpio: 3/4 Fixes some field macroMaxim Polyakov
Fixes some bit fields to convert to target macros PAD_CFG_*() macros. This is part of the patch set "mb/supermicro/x11-lga1151: Rewrite pad config using intelp2m": CB:42916 - 1/4 Decode raw register values CB:42917 - 2/4 Exclude fields for PAD_CFG CB:42918 - 3/4 Fixes some field macro CB:35679 - 4/4 Convert field macros to PAD_CFG Change-Id: I291f5f0f34505c466b610aa4049c8cc35937d140 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42918 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24supermicro/x11-lga1151/gpio: 2/4 Exclude fields for PAD_CFGMaxim Polyakov
This patch excludes bit fields that should be ignored [1] in order to convert current macros to target PAD_CFG_*() macros. The following commands were used for this: ./intelp2m -ii -fld cb -ign -t 1 -p snr -file ../../src/mainboard/ supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h /intelp2m -ii -fld cb -ign -t 1 -p snr -file ../../src/mainboard/ supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h [1] ignore RX Level/Edge Configuration (bit 26:25) and RX/TX Buffer Disable (bit 9:8) for the native function, because it does not affect the pad in this mode. This is part of the patch set "mb/supermicro/x11-lga1151: Rewrite pad config using intelp2m": CB:42916 - 1/4 Decode raw register values CB:42917 - 2/4 Exclude fields for PAD_CFG CB:42918 - 3/4 Fixes some field macro CB:35679 - 4/4 Convert field macros to PAD_CFG Change-Id: Icdf366a8d416598cec5afcb9a0fae6bf7ecd7ba0 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42917 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24mb/google/volteer: Remove unused dptf.asl filesTim Wawrzynczak
In the middle of the Great DPTF Refactor of 2020, new volteer variants were added, but their dptf.asl files are no longer used, so delete them. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I52f2042aa870a29026eb9fe122340ad07654e706 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-07-24assert.h: Do not use __FILE__ nor __LINE__ on timeless buildsAngel Pons
When refactoring, one can move code around quite a bit while preserving reproducibility, unless there is an assert-style macro somewhere... As these macros use __FILE__ and __LINE__, just moving them is enough to change the resulting binary, making timeless builds rather useless. To improve reproducibility, do not use __FILE__ nor __LINE__ inside the assert-style macros. Instead, use hardcoded values. Plus, mention that timeless builds lack such information in place of the file name, so that grepping for the printed string directs one towards this commit. And for the immutable line number, we can use 404: line number not found :-) Change-Id: Id42d7121b6864759c042f8e4e438ee77a8ac0b41 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-07-24nb/intel/sandybridge: Put host bridge registers into its own fileAngel Pons
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical. Change-Id: Ibfaecd6ab94d2caae9804bb827ce8e48a2166d35 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-24nb/intel/haswell: Put host bridge registers into its own fileAngel Pons
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I1d3a32a9386c0dee65eea6f9d0a2520d5e800db1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43690 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24device/pci_device.c: Do not complain about disabled devicesAngel Pons
One would expect disabled devices to not be present. So, don't print misleading warnings about it, because it only confuses people. Change-Id: I0f14174a1d460a479dc9f15b63486f4f27b8f67c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-07-24supermicro/x11-lga1151/gpio: 1/4 Decode raw register valuesMaxim Polyakov
Use the intelp2m utility [1,2] with -fld=cb options to convert the pad configuration format with the raw values of the DW0 and DW1 registers to the format with the bit fields macros: PAD_FUNC(), PAD_RESET(), PAD_TRIG(), PAD_BUF(), PAD_PULL(), etc... Also use the -ii options to generate the target macro in the comments, so that it is easier to understand what result we should get: ./intelp2m -ii -fld cb -t 1 -p snr -file ../../src/mainboard/supermicro/ x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h ./intelp2m -ii -fld cb -t 1 -p snr -file ../../src/mainboard/supermicro/ x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h [1] https://github.com/maxpoliak/pch-pads-parser [2] https://review.coreboot.org/c/coreboot/+/35643 This is part of the patch set "mb/supermicro/x11-lga1151: Rewrite pad config using intelp2m": CB:42916 - 1/4 Decode raw register values CB:42917 - 2/4 Exclude fields for PAD_CFG CB:42918 - 3/4 Fixes some field macro CB:35679 - 4/4 Convert field macros to PAD_CFG Tested with BUILD_TIMELESS=1, Supermicro X11SSH-TF and X11SSM-F, remains identical. Change-Id: I209ecdca75a0e62233d3726942c75ea06acc40a2 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42916 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24soc/intel/common/gpio_defs: Remove unused macro for NFMaxim Polyakov
Since the bufdis parameter (bit 9:8 in Pad Configuration DW0 register) does not affect the pad in native function mode, PAD_CFG_NF_BUF_IOSSTATE_IOSTERM() macro is not required to configure the pad. This macro has not been used, so deleting it will not affect anything. Change-Id: Icce6f130308dbe7032b99539f73688bae8ac17e0 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42913 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24soc/intel/common/gpio_defs: Undo set TxDRxE in GPI_TRIG_OWN()Maxim Polyakov
IO Standby State can use various settings independently of PAD_CFG_GPI_TRIG_OWN (). Instead, use other existing macros to set this parameter: - PAD_CFG_GPI_IOSSTATE_TRIG_OWN() - PAD_CFG_GPI_TRIG_IOS_OWN() Change-Id: I0f5fbd79f892981eb4534f50ac96a7d0c190f59e Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42912 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24soc/intel/common/gpio_defs: Improve some GPI macrosMaxim Polyakov
The patch updates existing macros for the GPI: - PAD_CFG_GPI_IOSSTATE_IOSTERM() - PAD_CFG_GPI_IOSSTATE() to allow the user to set the RX Level/Edge Configuration (trig) and the Host Software Ownership (own) fields in addition to IO Standby State (iosstate) and IO Standby Termination (iosterm) in the pad configuration using these macros. Change-Id: I8a70a366e816d31720d341a5d26880dc32ff9b8d Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner
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