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2020-07-07src/include: improve the description of hexstrtobinAnna Karas
Specify how hexstrtobin.c processes the strings of odd length. Signed-off-by: Anna Karas <aka@semihalf.com> Change-Id: Ie8cd8fb93d7dab08c5e7f28fc511b6381f5ad13a Reviewed-on: https://review.coreboot.org/c/coreboot/+/43089 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07mb/google/vilboz: Drop gpio.c from variants/vilbozPeichao Wang
Update GPIOs since Vilboz hardware design follow schematic V3.2, so gpio.c is unnecessary. BUG=b:157744136 BRANCH=NONE TEST=flash the bios to vilboz DUT and test touchpad function Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I575f8b233b56185f3281ad7127bc274bda5ea801 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42986 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07mb/google/vilboz: Fix variant ID for v3+ schematics for vilbozPeichao Wang
At this moment, Vilboz board version is 1 and it according to v3+ schematics, however WiFi power enable is active high. This change sets VARIANT_MIN_BOARD_ID_V3_SCHEMATICS for Vilboz as 1 and VARIANT_MIN_BOARD_ID_WIFI_POWER_ACTIVE_LOW as 2. BUG=b:160547115 BRANCH=None TEST=flash the bios to vilboz DUT and test WIFI module Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I9699bb839a801ab7d14c38b971ec28e3a322a997 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-07mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up3John Zhao
Two usb Type-C ports under the actual mux device. Each port has its own ACPI device entry. These nodes are the ones that the USB Type-C port/connector device will refer to in order to configure the mux. TEST=Verified the scope of PMC.MUX CONx in the SSDT on Tigerlake RVP board. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I7210e00cebe16a5fb8417ac23abad98e574e0982 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42953 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07mb/google/volteer: Change ov2740 HID of Chrome driver to match withDaniel Kang
Windows definition There was a review comment for Chromium Linux ov2740 driver that Windows driver already set the HID as INT3474 and suggested to have the same value for Chrome. The upstreamed Linux driver code has INT3474 as HID and this patch is to set the same HID in ACPI configuration. https://patchwork.kernel.org/patch/11540753/ BUG=b:160334865 BRANCH=none TEST=User-facing camera should work with the driver which set the HID as INT3474 Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Change-Id: I10e98d32899f31d91c1cc7ddfa099af73d8aef37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43006 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Daniel H Kang <daniel.h.kang@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07mb/google/volteer: Fix world-facing camera LED is always on issueDaniel Kang
Volteer world-facing camera has a privacy LED and it is supposed to be turned on only when the camera is being used. But the LED is always on and this is to fix the issue. RCAM_SNR_PWR_EN (RearCAMera_SeNsoR_PoWeR_ENable) GPIO, which controls the world-facing camera LED, was not in the power-up and power-down sequence definitions and this caused the issue. BUG=b:160341981 BRANCH=none TEST=Build and boot volteer proto 2 board. Start a camera app and check the world-facing camera LED is only turned on only when the camera is working. Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Change-Id: I564690baffddfdd0f998525992643aaf16ba4b02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42985 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Daniel H Kang <daniel.h.kang@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07dptf: Add support for IDSPTim Wawrzynczak
\_SB.DPTF.IDSP adverties to the DPTF daemon which policies the implementation supports. Added a new acpigen function to figure out which policies are used, and fills out IDSP appropriately. Change-Id: Idf67a23bf38de4481c02f98ffb27afb8ca2d1b7b Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07dptf: Add support for Fan and TSR optionsTim Wawrzynczak
DPTF has several options on how to control the fan (fine-grained speed control, minimum speed change in percentage points, and whether or not the DPTF device should notify the Fan if it detects low speed). Individual TSRs can also set GTSH, which is the amount of hysteresis inherent in the measurement, either from circuitry (if analog), or in firmware (if digital). BUG=b:143539650 TEST=compiles Change-Id: I42d789d877da28c163e394d7de5fb1ff339264eb Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07dptf: Add support for Running Average Power LimitsTim Wawrzynczak
This change adds support for emitting the PPCC table, which describes the ranges available as knobs for DPTF to tune. It can support min/max power, min/max time window for averaging, and the minimum adjustment size (granularity or step size) of each power limit. The current implementation only supports PL1 and PL2. BUG=b:143539650 TEST=compiles Change-Id: I67e80d661ea5bb79980ef285eca40c9a4b0f1849 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07dptf: Add support for Fan Performance StatesTim Wawrzynczak
This change adds support for generating the _FPS table for the DPTF Fan object. The table describes different levels of fan activity that may be applied to the system in order to actively cool it. The information includes fan speed at a (rough) percentage level, fan speed in RPM, potential noise level in centibels, and power in mA. BUG=b:143539650 TEST=compiles Change-Id: I5591eb527f496d0c4c613352d2a87625d47d9273 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07dptf: Add support for Charger Performance StatesTim Wawrzynczak
This change generates the DPTF TCHG.PPSS table in the SSDT. This table describes different charging rates which are available to use. DPTF can pick different rates in order to passively cool (or not) the system. BUG=b:143539650 TEST=compiles Change-Id: I6df6bfbac628fa4e4d313e38b8e6c53fce70a7f2 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07dptf: Add support for Critical PoliciesTim Wawrzynczak
This patch adds support for DPTF Critical Policies, which are consist of Method definitions only. They are `_CRT` and `_HOT`, which are defined as temperature thresholds that, when exceeded, will execute a graceful suspend or a graceful shutdown, respectively. BUG=b:143539650 TEST=compiles Change-Id: I711ecdcf17ae8f6e653f33069201da4515ace85e Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07dptf: Add support for Passive PoliciesTim Wawrzynczak
This patch adds support for emitting the Thermal Relationship Table, as well as _PSV Methods, which together form the basis for DPTF Passive Policies. BUG=b:143539650 TEST=compiles Change-Id: I82e1c9022999b0a2a733aa6cd9c98a850e6f5408 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07dptf: Add support for generation of Active PoliciesTim Wawrzynczak
This change adds support for generating the different pieces of DPTF Active Policies. This includes the Active Relationship Table, in addition to _ACx methods. BUG=b:143539650 TEST=compiles Change-Id: Iea0ccbd96f88d0f3a8f2c77a7d0f3a284e5ee463 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07drivers/intel/dptf: Add current participant Devices to DSDTTim Wawrzynczak
In this DPTF implementation, the participant device objects are written into the DSDT with only minimal Names attached (_HID/_ADR, _STA, _UID, PTYP, and _STR). All other Methods & Names will be written into the SSDT. If a device is not used in any policy, then its _STA is set to return 0 ("off"). BUG=b:143539650 TEST=Compiles. Change-Id: Ief69a57adce9ee0b19056ce6a11ed8a5b51b3f87 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07soc/intel/{tiger,jasper}lake: Add IPU to soc_acpi_nameTim Wawrzynczak
For both Tiger Lake and Jasper Lake, add the DEVFN for Image Processing Unit (IPU) to soc_acpi_name, which is set to return "IPU0". Change-Id: Ib11be5be7fbaec688d8788945a3bcab3f8d834a1 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42878 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07soc/intel/common: Add a minimal PCI driver for IPUTim Wawrzynczak
Add a minimal PCI driver for Intel's IPU, this allows devices to be added underneath it in the devicetree. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I531b293634a5d40112dc6af7b33fedb5e13f35e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42812 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07pci_ids: Add TGL & JSL IPU PCI IDsTim Wawrzynczak
Add PCI IDs for Intel's Image Processing Unit (IPU) for TGL & JSL Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I71dc95a6692e82ca25b0252b4f0789ee059df89f Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42811 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07drivers/intel/mipi_camera: Add camera power resource to SSDTSugnan Prabhu S
This change adds support function to parse entries in the devicetree to generate PowerResource entries for the MIPI camera. Change-Id: I31e198b50acf2c64035aff9cb054fbe3602dd83e Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41624 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07acpi: add STA function to return external variableSugnan Prabhu S
This change adds support function to add STA function which returns an external variable. Change-Id: I31755a76ee985ee6059289ae194537d531270761 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42245 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07drivers/intel/mipi_camera: Add support to handle CIO2 deviceMatt Delco
This change updates mipi_camera driver to handle CIO2 device type. Change-Id: I521740524bc1c4da3d8593f011a033542e4a872c Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42470 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07drivers/intel/mipi_camera: SSDT changes to add PLDMatt Delco
This change updates mipi_camera driver to add PLD section to SSDT. Change-Id: If65b9cbabca95e9645d8e5023ce7fd78b0625d1e Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42469 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07drivers/intel/mipi_camera: SSDT changes to add DSMMatt Delco
This change updates mipi_camera driver to add DSM section to SSDT. Change-Id: Ic60e972b6aebad171a7b77fe0d99781693adfb20 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42468 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07drivers/intel/mipi_camera: Add support for camera sensor in SSDTMatt Delco
This change updates mipi_camera driver to handle camera sensor. Change-Id: I581c9bf9b87eac69e88ec11724c3b26ee5fa9431 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42467 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07drivers/intel/mipi_camera: Handle NVM and VCM device typeMatt Delco
This change adds support in mipi_camera driver to handle NVM and VCM device types. Change-Id: I24cb7f010d89bc8d14e0b4c8fe693ba6e9c68941 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42466 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07drivers/intel/mipi_camera: Handle acpi_name and common codeMatt Delco
This change updates the mipi_camera driver to handle acpi_name based on device_type, if acpi_name is not set in the devicetree and moves some of the common code to separate methods. Change-Id: I15979f345fb823df2560db269e902a1ea650b69e Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41607 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07mb/google/zork: update telemetry settings for dalbozChris Wang
update telemetry value for SDLE test result. BUG=b:152922299,b:152369472 TEST=emerge-zork coreboot Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I14d218243931271ba15ec4113e9bc46c670fb2ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/42999 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07mb/google/volteer/var/terrador: Update gpio settings and overridetree.cbDavid Wu
Based on schematic and gpio table of terrador, generate gpio settings and overridetree.cb for terrador. BUG=b:156435028,b:151978872 TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Verify that the image-terrador.bin is generated successfully. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I4bf9081b034bc4cd566dde45586be8309cdbb4a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42302 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07mb/google/volteer/var/terrador: Add memory parts and generate DRAM IDsDavid Wu
This change adds memory parts used by variant terrador to mem_list_variant.txt and generates DRAM IDs allocated to these parts. Added memory 1. MT53E512M64D4NW-046 WT:E 2. MT53E1G64D8NW-046 WT:E BUG=b:159195585,b:152936481,b:156435028 TEST="emerge-volteer coreboot chromeos-bootimage", flash terrador and verify terrador boots to kernel. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ia14f76e9cb0df64961d46f4b61b39439e56f6a8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/41995 Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07lp4x: Add new memory parts and generate SPDsDavid Wu
This change adds the following memory parts to LP4x global list and generates SPDs using gen_spd.go for TGL: 1. MT53E512M64D4NW-046 WT:E 2. MT53E1G64D8NW-046 WT:E BUG=b:159195585,b:152936481,b:156435028 TEST=build. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: If69087e5e189b3e0f70e5f1afbfe3f884173d3b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-07-06trogdor: Add board variant checks in KconfigRavi Kumar Bokka
Diffentiate Lazor and trogdor build configuration Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: I3ad413ea6e658e939796bebdff8c1e0dd76417cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/42730 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06sb/intel/i82801jx/sata.c: Handle ABAR as a resourceAngel Pons
Instead of directly reading ABAR without any checking, do like i82801ix and treat it as a resource. This prevents problems if ABAR is not set. Change-Id: I4f888b748204860b0a7e1bf5611f5f3e487e8081 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-06src/**/acpi/smbus.asl: Drop dead codeAngel Pons
The `ENABLE_SMBUS_METHODS` symbol is not defined anywhere, so this code isn't even being tested. So, throw it into the bitbucket before it rots any further. If anyone needs that code ever again, it's in git history. Change-Id: I22e3f1ad54e81f811c9660d54f3765f3c6b83f01 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-06mb/google/volteer: Enable HotPlug on PCIe root port for the SD expressnick_xr_chen
Enable HotPlug for the PCIe root port that the SD express is on so the OS can re-train the link without needing a reboot if it goes down unexpectedly at runtime. BUG=b:156879564 BRANCH=master TEST=enable HotPlug on Volteer Root Port 7 (SD express) and check in linux that it is identified as a HotPlug capable root port Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com> Change-Id: Ie9d427dd297567f06123119a670b5ed2e1f73701 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42897 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06soc/intel: Drop unused `#include <reg_script.h>`Angel Pons
In some cases, the SoC did not even select `REG_SCRIPT` in Kconfig. Change-Id: I617f332b80c534997e06a91247d1be90a85573be Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-07-06mb/amd/mandolin: Drop SPD eeproms in devicetreeKyösti Mälkki
Even with previous platforms, these entries were not utilised for raminit. Change-Id: I9a9a1a292bad8c4c89cbacb826c80f4098cae00f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-07-06prog_loaders: Fix ramstage loading on x86Nico Huber
A regression sneaked in with 18a8ba41cc (arch/x86: Remove RELOCATABLE_ RAMSTAGE). We want to call load_relocatable_ramstage() on x86, and cbfs_prog_stage_load() on other architectures. But with the current code the latter is also called on x86 if the former succeeded. Fix that and also balance the if structure to make it more obvious. TEST=qemu-system-x86_64 boots to payload again. Change-Id: I5b1db5aac772b9b3a388a1a8ae490fa627334320 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43142 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06mb/google/volteer: Rename remaining pmc_mux/con to connPatrick Georgi
CB:43090 renamed con to conn to avoid issues when building on Windows. CB:42905 introduced more uses of the old name. Adapt the latter to comply with the former. Change-Id: I723141add5452fc541f67cb8591793f2d64cc231 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43141 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06mb/asus/p8z77-m_pro: Remove PS/2 keyboard & mouse duplicateKeith Hui
PS/2 keyboard and mouse devices are declared twice in the DSDT, once in mainboard and once in southbridge. It would appear in Windows Device Manager as two PS/2 keyboards and two PS/2 mouses, all with resource conflicts. This change drops the declaration from mainboard. The issue was discovered when this setup was copied for p8z77-m and being boot tested. Change-Id: I746a960aaf3992acbcb6a7364641fc4fd12002d2 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41225 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06drivers/ipmi: Increase BMC waiting message level from DEBUG to INFOPaul Menzel
As the booting the system can be delayed for a noticeable amount of time, often 60 seconds is the default, this is not a debug message. Chose log level BIOS_INFO. Change-Id: I941792148820c0e1d3fbc80197125fee8cedf09f Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-07-06nb/intel/i440bx: Add PMCR register to ACPI codeKeith Hui
p3b-f suspend code is going to use it. Change-Id: Iebc17257e9f690115ec35d94c7c36df39341f0df Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41092 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06nb/intel/i440bx: Refactor ACPI codeKeith Hui
Bring DRB7 OpRegion and top-of-memory indicator inside NB device. Use more concise ASL 2.0 syntax for TOM calculations. Change-Id: I2c74ef30a9bb48e02154f963b1ca3a4f5f3004df Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-06sb/intel/i82371eb: Don't fill \_SB.PCI0.MBRSKeith Hui
Only two mainboard groups use this southbridge: emulation/qemu-i440fx: Nothing creates or consumes this ACPI path. asus/p2b: It only fills the (mostly static) PIIX4E PM/SMBus I/O resources, which are being declared in DSDT. It is not doing anything useful and causes ACPI errors in Linux kernel[1][2], so it has to stop. [1] https://review.coreboot.org/c/coreboot/+/38601 [2] https://review.coreboot.org/c/coreboot/+/38304 Change-Id: I770047610e02c08191613b57c989b3bc1d464684 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-07-06mb/intel/dg43gt: Don't redefine MMCONF_BASE_ADDRESSArthur Heymans
Change-Id: I4d62a04778c8f634b48eee459808f640451b9b48 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-06arch/x86: Remove RELOCATABLE_RAMSTAGEKyösti Mälkki
We always have it, no need to support opting-out. For PLATFORM_HAS_DRAM_CLEAR there is a dependency of ramstage located inside CBMEM, which is only true with ARCH_X86. Change-Id: I5cbf4063c69571db92de2d321c14d30c272e8098 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43014 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06mb/google/volteer/var/voxel: Update gpio settings and overridetree.cbDavid Wu
Based on schematic and gpio table of voxel, generate gpio settings and overridetree.cb for voxel. BUG=b:157879197,b:155062762 TEST=FW_NAME=voxel emerge-volteer coreboot chromeos-bootimage Verify that the image-voxel.bin is generated successfully. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I49c1923e63d87f11de362fd893905ac2f1137bba Reviewed-on: https://review.coreboot.org/c/coreboot/+/42731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-07-06mb/google/zork: Apply cereme telemetry settings for dalbozChris Wang
Currently, the telemetry settings are not for the pollock platform and might causethe power and performance issue. so applied the Pollock reference board settings to Dalboz to improve the performance, and the values need to be updated after the SDLE test finished. BUG=b:157961590,b:152922299 TEST=Build. Change-Id: I0da5b81afaa5814c13ec0257dc0eb3471be94c29 Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2228257 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42998 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06mb/google/zork: Apply USB2 default phy tune parameter for Zork familyChris Wang
Apply the default USB2 phy tuning parameter for Zork family BUG=b:155132211 TEST=Build, verified the default value been applied on trembyle and the USB2 device works well. Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I1f00b04173796d70147e232bafa405487b0761e1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2260216 Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42997 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06mb/google/zork: Add USB2 phy tuning parameter for SI tuningChris Wang
Add the USB2 phy tuning parameter to adjust the USB 2.0 PHY driving strength. BUG=b:156315391 TEST=Build, verified the tuning value been applied on Trembyle. Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I3d31792d26729e0acb044282c5300886663dde51 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2208524 Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Tested-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-06mb/google/volteer: Add support for passive USB-C daughterboardCaveh Jalali
The USB-C SBU and HSL orientation configuration depends on the USB daughterboard used on the system. This patch adds an additional configuration for supporting passive USB daughterboards using "probe" directives to select the appropriate configuration at runtime. BUG=b:158673460 TEST=verified active USB DBs enumerate at USB3 speeds in linux Signed-off-by: Caveh Jalali <caveh@chromium.org> Change-Id: Ia4bd97de8f974531f97469a5e47ecf4d948beca9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 05:42:27 +0000