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2020-06-24jasperlake: enable DPTF functionality for dededeSumeet R Pawnikar
Enable DPTF functionality on jasperlake based dedede platform BRANCH=None BUG=None TEST=Built for dedede system Change-Id: I17b6e4e96abee6181b0d1f94c356a32aa82c19b9 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41668 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-24soc/amd/picasso: fix host bridge bus numbersAaron Durbin
The host bridge's resources covering bus numbers assumed 256 buses were being decoded. However, MMCONFIG was only covering 64 buses. This results in Linux complaining: acpi PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000 [bus 00-3f] only partially covers this bridge When retrieving the host bridge's resources fix up the bus numbers to utilize MMCONF_BUS_NUMBER Kconfig. I couldn't keep IASL from complaining when trying to do this statically. BUG=b:158874061 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ief1901743e2c99f583ef0181490d493d23734f64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-24mb/google/zork: Add UPD xhci0_force_gen1 for Trembyle and EzkinilLucas Chen
Add UPD xhci0_force_gen1 for Trembyle and Ezkinil. The default setting is set to disable, and set enabled for Ezkinil. Trambyle -> set default as disable. Ezkinil -> set enable by request. BUG=b:156314787 BRANCH=trembyle-bringup TEST=Build. Verified the setting will be applied on Ezkinil/Trembyle. Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Change-Id: I65d06bfe379f9e42101bfae1a02a619ee2f24052 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2216090 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-24soc/amd/picasso: Add UPD xhci0_force_gen1Chris Wang
Adding xhci0_force_gen1 UPD to force USB3 port to gen1. BUG=b:156314787 BRANCH=trembyle-bringup TEST=Build. Cq-Depend: chrome-internal:3013435 Change-Id: Iff3746e248625c253776c3bc3946d123b0635ffe Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2217662 Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42216 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-24mb/google/volteer/malefor: Update overridetree.cbWilliam Wei
1) Based on malefor schematics, disable unused I2C port, USB port, TBT PCIe 2) Add audio device to the tree BUG=b:150653745, b:154973095 TEST=FW_NAME=malefor emerge-volteer coreboot chromeos-bootimage Boot to kernel and check the devices' function worked properly. Signed-off-by: William Wei <wenxu.wei@bitland.corp-partner.google.com> Change-Id: I9ce465705e8b8f67ddbc9e4eb06c5a8bfac65fcb Reviewed-on: https://review.coreboot.org/c/coreboot/+/42246 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-24volteer: Create volteer2 variantNick Vaccaro
Create the volteer2 variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.1.1). Modified to alphabetize and update to duplicate latest volteer changes currently in the review and merge pipeline. Added the following missing files from the variants/volteer2/ folder: - gpio.c - include/variant/acpi/dptf.asl - acpi/mipi_camera.asl - Makefile.inc - memory/dram_id.generated.txt - memory/Makefile.inc - memory/mem_list_variant.txt - overridetree.cb BUG=b:159135047 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_VOLTEER2 Change-Id: I987c72b83dc993af248a753a2caa56be0f26c1ad Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42605 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-24soc/intel/tigerlake: Fix unresolved symbol CDW1 errorJohn Zhao
The dmesg shows unresolved symbol CDW1 with AE_NOT_FOUND error after booting to kernel. Fix the error by properly creating the buffer field CDW1 to cover all errors scenarios. BUG=b:140645231 TEST=Verified no AE_NOT_FOUND error related to \_SB.OSC.CDW1. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ibfe677f87736ce1930e06b9cd649791977116012 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42693 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-24soc/intel/broadwell/adsp: Fix 8-bit write on PCI_INTERRUPT_LINE registerElyes HAOUAS
The PCI_INTERRUPT_LINE register is one byte wide. Possible side effects of clearing the three bytes after PCI_INTERRUPT_LINE are unknown. Change-Id: I64e785309b0bf7f4d74436ea12a2444092deae22 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41009 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-24src: Report byte-sized access for GPE0Angel Pons
According to the ACPI specification, version 6.3: OSPM accesses GPE registers through byte accesses (regardless of their length). So, reporting dword-sized access is wrong and means nothing anyway. Tested on Asus P8Z77-V LX2, Windows 10 still boots. Change-Id: I965131a28f1a385d065c95f286549665c3f9693e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42671 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-24sb/intel/bd82x6x: Align mei_recv_msg() functionsAngel Pons
They only differ in rather small details, so we can iron them out. Tested on Asus P8Z77-V LX2, still boots. Change-Id: I01907f1b8576e82c74b7beeea31ae8ee3e2cc773 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42010 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-24soc/amd/stoneyridge: Correct ACPI CPU string prefixMatt DeVillier
Commit 9550e97 [acpi: correct the processor devices scope] changed the default CPU scope from _PR to _SB, but the default prefix in Stoneyridge's Kconfig was missed, leading to ACPI errors for 'AE_NOT_FOUND for object \_PR.P00n.' Fix the default prefix and eliminate the errors reported in dmesg. Test: boot Linux w/5.3 kernel on google/liara, check for errors Change-Id: I5611b6836062a0a9f90036d7fe40cd98bd730af3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-24ACPI: Replace smm_setup_structures()Kyösti Mälkki
Except for whitespace and varying casts the codes were the same when implemented. Platforms that did not implement this are tagged with ACPI_NO_SMI_GNVS. Change-Id: I31ec85ebce03d0d472403806969f863e4ca03b6b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-24ACPI: Replace uses of CBMEM_ID_ACPI_GNVSKyösti Mälkki
These are the simple cbmem_find() cases. Also drop the redundant error messages. Change-Id: I78e5445eb09c322ff94fe4f65345eb2997bd10ef Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-06-24ACPI: Add framework for GNVS initialisationKyösti Mälkki
Provide common initialisation point for setting up GNVS structure before first SMI is triggered. Change-Id: Iccad533c3824d70f6cbae52cc8dd79f142ece944 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42423 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-24volteer: Create delbin variantZhuohao Lee
Create the delbin variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.1.1). BUG=b:158797761 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_DELBIN Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Change-Id: Icf5fc6b9cc6a7c47e52103b2d396bcddb26adf50 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-24mb/amd/mandolin: resize EC FMAP section to match EC firmware sizeFelix Held
The EC firmware is 128k including its header, so there's no need to reserve another 4k for the header. TEST=Mandolin still boots. Change-Id: Id3a7a087bf37461ca8ad3da9a809f13d7f0d570c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42705 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-23hatch: Create wyvern variantPaul Fagerburg
Create the wyvern variant of the puff reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.1.1). BUG=b:158269582 BRANCH=None TEST=util/abuild/abuild -p none -t google/hatch -x -a make sure the build includes GOOGLE_WYVERN Signed-off-by: Paul Fagerburg <pfagerburg@google.com> Change-Id: Id7a090058d2926707495387f7e90b3b8ed83dac7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42551 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-23hatch: Create faffy variantEdward O'Callaghan
Create the faffy variant of the puff reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.1.1). V.2: Manually modified to keep Kconfig sorted. BUG=b:157448038 BRANCH=None TEST=util/abuild/abuild -p none -t google/hatch -x -a make sure the build includes GOOGLE_FAFFY Signed-off-by: Edward O'Callaghan <quasisec@google.com> Change-Id: I5f14c2d6144ce3c2e48488ca81f31b3c04dc5fb9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42717 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-23src/*: Update makefiles to exclude x86 code from psp-verstageMartin Roth
The assumption up to this point was that if the system had an x86 processor, verstage would be running on the x86 processor. With running verstage on the PSP, that assumption no longer holds true, so exclude pieces of code that cause problems for verstage on the PSP. This change will add these files to verstage only if the verstage architecture is X86 - either 32 or 64 bit. BUG=b:158124527 TEST=Build and boot on Trembyle Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I797b67394825172bd44ad1ee693a0c509289486b Reviewed-on: https://review.coreboot.org/c/coreboot/+/42062 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-23mb/amd/mandolin/acpi: drop gpe.aslFelix Held
Change-Id: I366108334006c81a4d5fb193f583a1e83f7c1456 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-23mb/google/zork: Add support for fingerprint deviceFurquan Shaikh
This change adds support for fingerprint device in overridetree for the following variants: 1. berknip 2. morphius 3. trembyle Generates the following node in SSDT1: Scope (\_SB.FUR1) { Device (CRFP) { Name (_HID, "PRP0001") // _HID: Hardware ID Name (_UID, Zero) // _UID: Unique ID Name (_DDN, "Fingerprint Reader") // _DDN: DOS Device Name Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { UartSerialBusV2 (0x002DC6C0, DataBitsEight, StopBitsOne, 0x00, LittleEndian, ParityTypeNone, FlowControlNone, 0x0040, 0x0040, "\\_SB.FUR1", 0x00, ResourceConsumer, , Exclusive, ) GpioInt (Level, ActiveLow, ExclusiveAndWake, PullDefault, 0x0000, "\\_SB.GPIO", 0x00, ResourceConsumer, , ) { // Pin list 0x0006 } }) Name (_S0W, 0x04) // _S0W: S0 Device Wake State Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x0A, 0x03 }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, Package (0x01) { Package (0x02) { "compatible", "google,cros-ec-uart" } } }) } } BUG=b:147853944 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I7ccb3633332ce3e388293872af7b22f1867c8465 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-23palkia: separate the gpio pins control for the second touchZhuohao Lee
There are two touch screen controllers on the Palkia device. One is on the lid; another is on the base. To support the different control path (for example: turning off the base's touch event when we don't want to use it however still keeping the lid's touch event), we use the different gpio pins to control the second touch. As a result, we need to modify the devicetree to adopt this change. With this change, we can control the primary and secondary touch screen controller respectively. BUG=b:149714955 TEST=lid/base touch screen works correctly Change-Id: I1f896e334e51c78300af724cbef8d57641ae5612 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-23mb/google/hatch: Make puff and variants share common mainboard.cEdward O'Callaghan
Here we consolidate some of the mainboard.c duplication between Puff and it's variants. Customizations can be done later via introducing a devicetree parameterisation. BUG=b:154071868 BRANCH=none TEST=none Change-Id: I75c2de7ae8efd544d800bc77e34e667c3afa4b01 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42672 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22cbmem: Remove IDs for TSEG and BERTMarshall Dawson
Remove the changes added in commit 80df052d3 "cbmem: Add IDs for TSEG and BERT table data" No platform uses either ID. TSEG in cbmem is incompatible with stage cache. BERT reserved data in cbmem is unusable in Linux. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I5501424bfeb38d5ff5432678df9e08b4c16258f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42532 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22soc/amd/picasso: Set BERT_SIZE to 0 when no table generatedMarshall Dawson
BUG=b:136987699 TEST=Verify no region reserved when CONFIG_ACPI_BERT=n Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I95d511e454e7f2998e46e14112eea5e8b09d59b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-22soc/amd/picasso: Convert BERT reserved region from cbmemMarshall Dawson
Picasso's BERT region should not have been moved to cbmem in commit 901cb9c "soc/amd/picasso: Move BERT region to cbmem". This causes an error of "APEI: Can not request [] for APEI BERT registers. FSP has been modified to set aside a requested region size for BERT, simiar to TSEG. Remove the cbmem reservation and locate the region by searching for the HOB. BUG=b:136987699 TEST=Check that BERT is allocated Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I20e99390141986913dd45c2074aa184e992c8ebb Reviewed-on: https://review.coreboot.org/c/coreboot/+/42530 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22src/mainboard: Remove unused include 'sandybridge.h'Elyes HAOUAS
Change-Id: I9356a56c34d1c6746cf8acfe931386ffed58ba74 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-22mb/amd/mandolin/hda_verb: use AZALIA_RESET and AZALIA_PIN_CFG macrosFelix Held
TEST=Doesn't change the resulting binary for BUILD_TIMELESS=1. Change-Id: I9fccc53c3d56116027e28a9eec6ec27202017a79 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-22sb/intel/i82801ix/fadt.c: Use acpi.h definitionsAngel Pons
Tested with BUILD_TIMELESS=1, Roda RK9 remains identical. Change-Id: I284eec23a8804f7bb18d2ef493c1200c197c109e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-22sb/intel/i82801{ix,jx}/hdaudio.c: Use `Azalia` in printkAngel Pons
For some reason, one printk statement begins with `HD Audio` instead of the more common `Azalia`. Change the different prefix for consistency. Change-Id: Ia79e340f331b9186cc09b04f925ff9d94204955e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-06-22sb/intel/i82801{gx,ix,jx}/hdaudio.c: Drop unused typedefAngel Pons
Tested with BUILD_TIMELESS=1, Roda RK9 does not change. Change-Id: I9967d625a8e6d2e1063b9b38965d81a466738964 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-06-22sb/intel/i82801jx/hdaudio.c: Align with i82801ixAngel Pons
The code is pretty much the same, only differing in a comment and a printk statement. Change-Id: Ic404ef466636fc05c2baa70aad8a39bb1b458d42 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-22sb/intel/i82801ix/hdaudio.c: Clean up cosmeticsAngel Pons
Reflow some comments and add spaces around an operator. Tested with BUILD_TIMELESS=1, Roda RK9 does not change. Change-Id: I655d74ecbefa664d79b1af805f92cbcf877a43ac Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-22sb/intel/i82801ix/early_init.c: Reorder functionsAngel Pons
Both i82801gx and i82801jx start with the LPC setup function. For some reason this isn't reproducible, but it should not effect functionality. Change-Id: I9d26a151757d60e56ed70181ff7aef48e229d322 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-22sb/intel/i82801ix: Rename i82801ix_lpc_decode()Angel Pons
For consistency with other Intel southbridges, we rename this function to `i82801ix_lpc_setup`. Tested with BUILD_TIMELESS=1, Roda RK9 does not change. Change-Id: Id8b3bcc9174277e085868866a1b5d90b5c51201a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-22sb/intel/i82801{ix,jx}: Correct include guardsAngel Pons
These southbridges are not i82801gx. Tested with BUILD_TIMELESS=1, Roda RK9 does not change. Change-Id: I6b4c7bc11bcb668adb0aae463defea982cf9059c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-06-22vc/amd/fsp/picasso: Sync UPD and GUID filesMarshall Dawson
Update to the latest auto-generated UPD files. Add the GUID for the BERT HOB now being reported. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ia01f626bc85696483173b567bb4f06d308832a91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42529 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22mb/google/volteer/variants/terrador: Enable Cmd MirrorDavid Wu
Enable CmdMirror for Terrador to achieve optimum routing from SoC to DRAMs BUG=b:156435028 BRANCH=none TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I0db9fff0dddf35c99a6cb2a90d40886ed8e18686 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-22soc/intel/tigerlake: Add CmdMirror option in chip.hDavid Wu
Provide CmdMirror option in chip.h so that it can control CmdMirror FSP UPD via dev tree. BUG=b:156435028 BRANCH=none TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Idae9fa439f077f8f3fb16fe74c2f263c008cd5f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42276 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22mb/emulation/qemu-i440fx,q35: Fix comment stylePaul Menzel
The comment fits in 96 characters, so do it, also getting rid of the unwanted multi-line comment style. Add a dot/period to the end of the sentence. Change-Id: I7b5c7ea5da00d649aa06361e0e0cf2431874a6ec Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-22soc/intel/xeon_sp/cpx: rename xeon_sp_get_cpu_count()Jonathan Zhang
Rename function from xeon_sp_get_cpu_count() to xeon_sp_get_socket_count(). This function returns CPU socket count, by getting it from the field named as numCpus in FSP HOB. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Change-Id: Ic96bdf4ab042ac15d43f9b636185627c63fbf8a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42439 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22spi/winbond: Simplify status reg union typesDaniel Gröber
Having speparate types for the status register with three and four block protection bits respectively doesn't really make sense, it's the same size either way just a different representation, so one union type will do. This allows us to de-duplicate the status register read in winbond_get_write_protection as well as removing another layer of union in 'struct status_regs'. Change-Id: Ie99b98fb6762c8d84d685b110cfc2fd5458b702e Signed-off-by: Daniel Gröber <dxld@darkboxed.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42111 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22lockdown: Add hint for how to check for lockdown support in boot logDaniel Gröber
Change-Id: Iaceb2e82f900e52efcce702486e18d0483665640 Signed-off-by: Daniel Gröber <dxld@darkboxed.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41749 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22lockdown: Add Kconfigs for SPI media protection modeDaniel Gröber
SPI_WRITE_PROTECTION_REBOOT seems to be a Winbond thing, other vendors such as Macronix only support permanent protection but conditional on the WP# pin state. Change-Id: Iba7c1229c82c86e1303d74c7bc8f89662b5bb58c Signed-off-by: Daniel Gröber <dxld@darkboxed.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41747 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22mb/google/volteer/variants/volteer: clean up gpio.cNick Vaccaro
Remove an unneccessary comment and group the variant_early_gpio_table together based on GPIO group. Changed static variable name gpio_table to override_gpio_table to be more descriptive. BUG=none TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer to kernel. Change-Id: Iabe810df1e5a3df35e3543ab81b9fdb6f76c223a Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42577 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22mb/google/volteer: move volteer devices to overridetree.cbNick Vaccaro
Move the following volteer-specific devices from baseboard's devicetree.cb into volteer's overridetree.cb file: - Goodix Touchscreen - ELAN Touchscreen - ELAN Touchpad - SAR0 Proximity Sensor Adjust the other variant's overridetree.cb files to correspond to the changes made to the baseboard's devicetree.cb in this change. BUG=b:159241303, b:154646959 TEST='emerge-volteer coreboot chromeos-bootimage', flash and boot volteer to kernel and verify that the trackpad works. Change-Id: I30f8266ec87a7cde293c84d3e687d133207b8d59 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-22mb/google/volteer: update fw_config definitionNick Vaccaro
Update fw_config definition in devicetree.cb to match current definition for volteer. BUG=b:159157584 TEST=none Change-Id: I761893818231880d86fd13cfa61319157d06a7d5 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42331 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22mb/google/volteer: Disable D3Cold for TCSS along with pass through modeJohn Zhao
The pass through mode (SW CM) RTD3 is not supported until QS platform. D3Cold is needed to be disabled along with upstream TBT firmware signed_TGL_HR_4C_A0_rev6_pre4_SW_CM_PM_support_ENG_VER_perst_check_fix. This temporary patch will need to be reverted once PM RTD3 support is validated on QS platform. BUG=b:159050315 TEST=Verfiy PM S0ix along with upstream TBT firmware. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I98ed991e4185abf1f3168e33b099e0e97c9075f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42504 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Divya Sasidharan <divya.s.sasidharan@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22mb/google/volteer: Override power limits with SKU-specific limitsTim Wawrzynczak
Using guidance from Intel, a new set of power limits (PL1, PL2 & PL4) are available for TGL-U. They are dependent upon the SKU of the CPU that the mainboard is running on. Volteer is updated here to use these new limits. To accomplish this, the SoC chip config's power_limits_config member was expanded to an array, which can be indexed by POWER_LIMITS_*_CORE macros. Just before power limits are applied, the correct set of them is chosen from the array based on System Agent PCI ID. Therefore, a TGL board should have two sets of power limits available in the devicetree. BUG=b:152639350 TEST=On a Volteer SKU4 (4-core), verified the following console output: CPU PL1 = 15 Watts CPU PL2 = 60 Watts CPU PL4 = 105 Watts Change-Id: I18a66fc3aacbb3ab594b2e3d6e2a4ad84c10d8f0 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-06-22amd/picasso/acpi: Add power resources for I2C and UARTRaul E Rangel
This allows the kernel to runtime suspend these devices and properly shut them down. If a tty is not used, the kernel will disable the device. I omitted UART0 because the PSP will not power the controller before accessing it. This causes PSP boot failures. See b/158772504. We also can't enable UART0 D3 until we stop using the mmio kernel command line `console=uart,mmio32,0xfedc9000`. The kernel will suspend the UART controller before it notices that the mmio address matches ttyS0. This causes the kernel to fail writing to the UART. So we need to move over to `console=ttyS0`. BUG=b:153001807, b:157617092, b:157858890, b:158772504 TEST=Boot trembyle and see I2C devices entering and exiting D3. * See the UART devices entering D3 * Made sure the i2c peripherals were still functional. * Ran suspend stress test for 40+ iterations. [ 0.349094] power-0362 __acpi_power_on : Power resource [FUR1] turned on [ 0.350627] power-0362 __acpi_power_on : Power resource [FUR2] turned on [ 0.352094] power-0362 __acpi_power_on : Power resource [FUR3] turned on [ 0.353626] power-0362 __acpi_power_on : Power resource [I2C2] turned on [ 0.376980] power-0362 __acpi_power_on : Power resource [PRIC] turned on [ 0.399997] power-0362 __acpi_power_on : Power resource [PRIC] turned on [ 0.401953] power-0362 __acpi_power_on : Power resource [I2C3] turned on [ 0.403460] power-0362 __acpi_power_on : Power resource [I2C4] turned on [ 0.483646] power-0418 __acpi_power_off : Power resource [I2C4] turned off [ 1.028404] power-0418 __acpi_power_off : Power resource [I2C3] turned off [ 1.448426] power-0418 __acpi_power_off : Power resource [I2C2] turned off [ 5.308094] power-0418 __acpi_power_off : Power resource [FUR1] turned off [ 5.340833] power-0418 __acpi_power_off : Power resource [FUR2] turned off [ 5.382041] power-0418 __acpi_power_off : Power resource [FUR3] turned off [ 5.423861] power-0362 __acpi_power_on : Power resource [I2C3] turned on [ 6.698225] power-0362 __acpi_power_on : Power resource [I2C2] turned on [ 6.856573] power-0418 __acpi_power_off : Power resource [I2C3] turned off [ 8.246970] power-0418 __acpi_power_off : Power resource [I2C2] turned off Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I04c4a729d4cb9772ab78586fdbb695b450cc1600 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-21 22:16:20 +0000