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According to the specification the register offset must be 0x71 instead
of 0x70.
Change-Id: Icf69ffc701a42a31a4545ce53c13e2c2554863e1
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Drop DRAMT write as it's only rewriting the power on default.
PMCR write is required. Update comment on its purpose and move to
end of sdram_enable().
Change-Id: I62e8b2531f0f297ffb7db440db89ffa65771b7d5
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I27b2fcf6fea18e03dddb015eb017acc5db1db540
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Build broke with CONFIG_DEBUG_RAM_SETUP enabled after commit 3f882faf
(intel/i440bx,i82371: Remove wrapper spd_read_byte()).
This is the fix.
Change-Id: Ib83885fc50c8fab61ced5ff18f22aa4655c5aaab
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The bits cleared by this have to do with dGPU power, which this
board lacks.
TESTED: x201 still boots.
Change-Id: I441743f76afc7bbbee930a1c8116035e85d94e52
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36911
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch updates SA DRAM registers bit definitions as per
SKL datasheet vol 2, doc 332688.
TEST=Build and boot EVE and Soraka to OS.
Change-Id: Ia32723444c044572fbcecce151d89e739e570b3b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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TEST=Build and boot EVE and Soraka to OS.
Change-Id: Ic765dc2a7a522872ee991e47e3608f60a0e6411a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38513
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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As per PC client TPM specification, the TPM description contains the
base address of the TIS interface 0xfed40000 and the size of
the MMIO area is 20KB (0x5000). Hence ACPI used to reserve those fixed
system memory from getting used by OS.
Platform with TPM_CR50 doesn't require fixed SoC mapped memory hence
additional reservation might not required.
TEST=Build and boot EVE and Soraka to OS.
Change-Id: Id02a2659ce42f705180370000df89d4f6b64afce
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38512
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add IPU ACPI object for Camera ACPI.
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I8c1ca9c053f0c8ef8d7c027c317c7af74d5f0f8c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Optane memory module shows up as 2 NVMe devices in x2 config - NVMe storage
device and NVMe Optane memory. Storage device uses rp9 and optane memory
uses rp11. This patch enables rp11. Please note that these two share clk pins.
This is also dependent on pciecontroller3 config to be set as 2x2 instead of
1x4 in fit configuration in IFWI.
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board from Optane and check 2 NVMe devices
from lspci
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ic81244bebac78102af7ba6308ab64b18c886f839
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board from NVMe
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I14997e0a7d03bf1a97d115cbf0a7ad2603ef9953
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38285
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update FSP header files for Tiger Lake platform version 2457.
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I47574844a8b5fd888e8e75ed2f60f6df465b33ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
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This patch adds ASL methods like GRXS, GTXS, STXS and CTXS
which are used to get, set and clear gpio values. We use
ASL 2.0 syntax here for gpio.asl.
BUG=b:144680462
BRANCH=none
TEST=Build and boot tigerlake rvp board
Change-Id: I17e75ff2a7cb67e94669059a1ed9d73a720ebcb1
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38442
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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GPIOs are divided into different communities. Each community
consists of one or more GPIO groups. We need to configure the
groups in coreboot so that they are mapped properly.
GPIO comuinities in coreboot should match with the kernel gpio
communities also. Kernel reads the ASL file from coreboot. This
patch adds the proper community mapping in ASL code to match with
kernel code. In gpio_soc_defs.c file we are indexing the groups
correctly. In gpio.h file we define all the gpio devices as kernel
populates sysfs with separate gpio device for each community. This
patch is created based on Intel Tiger Lake Processor PCH Datasheet
with Document number:575857 and Chapter number:27.
BUG=b:144680462
BRANCH=none
TEST=Build and boot tigerlake rvp board. In /sys/kernel/debug/pinctrl
verify INTC34C5:0<1-3> listing all the pins for each community.
e.g., #cat /sys/kernel/debug/pinctrl/INT34C5:00/pins should list
all the community 0 pins.
Change-Id: I40c386db060d84c1b7fba9c587f960d6a92f84ba
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
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Having a working board reset is certainly better when you're running
vboot (because otherwise you'll hang when transitioning into recovery
mode), but I don't think it should be strictly required, since it's
still somewhat usable without. This is particularly important for
certain test platforms that don't have a good way to reset but might
still be useful for vboot testing/prototyping.
Change-Id: Ia765f54b6e2e176e2d54478fb1e0839d8cab9849
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38417
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TEST=Build and boot EVE and Soraka to OS.
Change-Id: Ic7840ce264393b4a955f17b16f5e0f556e34a776
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38511
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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SoC handles PCI IRQs programming inside PCH related ASL.
TEST=Build and boot EVE and Soraka to OS.
Change-Id: If95101193fa1b528dc64f57c0fc12f13f16d82b4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Remove fixed IccMax values for U22 CPU.
IccMax will be selected by CPU SKU.
BUG=b:148110226
BRANCH=None
TEST=build coreboot and fsp with enabled fw_debug.
Flashed to device and checked IccMax[1].
Change-Id: Ifcd31ad5b608ce599d4294a6522fdda022f8a177
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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BUG=N/A
TEST=build
Change-Id: Ifb45bc1f7f4d3744124d6797fb4c791fd5f227ca
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Add Provides ACPI_GPIO_IRQ_LEVEL_[LOW|HIGH]_WAKE versions to allow board to define a gpio irq as wake capable.
Change-Id: I42f5084c5f0f5da0a4b39df77707b2f158bcc03d
Signed-off-by: Alex Levin <levinale@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Enable both SATA ports for TGLRVP.
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board with SATA memory
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I9f35682982a6c06522e58b0bbd7162ff02c37f32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38505
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure SATA FSP UPD according to mainboard design.
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board with SATA memory
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I9350d71d76cd3d449fd959b5398d5ac653bc459e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38504
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch updates system agent related registers bit definitions
as per EDS.
For example:
As per CNL/ICL EDS MCHBAR register base is between bit 16-38
but coreboot programming was not aligned with EDS previously.
CNL EDS doc number: 566216
Also provide provision to program 64bit values as per SA EDS definitions
TEST=Dump MCHBAR in coreboot and ASL shows same 32 bit value.
Change-Id: I37340408fe89c94ce81953c751c8d7e22bc81a42
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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1. Add a TEMP_SENSOR3
2. Update DFPS (fan performance state) table with values received
from thermal team
3. Update PL1 override to 15W
4. Update PL2 override to 51W
BRANCH=hatch
BUG=b:147792204
TEST=build and verify by thermal team
Change-Id: I21c17c09a097c963f4dd1b7d5f8212c83a639dc3
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38025
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT for tigerlake.
BUG=b:142961277, b:145494156
BRANCH=none
TEST=none
Change-Id: I1f785f410982f7d7598942f9b12196851e77c240
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37629
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This CL allows MKBP events from the EC to wake the system from suspend
states.
BUG=b:144122000
BRANCH=firmware-hatch-12672.B
TEST=Verify that MKBP events generated from EC will wake the system
from S0ix.
Change-Id: I8a0d2c7ed89fa1ea937a08c3082cc5d3e782efff
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The firmware configuration (fw_config) field is store in the CBI EEPROM
and it should be used to make firmware customization instead of
sku/variant id.
BUG=b:145519081
TEST=builds
Change-Id: I790998a29e724ecdff8876cca072267537b7cea6
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Copy ec_commands.h directly from Chromium OS EC repo at sha e57217a250.
This is needed for the FW_CONFIG CBI field definition.
Change-Id: Id010721033ebe32ac9c9482d666cf790442a26ee
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add initial fsp upd settings for TGL, both romstage and ramstage upd's to
support basic build and boot of TGL RVP.
- Add Silicon upd settings which includes
* Serial IO/UART settings
* Graphics settings
* USB2/USB3 settings
- Add Romstage upd settings which includes
* Pcie Root port settings
* IGD initialization
* Hyper Threading settings
* SMBus controller settings
* Debug probe settings
BUG=none
BRANCH=none
TEST=Build and boot Tigerlake rvp board
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I16df66451fd3a681df1222d283d97dd6bdaff0e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37960
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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GPIOs are divided into different communities. Each community
consists of one or more GPIO groups. We need to configure the
groups from coreboot so that they are mapped properly.
GPIO communities should be properly configured in GPIO_CFG and
MISCCFG registers. GPP_* defines in gpio_soc_defs.h are configured
in GPIO_CFG register while the PMC_GPP_* in pmc.h are used to
configure the MISCCFG registers.
BUG=b:144680462
BRANCH=none
TEST=Build and boot tigerlake rvp board. Verified that after
setting the gpe from devicetree the GPP_EN register for
that community gets updated setting that specific bit.
From the iotools i checked that GPE_EN register for that
community is updated with that specific bit set to 1.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I585100375feee39b5a9105bdf6d9f5ca3a5bb2fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Add Elkhartlake CPU, SA and PCH IDs.
EHL PCH is code named as MCC.
Also add a MCH ID (JSL_EHL) which is shared by both JSL and EHL SKUs.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I03f15832143bcc3095a3936c65fbc30a95e7f0f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38489
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update interrupt header and interrupt mapping per Intel Silcon reference code.
Need to match pci_irqs.asl with FSP setting which followed by PCH BIOS spec.
Reference
PCH BIOS spec#613495
https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/master/ClientOneSiliconPkg
/IpBlock/Itss/LibraryPrivate/PeiItssPolicyLib/PeiItssPolicyLibVer2.c
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Iffc4efad4d0aa55fc0de88d7fe32c0356dbc3c60
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38258
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Align the fbg1701 sleepstates implementation with monolith.
BUG=N/A
TEST=build
Change-Id: I3a715781bf51da41d6954463ad38ed94b0dfd217
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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The monolith board doesn't support the S3 and S4 states because of the
watchdog and failover mechanisms.
Remove S3 and S4 from the available sleepstates.
BUG=N/A
TEST=build
Change-Id: I01f67d8bb3f9e45caef748caca91eeb6859d7393
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Some boards don't support S3 or S4. The S4 state can't be removed from
the available sleep states.
Add a config item that allows removal of the S4 state from the list of
available sleep states. The S4 state can be removed by selecting the
item on board level.
For the AMD chipsets the SSFG mask is updated to remove the S4 state.
BUG=N/A
TEST=build
Change-Id: Id802c4cc40308ddf39e99e7f226d55e0e020f0c9
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38431
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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According to VRTT report, add ac/dc loadline configuations in puff device
tree.
BUG=b:147206535
BRANCH=None
TEST=build coreboot and fsp with enabled fw_debug.
Flashed to puff and checked the log.
All ac/dc loadline configs were set correctly.
Change-Id: Ia806de23a1fefcaac3ce9a462a8a04eee5eabcae
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Jinlon will use EC to control fan, so remove DPTF fan control.
BUG=b:141259174
TEST=emerge-hatch coreboot chromeos-bootimage
Change-Id: I8ada4fe72eee260fecf45d00510da8b91e3f10a4
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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ONBOARD_VGA_IS_PRIMARY is selected if board selects
DRIVERS_LENOVO_HYBRID_GRAPHICS.
See commit 35abe73e with Change-Id:
I6594fbb957c9a8135fe670d38b5755adf29d2dff ("mb/lenovo/t430: Fix Dual
Graphics").
Change-Id: I39687e5cd34979fd4318978f5aa46ac6cdf721e8
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I6c7bbb89af88cce1a53c21a4b4d8bc1c284e1cb2
Signed-off-by: Ivan Vatlin <jenrus@tuta.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Use information provided by AGESA to fill the SMBIOS memory tables.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I45bb2fc36cf0c01670e9fc8559d3a6183ea271f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Following the example of change CB:37737 (ee8f969).
Switching was done by moving a SIO configuration and
the clocks setup from 'romstage.c' to 'bootblock.c'.
Tested-by: Damien Zammit <damien@zamaudio.com>
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Change-Id: I2e710ac61843c09a055523c7971e4c05bae56a37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Fix devicetree to advertise the correct USB names and types
in the generated ASL.
BUG=b:146437991
BRANCH=none
TEST=booted and inspected the reported generated ASL.
Change-Id: I133b4db444f9a5f0a36d8e976ae490f24cf307d8
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Add SMMSTORE support for saving EFI NVRAM variables in
conjuction with Tianocore payload.
Test: none, as this duplicates tested functionality in
amd/stoneyridge.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Id05b33edf949611c3f9eac94e7b63a4266c6c4d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ibb37c2d99c1a95b1d37bec784c98e636da4836d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38470
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Only the ACPI code needs to be extended, as smihandler.c already
supported it. The _Q50 Method is just _Q18 with changed name.
On Linux, pressing the undock button does nothing, so the only safe
way to undock is to press Fn+F9. With this patch, when the undock
button is pressed, the green LED lights up, and undocking is safe.
Change-Id: Iaaecad031bb1f39dd1a778d0c8eaea6bce9e0f57
Signed-off-by: Maciej Matuszczyk <maccraft123mc@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38446
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Mimoja <coreboot@mimoja.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add Nuvoton NCT5104D GPIO IO VLDN and define an IO base address
unused by any peripheral for GPIO use.
Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I034c5d0169b8d97eac97a20c92c22816fd674f79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Now, Super I/O GPIOs can also be controlled directly through
access to I/O registers. VLDN 108 and specific I/O port from a range
<100h; ff8h> may be enabled in mainboard devicetree.
Change-Id: I4ce99bb44e6f5db684170f4190bdc38a944849f6
Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35849
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The mainboard ASL code contained a power button definition. This is not
required as the system uses the standard ACPI power button.
Remove the PWRB device from ASL.
BUG=N/A
TEST=tested using fwts on a facebook monolith.
Found-by: fwts 19.12.00
Change-Id: I25a842539ee2e8febc8a1ae88843a71ccb4ee68e
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38133
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The mainboard ASL code contained a power button definition. This is not
required as the system uses the standard ACPI power button.
Remove the PWRB device from ASL.
BUG=N/A
TEST=build
Found-by: fwts 19.12.00
Change-Id: I4fac1411fd99475551bc970818759649f80b3f0e
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38134
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add SMMSTORE support for saving EFI NVRAM variables in
conjunction with Tianocore payload.
Test: build/boot several google/kahlee variants, test
manipulation and persistence of Tianocore bootorder variables.
Change-Id: Ida604a44d1fa5288e96dbe05de1f847e597cc95d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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