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2018-09-07fsp_broadwell_de: enable spi consoleOkash Khawaja
this enables spi console for wedge100s with broadwell_de. the console size is 64kb. enabling spi console in `board.fmd` enables code which calls into `timer_monotonic_get` (from `spi_flash_cmd_poll_bit`) and `udelay` (from `ich_status_poll`). this patch selects `TSC_CONSTANT_RATE` in fsp_broadwell_de's Kconfig to satisfy that. Change-Id: Ib925c5aee88b65c46a81534405c364dd5649f8e8 Signed-off-by: Okash Khawaja <okash.khawaja@gmail.com> Reviewed-on: https://review.coreboot.org/28528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-09-06mb/google/octopus: Configure H1 interrupt pad using Rx level configFurquan Shaikh
This change configures GPIO_63 (which is used for H1 interrupts) as Rx Level. This ensures that the signal gets passed on to the next logic state as is and the APIC entry can be configured to trigger interrupt on level or edge as per the kernel driver expectation. TEST=Verified that no H1 interrupt timeouts are seen with 100 iterations of warm and 100 iterations of cold reboot. Change-Id: I7aac30300a4251d9b40276dcca7ebc6a6d814c40 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-06qemu-q35: Use the TSC for udelayMichael van der Westhuizen
Use the TSC for delays on q35, ensuring that the TSC delay code is included in the correct stages when selected. Tested on qemu-35 and wedge-100s (for no regressions). Change-Id: I3f8368509807974bfcf2a0fcff7a4aa21adf47ed Signed-off-by: Michael van der Westhuizen <rmikey@fb.com> Reviewed-on: https://review.coreboot.org/28526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-09-06wedge100s: enable mrc cache in fmapOkash Khawaja
this enables mrc cache in fmap for wedge100s and always enable it in Kconfig. Change-Id: I27cd236f67a6500b40fc3eb731397d408402f041 Signed-off-by: Okash Khawaja <okash.khawaja@gmail.com> Reviewed-on: https://review.coreboot.org/28527 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-06mainboard/google/poppy/variants/rammus: Enable GSPI clock for bus 0.kane_chen
On rammus, system halt was observed because of gspi clk value being set to 0. Log info from serial coreboot: FMAP: area RW_NVRAM found @ 9fa000 (24576 bytes) SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000 VBNV: Restore from flash failed ASSERTION ERROR: file 'src/soc/intel/common/block/gspi/gspi.c', line 443 gspi.c 442 443 assert(gspi_clk_mhz != 0); 444 assert(ref_clk_mhz != 0); 445 return (DIV_ROUND_UP(ref_clk_mhz, gspi_clk_mhz) - 1) & SSCR0_SCR_MASK; BUG=none BRANCH=master TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure system boots up. Change-Id: Ibe3937902901b2cdc1a196415c08fabb0f3155f2 Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28405 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-06soc/intel/cannonlake: Fix Coverity Scan reportLijian Zhao
Fix uninitialized variable OnModuleSpd, init bool with false first. BUG=CID 1395330, 1395331 TEST=N/A Change-Id: I050287370f7321ff9905937304bb3cc7f20d8c6a Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-06mediatek: Refactor memory test code among similar SoCsTristan Shieh
Refactor memory test code which will be reused among similar SoCs. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: I800aa9a73f0b4588f46a98c964e2794bdf04f09d Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/28436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com> Reviewed-by: Julius Werner <jwerner@google.com>
2018-09-06mb/google/poppy/variants/nocturne: Enable DMIC CLK0/DATA0Sathyanarayana Nujella
DMIC's are now connected to DMIC_CLK0/DMIC_DATA0. So, enable the pins accordingly. BUG=b:113744731,b:111106010 BRANCH=none TEST='emerge-nocturne coreboot chromeos-bootimage' builds the image Change-Id: I48cace3c6099a2853fcb377c695a5e325094baf6 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Signed-off-by: Harsha Priya <harshapriya.n@intel.com> Reviewed-on: https://review.coreboot.org/28433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-06soc/intel/common: Add function to set BILD bit in RTCRizwan Qureshi
Add a function to set the Bios Interface Lock Down bit (bit 31) in RTC Configuration register (0x3400). This bit when set prevents the top swap enable bit (bit 0) in the RTC BUC register (0x3414) from being changed. Change-Id: Iacaeeb0d6cabcf0c2c46a58948457ab832351476 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/28057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-06acpi/gnvs: delay setting chromeos_apci_t.vdat until depthchargeJoel Kitching
Standardize on using vboot_handoff data structure for transferring data between coreboot and depthcharge. chromeos_acpi_t.vdat is undefined until set in depthcharge. BUG=b:112288216 TEST=compile and run on eve CQ-DEPEND=CL:1198814 Change-Id: Iccc021334d3c6f0145dffd5ca05beb9e430378a9 Signed-off-by: Joel Kitching <kitching@gmail.com> Reviewed-on: https://review.coreboot.org/28407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-06chromeos/gnvs: remove function and naming cleanupJoel Kitching
- Remove unused acpi_get_chromeos_acpi_info (see CB:28190) - Make function naming in gnvs.h consistent (start with "chromeos_") BUG=b:112288216 TEST=compile and run on eve Change-Id: I5b0066bc311b0ea995fa30bca1cd9235dc9b7d1b Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/28406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-06x86/acpi: Add APEI definitionsMarshall Dawson
Add ACPI Platform Error Interfaces definitions that will be used for building a BERT table region in a subsequent patch. Two tables are defined: the Generic Error Status Block, Generic Error Data Entry. For reference, see the ACPI specification 6.2-A tables 381 and 382. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: Ib9f4e506080285a7c3de6a223632c6f70933e66c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-06src/include: Add CPER definitionsMarshall Dawson
Add definitions from the UEFI appendix on Common Platform Error Record (appx. N in revision 2.7-A). The structures and fields defined are the minimum required for generating ACPI Boot Error Record data in a subsequent patch. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: I74d8ec8311de749e891827747b84dce0e737aceb Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-06src/include: Introduce guid_t typeMarshall Dawson
Duplicate the guid_t and GUID_INIT framework from the Linux driver. Adapt it for coreboot, and create supporting copy and compare functions. Change-Id: Ia1cd7a1f0e0f900858830e1a6a7e2bbbe272fa30 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-06mb/google/poppy/variants/nautilus: Bump VCC_SA voltage offset 75mVSeunghwan Kim
Nautilus-Wifi with m3 AP got a halt issue during CTS test. Nautilus-Wifi was FCS with Celeron AP first and also its PCB/BOM was validated only with Celeron. Since Celeron deos not support turbo boost mode, its steady power demend and lower CPU frequency may not reflect the potential noise hidden inside the board. Bumping VCC_SA voltage offset 75mV confirmed works to mitigate the potential noise coupling to VCC_GT/SA, and we verified this change makes this issue go away on Nautilus-Wifi board. Nautilus-LTE doesn't show this issue, since it has 10L PCB, will have better grounding and less noise/ripple than 8L PCB. BUG=b:111417632 BRANCH=poppy TEST=Verified CTS test pass without an issue. Change-Id: Id13fcc36a5b6ed42620c66f57a7303f30bff1a50 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/28439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-06intel/fsp2_0: Add fsp2.1 shared stack feature supportAamir Bohra
FSP 2.1 implementation is adding features on top of fsp2_0. One such feature is a shared stack implementation that requires coreboot to allocate stack for fspm and then fsp uses the same stack as coreboot. This implementation adds support for shared stack feature. Change-Id: I6581111dbaddfa403eca14100577ccc8a05c4ec7 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/28358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-06mb/google/octopus: Enable TBMC deviceAmanda Huang
This change enables tablet mode ACPI device for all octopus boards. BUG=b:113348027 Change-Id: I69a5dd41cd0958b93f8eed338fed4b6ee77a178f Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28466 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-05mainboard/google/kahlee: Enable the BCLK bufferMartin Roth
Set GPIO135 high to enable audio through the BCLK buffer. BUG=b:113559558 TEST=None BRANCH=grunt Change-Id: I1dcecf5960d3c91e0c2165e7f8856ff423c06e8c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/28482 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-05nb/intel/x4x/gma.c: fix skipping of native graphics initStefan Tauner
CB:27984 (e6c8f7e) is supposed to skip over NGI if bit #1 in register GCC is set. However the check for x4x was wrongly checking if any bit of the whole register is set. Change-Id: I5000f5e771abb98f046e2ad19c1bee7dbc0743fc Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/28447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-09-05arch/x86/Makefile: include dependencies for romcc bootblockNico Huber
We already explicitly generated a dependencies file for the romcc bootblock. Though, as it has its own rule and isn't registered to any of our object-file classes, the dependencies file wasn't included automatically. Change-Id: I441cf229312dff82f377dcb594939fb85c441eed Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/28442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-05mb/intel/dg43gt/dsdt.asl: fix globalnvs.asl include pathStefan Tauner
Use ICH10's file instead of ICH7's. Change-Id: I02678179e8f1dbd9b9f7d6407383a7a6cad15011 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/28450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-09-05riscv: add entry assembly file for RAMSTAGEXiang Wang
RAMSTAGE will revoke CAR/scratchpad, so stack and exception handling needs to be moved to ddr memory. So add a assembly file to do this. Change-Id: I58aa6ff911f385180bad6e026d3c3eace846e37d Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/28384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-05mb/lenovo: Support dual graphics for xx20/xx30 ThinkPadsEvgeny Zinoviev
Add CMOS option that allows to use both integrated and discrete GPU. Tested on ThinkPad W530. Change-Id: I8842fef0fa1235eb91abf6b7e655ed4d8598adc7 Signed-off-by: Evgeny Zinoviev <me@ch1p.com> Reviewed-on: https://review.coreboot.org/28393 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-05riscv: add support to check machine length at runtimeXiang Wang
Highest two bits of misa can be used to check machine length. Add code to support this. Change-Id: I3bab301d38ea8aabf2c70437e179287814298b25 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/27770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-04mb/google/poppy/variants/rammus: add sku info into smbios tableZhuohao Lee
This patch adds the mainboard.c in order to support the sku id in smbios table where the sku id is queried from the eeprom via EC. BUG=b:113714761 BRANCH=master TEST=check the result of 'dmidecode' Change-Id: I3413784cca1ac10a2468d84f2d06c0e1d701fdcb Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/28426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-04riscv: add spin lock supportXiang Wang
Add spin lock support for riscv. Change-Id: I7e93fb8b35c4452f0fe3f7f4bcc6f7aa4e042451 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/27356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-04riscv: Add DEFINE_MPRV_READ_MXR to read execution-only pageXiang Wang
Must to set MXR, when needs to read the page which is execution-only. So make this change. Change-Id: I19519782fe791982a8fbd48ef33b5a92a3c48bfc Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/28394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-02drivers/intel/fsp1_1: Fix typoWim
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Change-Id: I9c6b063970fa328650de3f4402fe203305b5b760 Reviewed-on: https://review.coreboot.org/28373 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Wim Vervoorn Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-02riscv: separately define stack locations at different stagesXiang Wang
BOOTBLOCK/ROMSTAGE run in CAR/scratchpad. When RAMSTAGE begins execution will enable cache, then CAR will disappear. So the Stack will be separated. Change-Id: I37a0c1928052cabf61ba5c25b440363b75726782 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/28383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-09-02mb/lenovo: dGPU power handling on T430, T530Evgeny Zinoviev
Enable dGPU power handling on Lenovo ThinkPad T430, T530 via PMH7 register 0x50. Although there's no Thinker-1 chip on these models according to schematics, dGPU power control via PMH7 works the same as on T420/T520, so they can be considered Thinker-1-compatible. It can be tested from linux userspace using util/pmh7tool. To turn dGPU power off: pmh7tool -c 0x50 7 pmh7tool -c 0x50 3 To turn it on: pmh7tool -s 0x50 3 pmh7tool -s 0x50 7 To check whether it is on (bash): reg=0x$(pmh7tool -r 0x50) echo "$(( (( reg & 0x08 )) >> 3 ))" or just `pmh7tool -b 0x50 3` with https://review.coreboot.org/#/c/coreboot/+/28388/ Tested on ThinkPad W530. Change-Id: Ieab1a33b3c680c757cc0999660b5cb7e122474cc Signed-off-by: Evgeny Zinoviev <me@ch1p.com> Reviewed-on: https://review.coreboot.org/28392 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-02src/drivers/spi/tpm: Fix typo & capitalize TPM and IRQElyes HAOUAS
Change-Id: Ifb1e024821153865dd4a27a100f8a9c61151e0e1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-09-02mb/google/poppy/Kconfig: Fix missing device node /dev/tpm0 for H1Zhuohao Lee
This patch adds the DRIVERS_SPI_ACPI to enable the tpm device node. Without DRIVERS_SPI_ACPI, the kernel will popped out the below error: cr50-update[592]: Starting cr50 update cr50_get_name[595]: updater is /usr/sbin/gsctool -s cr50-update[609]: exit status: 3 cr50-update[613]: output: Could not open TPM: No such file or directory cr50_get_name[615]: board_id: '' board_flags: '0x', extension: 'prod' cr50-update[617]: hashing /opt/google/cr50/firmware/cr50.bin.prod cr50-update[678]: current state 3 in /var/cache/cr50.a3055efbc9.state cr50-update[682]: not running cr50-result[782]: Not running normal image. Skip setting Board ID trunksd[795]: TPM: Error opening tpm0 file descriptor at /dev/tpm0: No such file or directory BUG=none BRANCH=master TEST=/dev/tpm0 is created Change-Id: I35287c6c54299c2677c41fc830675570b9d45a94 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/28400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-02chromeec: PS2K node can't be under SIO nodeStefan Reinauer
Some operating systems won't find the keyboard if it is under the SIO node. BRANCH=none BUG=none TEST=Boot Windows, observe that keyboard is working Original-Signed-off-by: Stefan Reinauer <reinauer@google.com> Original-Change-Id: I76b1ca9bf9243ffa861bed9c356a45377e7f43ef Original-Reviewed-on: https://chromium-review.googlesource.com/895364 Change-Id: If99e15bef2173c44cecaa8fdeaa69381bd0e499a Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/28386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-02mainboard/google/kahlee/var/liara: Enable Synaptics touchpad deviceCrystal Lin
Enable Synaptics touchpad device for liara BUG=b:113309346 BRANCH=master TEST=Verify touchpad on liara works with this change Change-Id: Icdafe34a00fd55d5338fa07ffa304e48e7b85e7b Signed-off-by: Crystal Lin <crystal_lin@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-31google/cheza: Adjust FMAP to fit new requirementsJulius Werner
This patch overhauls the Cheza FMAP, removing some sections we don't seem to need (RW_CDT, the two RW_XBL_BUFFERs, and the second copy of RW_DDR_TRAINING), and adding new sections we're going to need soon or should have had anyway (RO_DDR_TRAINING, RO_FSG, RW_LEGACY). Make more use of implicit offsets and sizes, because we can and because it should make future adjustments easier. Change-Id: I0bd9e59e9cfa162c478c4bd1f048fcac61ad5062 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/28403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: T Michael Turney <mturney@codeaurora.org>
2018-08-31mb/google/kahlee/variants/liara: Update Audio/H1/TP i2c timingsChris Zhou
After adjustment on Liara Proto Audio: 399.2 KHz H1: 398.3 KHz TP: 399.0 KHz BUG=b:113319200 BRANCH=master TEST=emerge-grunt coreboot chromeos-bootimage measure by scope Change-Id: Ibba8c823ed8451a804cf731d49e7568a94ac7c6b Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-08-31siemens/mc_apl1: Correct the Tx signal from SATA interfaceMario Scheithauer
Because of an incorrect transmit voltage swing, the signal must be adjusted. The factor of slices for full swing level can be corrected via the High Speed I/O Transmit Control Register 3. Change-Id: I116802cd2a944658fc3022e948eba43cebe52bb4 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
2018-08-30mb/google/poppy/variants/nautilus: Set grip sensor thresholdSeunghwan Kim
Set threshold parameter for grip sensor STH9321 .ProxCtrl6: 75 .ProxCtrl7: 99 BUG=b:113303916 BRANCH=poppy TEST=Built and verified parameter passed to driver Change-Id: I8a410a23b5e3831fc8e90118b810fc2409a026eb Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/28381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Enrico Granata <egranata@chromium.org>
2018-08-30soc/intel/cannonlake: Fix comment errors for SMBUSLijian Zhao
On CannonLake PCH, SMBUS stays at Bus 0 Device 31 and Function 4, previous comment in southbridge.asl mention it as Function 3 that was a mistake. BUG=N/A TEST=N/A Change-Id: I29786457379809b6fcb592e1136ff612539e24dc Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-08-30riscv: update the definition of intptr_t/uintptr_tXiang Wang
These RISC-V ABIs defined by GCC : ilp32 ilp32d ilp32f lp64 lp64d lp64f. Through this we know that the length of the long's bit is equal to pointer. So update this code. This's more flexible. Change-Id: I16e1a2c12c6034df75dc360b65acb1b6affec49b Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/27768 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-30soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port()Richard Spiegel
Function pci_ehci_dbg_set_port() used NDA register DEBUGPORT_MISC_CONTROL, which was deprecated in favor of a public PCI register (though only the bits to enable debug port became public) 0x90. Therefore code needs to be updated. BUG=b:69231009 TEST=Build and boot grunt. Change-Id: Ibb25992729d984b8570712f91a03a7cd1e9b8643 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-30mb/google/octopus: Add missing IOstandy settings.Shamile Khan
Also removed internal pull ups for CX_PREQ_L and CX_PREQ_L signals as they have external pull ups. BUG=b:110654510 TEST=On Yorp Proto 2, flashed image and verified that it boots to OS. Checked Wake-on-Wifi works with both cnvi and pcie modules. Also executed a few suspend resume cycles. Change-Id: I0a76cd2a1481c828fc092aaf7e870a411624879c Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/28328 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-30soc/intel/cannonlake: Update PMC base address for CNP H and LPMaulik V Vaghela
PMC base address is different for CNP LP pch and CNP H pch. Added logic to determine PMC base addrress dynamically based on PCH ID. BUG=none BRANCH=none TEST=Boot Coffeelake U RVP board and check if PMC base address is determined correctly. Change-Id: I833395260e8fb631823bd03192a092df323250fa Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/27523 Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-30drivers/intel/gma: Fix OpRegion Mailbox3 backlight changeNico Huber
We should always update BCLP, no matter if the driver is ready yet to process the request. This way it will hold the current value when the driver initializes. Change-Id: I4b091d744f95da39abe542966f0a8589a187573b Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-30drivers/intel/gma: store uint8_t brightness values in mailbox3Alexander Couzens
The _BCM function requires a percentage value. While the brightness in mailbox3 requires a value in uint8_t. Meaning 255 = 100%. Previous implementation stored the percentage brightness value resulting in limiting the brightness to ~40% of it's maximum power. Only affects brightness control using mailbox3. Fixes: 6838aaebf9ec ("drvs/intel/gma/acpi: Add methods to use MBOX3") Change-Id: I290b5f5b2a8ee406e39e86d3e0de9997798d890d Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/28345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-29mainboard/google/kahlee: Enable EC firmware update screenMartin Roth
Grunt takes a few seconds to update the EC, so display a notification screen while that's happening. BUG=b:113286040 TEST=Boot Grunt with old EC firmware, see update screen Change-Id: I95fc4d3430bac66c09f57a4d34abde08752e5f0e Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/28374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-08-28lib/gpio.c: Validate num_gpioRichard Spiegel
In function _gpio_base3_value(), if num_gpio is 0 it'll cause the return of an undefined value, as no for loop will be executed. Assert that it's not 0. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: I2b6537900fa41ebbee0171959f3ce236d360bc80 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-28mb/google/octopus/variants/meep: Add weida touchscreen supportTony Huang
Add weida touchscreen support BUG=none BRANCH=master TEST=emerge-octopus coreboot, and verified that touchscreen works on meep. Change-Id: I4352322820237e4c2289410af6643e15109060a1 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-28soc/intel/cannonlake: Change LPDDR4 to MEMCFGLijian Zhao
Modify the previously SOC_CNL_LPDDR4_INIT to SOC_CNL_MEMCFG_INIT, to make the infrasturture to handle both LPDDR4 and DDR4 cases in the future. Consider the case of reading SPD from SMBus other than providing SPD pointer directly. BUG=N/A TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a" compiles successfully. Change-Id: I2f898147f67dd52b89cc3d9fc4e6b3854fa81f57 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28248 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-28acpi: Hide Chrome and coreboot specific devicesDavid Wu
Some ACPI interfaces introduced by Chrome or coreboot do not need drivers outside ChromeOS, for example Chrome EC or coreboot table; or will be probed by direct ACPI calls (instead of trying to find drivers by device IDs). These interfaces should be set to hidden so non-ChromeOS systems, for example Windows, won't have problem finding driver. Interfaces changed: - coreboot (BOOT0000), only used by Chrome OS / Linux kernel. - Chrome OS EC - Chrome OS EC PD - Chrome OS TBMC - Chrome OS RAMoops BUG=b:72200466 BRANCH=eve TEST=Boot into non-ChromeOS systems (for example Windows) and checked ACPI devices on UI. Change-Id: I9786cf9ee07b2c3f11509850604f2bfb3f3e710a Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1078211 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org> Tested-by: Hung-Te Lin <hungte@chromium.org> Trybot-Ready: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/28333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-03 21:52:27 +0000