summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2016-03-13northbridge/intel/i82810: Unify UDELAY selectionStefan Reinauer
Instead of manually including udelay_io.c in each romstage, select UDELAY_IO for all i810 boards in the chipset. Change-Id: Ifda7dcfdf37b6affce838ee96ca6382b2d4be8c3 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13784 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-12northbridge/intel/i82830: Unify UDELAY selectionStefan Reinauer
Instead of manually including udelay_io.c in each romstage, select UDELAY_IO for all i830 boards in the chipset. Change-Id: I0a63ddd3c5e43ea65f776385f54eceb6569751ac Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13783 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-12nb/amd/mct_ddr3: Consolidate duplicated codeTimothy Pearson
read_dqs_read_data_timing_registers() and read_read_dqs_timing_control_registers() served essentially the same function but had slightly different semantics, causing confusion and needlessly complex Family15h code. Consolidate both into read_dqs_read_data_timing_registers() and adjust surrounding code to match new semantics. Change-Id: I3be808db5d15ceec4c36d17582756b01425df09a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13994 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-12intel/skylake: Do not log wake source on resetDuncan Laurie
Skip logging a wake source when just resetting without coming from S3 or S5 state. This will prevent the occasional spurious event like PCI PME from showing up in the event log. BUG=chrome-os-partner:40635 BRANCH=glados TEST=run warm reboot teset on chell and ensure no wake source is logged Change-Id: If739034dc9022b37c90b9cc849a00c604383e70f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e7b5cc91adc3ed10df7cebd758cf8144216b9890 Original-Change-Id: I16f4f98df8c70fd25986a8b3644334c7209fd083 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/329846 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/331173 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13991 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-12intel/kunimitsu: Add SD card detect GPIO for SDHCI runtime PMmgarima
Enable SDHCI runtime PM since the display flicker due to SCC Power Gatingis addressed by 0x82 microcode BRANCH=glados BUG=chrome-os-partner:44663 TEST=Check if display flicker is gone when SCC is power-gated Change-Id: I7d1ac6e77a0d2e0a25414df6130862efcdae2c82 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b552120cfeff09d16cb79652b7de7296121858ba Original-Change-Id: Id82df475b262e8a91f0a93f8ddf80002b05c52f3 Original-Signed-off-by: Medha Garima <medha.garima@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/329651 Original-Commit-Ready: Jenny Tc <jenny.tc@intel.com> Original-Tested-by: Jenny Tc <jenny.tc@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/331172 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13990 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-12soc/intel/skylake: add option to statically clock gate 8254 timerAaron Durbin
In order to save more power by shutting down clocks add the ability to optionally clock gate the 8254 programmable interrupt timer. When doing this the platforms lose their "PC"-ness which certain payloads and OSes rely on such as SeaBIOS. BUG=chrome-os-partner:50214 BRANCH=glados TEST=Enabled option on chell. Noted the bit is set upon booting. Change-Id: I01f9d177bbde417d1efec2e16656a07dcebccbde Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 662575aa6a63656dedfa0ce1f202f5fac0205477 Original-Change-Id: Ib4a613cf1c28fc96c36fa2987c4b58a05beab178 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/329411 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/331171 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13985 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-12glados/chell: send an extra VR mailbox commandRizwan Qureshi
MPS IMVP8 VR is not entering PS4 in S0ix on Glados/Chell. The pcode has been updated since v76, and it requires an an extra VR mailbox command should be sent from coreboot to pcode. BUG=chrome-os-partner:48511 BRANCH=None TEST=Verified on glados, clean S0ix entry and exit. IMVP8 power is also pretty low CQ-DEPEND=CL:329393 Change-Id: Ia3ef4031269ac2d4557bba65de34c41a8d73f89a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3e66903c9017f9d3f45c97b68284f4e1058c03e2 Original-Change-Id: Ie9e370556bb35d02f6bfcfe5cb81dd977fceace1 Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/329480 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13983 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-12soc/intel/skylake: add option to enable VR specific mailbox cmdRizwan Qureshi
Adding an option to enable VR specific mailbox command. When set, an extra VR mailbox command specifically for the MPS IMPV8 VR will be sent. BUG=chrome-os-partner:48511 BRANCH=None TEST=Verified on glados, clean S0ix entry and exit. IMVP8 power is also pretty low Change-Id: Ia5a23cbb1eca8b463eb7c7c279b74635f1d6b9f7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c90a799b51fe35bf184dca6ffce59c89a60f9917 Original-Change-Id: Iffd3fbcb9a15611eefc942529e6cdafba859fb2e Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/329393 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13982 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-12vendorcode/intel/fsp/fsp1_1/skylake: update FspUpdVpd.h 1.9.0Aaron Durbin
The previous copy of FspUpdVpd.h was not up to date w.r.t. the FSP release being used for skylake boards. Fix that. BUG=chrome-os-partner:50863 BRANCH=None TEST=Built and booted on chell. Change-Id: I39896c04d35189b0fb2c903eefda4e5b7c57084a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fd647f354b8d9946b2217751cf1af845f29191b7 Original-Change-Id: I4ad131af6c563c9c33eb2b9207b13617ff24385d Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/331290 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/13984 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-12mediatek/mt8173: memlayout: Create DRAM DMA region for NOR flash DMA read.Yidi Lin
NOR flash has a hardware limitation that it can't access SRAM region after 4GB mode is enabled. We add a DRAM DMA region after 0x40000000 for NOR flash driver. So that the NOR flash driver can use this region after 4GB mode is enabled. BRANCH=none BUG=chormoe-os-partner:49229 TEST=Boot to kernel on rev4 w/ 2GB ram and rev3 w/ 4GB ram. And check /proc/meminfo. Change-Id: I4a86f0028b26509589ec8d09e2d077920446ece1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: dc61ec55187959101a9e891fe5e93928e9b8176e Original-Change-Id: Ifedc9e2dfba5d294297b3a28134997ac1dd38f94 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/327962 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/331177 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13989 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12mediatek/mt8173: detect sdram size at runtimeYidi Lin
Remove DRAM_SIZE_MB Kconfig setting and use sdram_size_mb() to detect the DRAM size at runtime. BUG=chrome-os-partner:49427 BRANCH=none TEST=Boot to kernel Change-Id: I0c3245db73335fb4f1c89c1debde715fc96ecba7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 00f6f2bbed0e7d23181337b9274191b31e73e223 Original-Change-Id: I409163fe527e966c184f28d7d9bbc809ae2308ed Original-Signed-off-by: PH Hsu <ph.hsu@mediatek.com> Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/327961 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/331176 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13988 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12mediatek/mt8173: mmu: update mmu range before DRAM is initialized.Yidi Lin
The DRAM size can not be determined before DRAM is initialized. Since mt8173 only support 2GB and 4GB DRAM models. We map 0x0 to the end of 2GB DRAM address before DRAM is initialized. BRANCH=none BUG=none TEST=boot to kernel Change-Id: I27a00106b0aa91c3dacfcd2bcd9208f08b108dc5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9720e67c86f0d37a08f7c32e900996c75d60288a Original-Change-Id: I87d9c6ac11486decde102b7821f550c2f1a51f1c Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/327960 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/331175 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13987 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12Add a driver for the parade ps8640Jitao Shi
BRANCH=none BUG=none TEST=none Change-Id: Icf397ce2ffdaed5048367daf2086c067984fea0a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b5a88793ccfc46af196300791a300be67b70f5b1 Original-Change-Id: I75adf2688c9c8b9a2338f7dee5d0ac10e7181529 Original-Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/321056 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13981 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12mediatek/mt8173: pll: raising the CPU core frequencyYidi Lin
Runs the LITTLE core at highest freqency to speed up the boot time. Set Vproc to 1.125V and set the freqency to 1.6Ghz for backward compatibility. (The highest frequency for the IC before E3 is 1.6Ghz.) BRANCH=none BUG=chrome-os-partner:47422 TEST=flash the bootloader and measure the boottime by cbmem result Change-Id: Id0b906bf34ac534667eb6e8f576e30942ceb923e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5fc38548d158158f07cded8cfc8ea5a0a7952161 Original-Change-Id: I62af26c13d98211974243100c581abcb5408fd63 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/324685 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13980 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12mediatek/mt8173: add NOR DMA readBayi Cheng
BRANCH=none BUG=none TEST=boot oak to kernel on rev2 Change-Id: I368fcac1cf5e2261d00a34882a7341733ebd0732 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6ea0407f7273bc88613bc23a6fc4c41f9cca1adb Original-Change-Id: Ic422e7265fdd35c573d8cd44280a1f7dc163a6db Original-Signed-off-by: Bayi Cheng <bayi.cheng@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/323932 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13979 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12device/i2c: Add i2c_read_bytes() APIJitao Shi
Add multi-bytes read support. BRANCH=none BUG=none TEST=saw edid log and dev screen Change-Id: I106be98e751e2a3b998ccaedb28f71f3c6e18994 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 94ee0b834947e8d971943aa24e61a9353c7b7306 Original-Change-Id: Iac5fe497da92b7d09383e0d6a04d98709aea5b20 Original-Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/325211 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13978 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12google/oak: Configure USB OC pinsYidi Lin
BRANCH=none BUG=none TEST=none Change-Id: If7244d0050833c676de72106d1c8473dd8f290a8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 89356785e66eb6d5b52fdf09933d2d28d9f67a90 Original-Change-Id: I94dda9834da6553795e7f3f65ff267fdcb6b7d47 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/321055 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13977 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12google/oak: Config USB Hub for rev5Ben Lok
Reset pin of USB Hub is connected to GPIO118, it is low active. Config GPIO118 as GPO and output high. BRANCH=none BUG=none TEST=emerge-oak coreboot Change-Id: I630cfd1c1019447736e7e5b286790fead4bdcfb6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b4b5cd98d0b3c5d2bab408ecebebc924d1f2b7df Original-Change-Id: I1ea0e1baac3da4d13301307f01bbe51e108298dd Original-Signed-off-by: Ben Lok <ben.lok@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/321054 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13976 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12google/oak: Config audio for rev5Koro Chen
BRANCH=none BUG=none TEST=emerge-oak coreboot Change-Id: Ibdafa4ffe0baf5231654e67612b7ca59d835b602 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 63fedfec26ba1444934e348ce59609fa88e12de5 Original-Change-Id: Ifbbf8d2b3b6e163481843308c2e3edc4a55f90c6 Original-Signed-off-by: Koro Chen <koro.chen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319988 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13975 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12google/oak: Remove obsolete Rev0 settingKoro Chen
BRANCH=none BUG=none TEST=emerge-oak coreboot Change-Id: I65aa87e88cf812fdb490933de1a3b121866a2694 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8f703f7e71ae6ffc0f1ac0e70486d087a28da5ba Original-Change-Id: I8d794464d45ea69f9a46f7ebc505f6ec2127f204 Original-Signed-off-by: Koro Chen <koro.chen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319987 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13974 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12google/oak: Enable TP_SHIFT_EN for the revisons before 5 onlyYidi Lin
BRANCH=none BUG=none TEST=emerge coreboot Change-Id: Ic46490a56a6a8146b91a055b9ce5d5bb23bc7a49 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 082ce1848bf37bba369fd0dccc4cf3fc83a8a018 Original-Change-Id: I58f009d2fc03cf5a52b4dbd042a92973cde4d035 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/320029 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13973 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12google/oak: da9212 gpio configuration for rev5henryc.chen
BRANCH=none BUG=none TEST=none Change-Id: Ib44a9e8ca94727809e47831228f4742c25a53977 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: da9185c22264440da822aa252c0c5d2aef78b455 Original-Change-Id: I98c2ad757d0cd0e3234e49392091784b43a106e7 Original-Signed-off-by: henryc.chen <henryc.chen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/320028 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13972 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12google/oak: Config PANEL_LCD_POWER_EN for rev5Yidi Lin
BRANCH=none BUG=none TEST=emerge-oak coreboot Change-Id: Ic2019a1d61cbc5949c1f42346b279ef05f725dfb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bf13606f01438bc2ea27ecccc6359a7320dc34cc Original-Change-Id: I3fcc403cb7a3429b9673be0e727fc7d8c9d4f556 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/320027 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13971 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12google/oak: Configure SPI_LEVEL_ENABLE pin for rev5Yidi Lin
Oak introduces a 1.8V to 3.3V level shifter for EC SPI bus after rev5. BRANCH=none BUG=none TEST=emerge-oak coreboot Change-Id: I71868b003fc71dee0532033299afc155a9fbec9c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 030b478fedf046a7b818696779299c591415fcbd Original-Change-Id: Ibff9705832700867279cb1b39b752b8f5f27cf33 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/320026 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13970 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12mediatek/mt8173: Update infracfg register mapMilton Chiang
BRANCH=none BUG=none TEST=emerge-oak coreboot Change-Id: Ifdeb686f7695fbefadc15d47e9b0c49b6b35c37d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2404a31dac8c84580424fc01816669b27ddf8617 Original-Change-Id: I831d34b1bce2675caa3da8da7a214f392e561000 Original-Signed-off-by: Milton Chiang <milton.chiange@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/320025 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13969 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12google/oak: Initialize i2c bus timing register for TPM and external buckjun.gao
BRANCH=none BUG=none TEST=build pass and boot to oak kernel Change-Id: Id2c3bbb70a1de54a56ee04ecda76178b1bdf1a4d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8641689e008c58e909606c225dddb81dc6457ae9 Original-Change-Id: I96ef8a36bc70594097e9df964934b7e3eca5d5f9 Original-Signed-off-by: jun.gao <jun.gao@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319031 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13108 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12google/oak: add event logCC Ma
BRANCH=none BUG=none TEST=boot to shell on Rev3 Change-Id: Ifca80705e392ce171ef33bf98ef787e3cd5ffd6b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7d511df7f527ae96c2da01804c62fe98a13fed56 Original-Change-Id: I68ab8be50f210fa17bd731b400a087b150566e3b Original-Signed-off-by: CC Ma <cc.ma@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/303207 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13104 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12google/oak: Add soc ARM Trusted Firmware supportJimmy Huang
We define a mechanism to pass board specific parameters to BL31. The idea is BL31 doesn't need to have the board revision knowledge, it only needs to process the board specific parameters to initialize and control specific hardware. In this way, we can support different boards with same BL31 binary. BRANCH=none BUG=none TEST=booted on oak-rev2 and oak-rev3 boards, and confirmed they got different board arguments in ARM TF Change-Id: I0df2c6d7d1ffac7d443511c3317c142efeb5701e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0f9a4a2776110c5ddc113f0d605d4337d5773ace Original-Change-Id: I985d9555238f5ac5385e126479140b772b36bac8 Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292678 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13101 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12mediatek/mt8173: Add soc ARM Trusted Firmware supportJimmy Huang
We define a mechanism to pass board specific parameters to BL31. The idea is BL31 doesn't need to have the board revision knowledge, it only needs to process the board specific parameters to initialize and control specific hardware. In this way, we can support different boards with same BL31 binary. [pg: add the code, but don't actually enable the support yet, because it relies on code that still needs to be merged to arm-trusted-firmware.] BRANCH=none BUG=none TEST=booted on oak-rev2 and oak-rev3 boards, and confirmed they got different board arguments in ARM TF Change-Id: I9ea3ce6c8f79dd427be67f30bc940d2038173b81 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0f9a4a2776110c5ddc113f0d605d4337d5773ace Original-Change-Id: I985d9555238f5ac5385e126479140b772b36bac8 Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292678 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13100 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12mediatek/mt8173: Provide I2C bus initialization APIjun.gao
BRANCH=none BUG=none TEST=build pass and boot to oak kernel Change-Id: I8aa9ca0fce804cc1682947b7e184781dd5d437f7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8641689e008c58e909606c225dddb81dc6457ae9 Original-Change-Id: I96ef8a36bc70594097e9df964934b7e3eca5d5f9 Original-Signed-off-by: jun.gao <jun.gao@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319031 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13107 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12google/oak: Initialize DRAMPeter Kao
BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: I3ed8bad1bdc7d17e334e0136f92a51c8e7ba4e67 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b614eeb1bba5660438c214e82225832809caca8e Original-Change-Id: I0f7b0a426dae1548b34114a024c92befdf6002f6 Original-Signed-off-by: Peter Kao <peter.kao@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292692 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13106 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12mediatek/mt8173: Add EMI driver, DRAM initializationPeter Kao
BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: I6b05898de2d0022e0de7b18f1db3c3e9c06d8135 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b614eeb1bba5660438c214e82225832809caca8e Original-Change-Id: I0f7b0a426dae1548b34114a024c92befdf6002f6 Original-Signed-off-by: Peter Kao <peter.kao@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292692 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13105 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12mediatek/mt8173: enable RTC in ramstageCC Ma
BRANCH=none BUG=none TEST=boot to shell on Rev3 Change-Id: I77c5a8aa31ab10d82115a60bdfee1da35707619f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7d511df7f527ae96c2da01804c62fe98a13fed56 Original-Change-Id: I68ab8be50f210fa17bd731b400a087b150566e3b Original-Signed-off-by: CC Ma <cc.ma@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/303207 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13103 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-12mt8173: add SPI NOR supportmtk05962
BRANCH=none BUG=none TEST=boot oak to kernel on rev1 Change-Id: I0773c81398df445aec16bcfcd0c5a8fe5a588b5c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ae15c42c2f7d9c2a716e5b6098d85e17279f5eae Original-Change-Id: I65abf810d35ae5e7156cf6f5730117e690183d18 Original-Signed-off-by: mtk05962 <bayi.cheng@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292693 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13102 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-11northbridge/intel: move mrccache.c of sandybridge + haswell to commonAlexander Couzens
The sourcecode is 99% the same. Only two lines differ, but not in functionality. Also rename mrccache.c -> mrc_cache.c Tested-on: boot + suspend/resume on x220 Change-Id: I36f79d066336f223b608c70c847ea6ea6e4ad287 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/14007 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-11northbridge/intel: move mrc_cache definition into a common headerAlexander Couzens
The mrc_cache definition and the struct mrc_container are the same over all intel platforms. Change-Id: I128a4b5693d27ead709325c597ffe68a0cc78bab Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/13998 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-11spi/SST: fix write support for SST25VF064CAlexander Couzens
The SST25VF064C doesn't support the auto incrementing write which all other supported SST chips support. Allow the chips to select their write method. Change-Id: Ic088d35461a625469ee6973d1267d7dd11963496 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/14000 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-11nortbridge/sandybridge/mrccache: parse the return code of flash->writeAlexander Couzens
Change-Id: I2738da99e4651598faeaa228fba447d0872e9ded Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/13999 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-11nb/amd/mct_ddr3: Train correct receiver in TrainDQSRdWrPos_D_Fam15Timothy Pearson
Change-Id: Ia26950a8297f0a7125c21e995c89a3fc68d9d8a9 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13932 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-11nb/amd/mct_ddr3: Consolidate calls to MCT minimum clock setting fetchTimothy Pearson
Change-Id: I4497b0be6ed6c90dbb31e89013feed8ff5ff9071 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13885 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-03-11nb/amd/mct_ddr3: Require minumum training quality for both read and writeTimothy Pearson
The existing MCT code proceeded to the next DRAM training phase if the minimum lane quality standard passed for either the read or write direction. Ensure that both pass for a given set of delay values before proceeding to the next training phase. Change-Id: I2316ca639f58a23cf64bea56290e9422e02edf1c Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13993 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-11nb/amd/mct_ddr3: Set read DQS delay to 1UI before calculating read latencyTimothy Pearson
The AMD Family 15h BKDG rev. 3.14 indicates that the maximum read latency must be calculated prior to DQS position training, however the read latency calculations use read DQS delay values that have not been set prior to DQS position training. Set the read DQS delay values to 1UI (i.e worst case) before calculating the read latency prior to DQS position training. Change-Id: I6ae88c891e92b21dc0ca3c47b8f3d269f83b3204 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13995 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-11nb/amd/mct_ddr3: Properly initialize arrays and add bounds checksTimothy Pearson
A couple of arrays were not properly initialized. This did not appear to affect operation of the codebase however it led to some ugly values being displayed when debugging was turned on. Also bounds check an array index; as before this did not appear to affect operation but was a potential point of failure. Change-Id: I243b7197a74aed78ddca808eb3b0f35f1fe9d95a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13934 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-11nb/amd/mct_ddr3: Restore previous DQS delay values on failed loopTimothy Pearson
Change-Id: Iacfcd7f379d09a633973b4c3ef3cbb97e6d1f09f Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13931 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-11soc/intel/apollolake: Avoid hardcoding CAR region size for FSPMAndrey Petrov
Instead of having to supply CAR memory region during compilation time it is possible to determine it in runtime. FSP2.0 blobs carry a copy of UPD structure pre-populated with 'default' values. The default value for StackSize is actually the real value blob needs. Change-Id: I298e07bb12470ce659f63846ab096189138e594f Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14001 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-11arch/x86/smbios: fix length calculation for SMBIOS type 17Iru Cai
Different DIMM modules give different SMBIOS type 17 lengths, so we can't use `meminfo->dimm_cnt*len' for entry struct size, otherwise it'll give a wrong SMBIOS size when two or more different DIMMs are installed on the machine. Change-Id: I0e33853f6aa4b30da547eb433839a397d451a8cf Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/14008 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-03-11Kconfig: remove COMPRESS_PRERAM_STAGES option from x86Martin Roth
Instead of just defaulting to disabled, remove the option for x86 since it doesn't work there. Change-Id: I2b84b9f866f9231943e573b873c970f420c7c9a5 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14017 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2016-03-11cbmem: Fix cbmem_add_bootmem()Andrey Petrov
Change 13363 (555d6c2) introduced a bug where cbmem_add_bootmem() was converted to use a new function. Unfortunately instead of passing a pointer, NULL was passed due to type confusion. This change fixes that problem by passing address of stack variable instead of NULL. Change-Id: Ib8e1add3547cda01f71bf1dea14d3e58bdd99730 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14033 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-03-11northbridge/i945/gma: Re-enable NVRAM tft_brightnessAlexander Couzens
Commit 71512b2c (northbridge/i945/gma: fix build error with native graphics init) unintentionally changed the code to ignore the NVRAM setting `tft_brightness`. Revert that hunk to restore the original behavior. Change-Id: Iffdfc5272732bad3476f35ddac1f5a7564270531 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/14002 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-10soc/apollolake: Add memory and reserve MMIO resourcesAndrey Petrov
This adds most important MMIO reserved memory resources, real DRAM memory resources, and some DRAM resources that can not be used as RAM for whatever reason. Change-Id: Id5a80cf18d67ace991e8046fa46c4b7ed47c626a Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13360 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-13 15:49:26 +0000