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2016-03-08cpu/x86/mtrr: add helper function to detect variable MTRRsAaron Durbin
The current MTRR API doesn't allow one to detect variable MTRRs along with handling fixed MTRRs in one function call. Therefore, add x86_setup_mtrrs_with_detect() to perform the same actions as x86_setup_mtrrs() but always do the dynamic detection. Change-Id: I443909691afa28ce11882e2beab12e836e5bcb3d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13935 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-03-08soc/intel/quark: Add the UPD support for SiliconInitLee Leahy
Add the routines to handle the UPDs for SiliconInit. Currently no support is required. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Edit .config file and add the following lines: * CONFIG_DISPLAY_UPD_DATA=y * Testing successful if coreboot calls SiliconInit Change-Id: I5176ab4b1ea7681c3095f102a86f4b614366c0fc Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13897 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-08cpu/x86: Sort some Kconfig optionsStefan Reinauer
Change-Id: I25ea327ed151e18ccb5d13626d44925d2a253d08 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/10012 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-08soc/intel/apollolake: Enable using FSP 2.0 driverAndrey Petrov
Change-Id: I5d50fecca51e89aed597e1cfafbcd4515d4d4388 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13806 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-08soc/intel/apollolake: Add romstage that calls FSP2.0 driverAndrey Petrov
This romstage is minimalistic. Its goal is to set up some BARs that FSP expects to be set and then invoke FSP driver to train memory. Change-Id: I3fa56aafe99cf6cf062a46dece3a0febeafdbfad Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13805 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-08soc/intel/apollolake: Add support for memory-mapped boot mediaAndrey Petrov
On Apollo Lake SPI flash is memory mapped. The mapping is different to previous platforms. Only "BIOS" region is mapped in contrast to whole flash. Also, the 128 KiB right below 4 GiB are being decoded by readonly SRAM. Fail accesses to those regions, rather than returning false data. Change-Id: Iac3fa74cd221a5a46ceb34c2a79470290bcc2d84 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13706 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-08drivers/intel/fsp2_0: Add framebuffer graphics supportAlexandru Gagniuc
This adds a few helper functions that are intended to assist setting up framebuffer. Change-Id: Id8ed4de1f9de32e9222b0120c15a6d33676346e7 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13802 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-08drivers/intel/fsp2_0: Add hand-off-block parsersAlexandru Gagniuc
FSP creates hand-off-blocks (HOBs) to exchange information with coreboot. This adds a set of utilities to parse HOBs and extract some useful information from them. Change-Id: If55dbfaa021cd68c312813a5532a36c68806dbbc Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13801 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-08drivers/intel/fsp2_0: Add Notify Phase APIAndrey Petrov
This adds Notify Phase API. This is an important call that is used to inform FSP runtimes of different stages of SoC initializations by the coreboot. Change-Id: Icec770d0c1c4d239adb2ef342bf6cc9c35666e4d Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13800 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-08drivers/intel/fsp2_0: Add SiliconInit APIAndrey Petrov
This adds SiliconInit API that is needed to be called after memory has been trained. This call is needed to let the blob do various initialisations of IP blocks. Change-Id: I35e02f22174c8392e55ac869265a19c4309932e5 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13799 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-08drivers/intel/fsp2_0: Add MemoryInit APIAndrey Petrov
This adds implementation of fsp_memory_init() that is used to train memory. Change-Id: I72268aaa91eea7e4d4f072d70a47871d74c2b979 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13798 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-08roda/rk9: Remove #include early_serial.c from romstageAntonello Dettori
Remove dependency on early_serial.c and instead use the Super I/O's header to access the functions needed. Also re-organize some of the superio code in order to succesfully compile the rom. Change-Id: I85a6f1352ae3b91c3c98e4d3fa0b90b87e02babc Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/13925 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-07intel/fsp_baytrail: use 20K PU/PD for GPIOBen Gardner
The E3800 datasheet only lists 2K and 20K Pull Strength for the GPIOs. The 10K and 40K values map to 'reserved'. This brings the code closer to the non-FSP baytrail. Change-Id: I77078bdbbccc00976525dc43fb98f5b2e79eae03 Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/13907 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-07soc/intel/quark: Split out MTRR supportLee Leahy
Split out the MTRR support into a new module: mtrr.c. TEST=Build and run on Galileo Change-Id: Ib9ec479d171dbbc062509e14fbe246f6d90e903a Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13895 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-07mainboard/intel/galileo: Enable SD flash cardsLee Leahy
Turn on the SD controller to allow it to claim resources. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Edit .config file and add the following lines: * CONFIG_PAYLOAD_ELF=y * CONFIG_PAYLOAD_FILE="path to UEFIPAYLOAD.fd" * Testing successful when at the UEFI shell prompt: * After issuing: * "connect -r" * "map -r" * The "dir" command displays the contents of the SD flash card * The "drivers" command shows an SD host and SD media connection Change-Id: I883dc87270045786ddb931bea83fc36646a128e6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13894 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-05tpm/acpi/tpm.asl: Only include tpm.asl if tpm is enabledMartin Roth
If the TPM code isn't getting built in, the Kconfig symbol CONFIG_TPM_TIS_BASE_ADDRESS doesn't exist. This ends up creating an invalid operating region in the ACPI tables, causing a bluescreen in windows. This should fix this issue: https://ticket.coreboot.org/issues/35 "commit 85a255fb (acpi/tpm: Gracefully handle missing TPM module) breaks Windows" Change-Id: I32e0e09c1f61551a40f4842168f556d5e1940d28 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13890 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-05arch/x86: Add common assembly code for stages that run in CARAndrey Petrov
This adds a few assembly lines that are generic enough to be shared between romstage and verstage that are ran in CAR. The GDT reload is bypassed and the stack is reloaded with the CAR stack defined in car.ld. The entry point for all those stages is car_stage_entry(). Change-Id: Ie7ef6a02f62627f29a109126d08c68176075bd67 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13861 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-03-05arch/x86: document CAR symbols and expose them in symbols.hAndrey Petrov
Attempt to better document the symbol usage in car.ld for cache-as-ram usage. Additionally, add _car_region_[start|end] that completely covers the entire cache-as-ram region. The _car_data_[start|end] symbols were renamed to _car_relocatable_data_[start|end] in the hopes of making it clearer that objects within there move. Lastly, all these symbols were added to arch/symbols.h. Change-Id: I1f1af4983804dc8521d0427f43381bde6d23a060 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13804 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-03-05amd/thatcher: Removed #include early_serial.c from romstageAntonello Dettori
Remove dependency on early_serial.c and instead use the Super I/O's header to access the functions needed. Change-Id: I9edf7fc2501aa832106dda9213e702dbcc1200b4 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/13887 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-03-05include/device/dram: Fix DDR3-1866Patrick Rudolph
The PLL multiplier value is off by one for DDR3-1866 due to a wrong TCK value, resulting in DDR3-1600 being used by the PLL. Needs test on real hardware ! Change-Id: I657b813889945f0d9990dd11680a3d3a25b53467 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13613 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-05sandybridge/gma_lvds: support both Sandy&Ivy on one boardIru Cai
Sandy and Ivy Bridge processors use the same socket, and a mainboard with the socket can support both types of CPUs. However, they use different native graphics init code for LVDS and cause a crash if running the wrong code. This change detects the CPU type and then selects the right code to run. It will add some more code in ramstage. It also merges the {SANDY,IVY}BRIDGE_LVDS symbol to one SANDYBRIDGE_IVYBRIDGE_LVDS. Tested on a Lenovo T520 with i7-2630qm and i7-3720qm Signed-off-by: Iru Cai <mytbk920423@gmail.com> Change-Id: I4624759f9c92d56d547db1ab4b9a1d611a182a91 Reviewed-on: https://review.coreboot.org/12087 Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Tested-by: build bot (Jenkins)
2016-03-05Hide EC_GOOGLE_CHROMEEC_SPI_BUS.Vladimir Serbinenko
It's mobo architecture, not a user-adjustable setting. Change-Id: I8bb81638f391cf0ba880801e4707d8f0957897c8 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13906 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-05lz4_wrapper: Use __asm__ rather than asm.Vladimir Serbinenko
__asm__ is more robust to compilation flags. Change-Id: Ic7ca6e38ddd439dcfc4a62ef272ecea62416b4be Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13905 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-03-05Kconfig: hide useless options on ARM.Vladimir Serbinenko
Those options have no effect or lead to compile error on ARM due to fundamental incompatibilities. Add proper "depends on" clauses to hide them. Change-Id: I860fbd331439c25efd8aa92023195fda3add2e2c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13904 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-04arch/x86: always use _start as entry symbol for all stagesAaron Durbin
Instead of keeping track of all the combinations of entry points depending on the stage and other options just use _start. That way, there's no need to update the arch/header.ld for complicated cases as _start is always the entry point for a stage. Change-Id: I7795a5ee1caba92ab533bdb8c3ad80294901a48b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13882 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-04arch/x86: rename reset_vector -> _startAaron Durbin
In order to align the entry points for the various stages on x86 to _start one needs to rename the reset_vector symbol. The section is the same; it's just a symbol change. Change-Id: I0e6bbf1da04a6e248781a9c222a146725c34268a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13881 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-03arch/x86: Allow soc/chipset to set linking addressAndrey Petrov
Until recently x86 romstage used to be linked at some default address. The address itself is not meaningful because the code was normally relocated at address calculated during insertion in CBFS. Since some newer SoC run romstage at CAR it became useful to link romstage code at some address in CAR and avoid relocation during build/run time altogether. Change-Id: I11bec142ab204633da0000a63792de7057e2eeaf Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13860 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-03-03cpu/x86/16bit: rename _start -> _start16bitAaron Durbin
In order to avoid collisions with other _start symbols while grepping and future ones be explicit about which _start this one is: the 16-bit one only used by the reset vector in the bootblock. Change-Id: I6d7580596c0e6602a87fb158633ce9d45910cec2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13880 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2016-03-03cpu/x86/16bit/reset16: mark reset vector executableAaron Durbin
It's helpful to see the reset vector in objdump output. Without it being marked executable it doesn't get displayed. Change-Id: I85cb72ea0727d3f3c2186ae20b9c5cfe5d23aeed Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13879 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2016-03-03cpu/x86/16bit/reset16: remove stale 32-bit jumpAaron Durbin
Patrick at least indicated this jump after the reset vector jump was a remnant from some construct used long ago in the project. It's not longer used (nor could I find where it was). Therefore, remove it. Change-Id: I31512c66a9144267739b08d5f9659c4fcde1b794 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13878 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2016-03-03drivers/intel/fsp2_0: Add utility functionsAndrey Petrov
This adds a set of utility functions that help load and identify FSP blobs. Change-Id: I1d23f60fd1dc8de7966142bcd793289220a1fa5e Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13797 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-03drivers/intel/fsp2_0: Add coreboot<->FSP header filesAndrey Petrov
This adds important header files that specify calling interface between coreboot and FSP. Change-Id: I393601c91e3c3f630e0fc899f1140ecefed8ecba Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13796 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-03nb/intel/sandybridge/raminit: Fill SMBIOS type17 infoPatrick Rudolph
Fill minimal info required for SMBIOS type 17. Report * DIMM size * channel * rank per DIMM * speed in Mhz * DIMM type * slot * manufacturer ID * serial Allows dmidecode to print the current RAM configuration. Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 * Linux 4.3 * dmidecode 3.0 dmidecode output: Handle 0x0005, DMI type 17, 40 bytes Memory Device Array Handle: 0x0000 Error Information Handle: Not Provided Total Width: 16 bits Data Width: 8 bits Size: 8192 MB Form Factor: DIMM Set: None Locator: Channel-0-DIMM-0 Bank Locator: BANK 0 Type: DDR3 Type Detail: Synchronous Speed: 1600 MHz Manufacturer: Unknown (cd04) Serial Number: None Asset Tag: Not Specified Part Number: F3-1866C9-8GSR Rank: 2 Configured Clock Speed: 1600 MHz Minimum Voltage: Unknown Maximum Voltage: Unknown Configured Voltage: Unknown Handle 0x0006, DMI type 17, 40 bytes Memory Device Array Handle: 0x0000 Error Information Handle: Not Provided Total Width: 16 bits Data Width: 8 bits Size: 8192 MB Form Factor: DIMM Set: None Locator: Channel-1-DIMM-1 Bank Locator: BANK 0 Type: DDR3 Type Detail: Synchronous Speed: 1600 MHz Manufacturer: Unknown (cd04) Serial Number: None Asset Tag: Not Specified Part Number: F3-1866C9-8GSR Rank: 2 Configured Clock Speed: 1600 MHz Minimum Voltage: Unknown Maximum Voltage: Unknown Configured Voltage: Unknown Change-Id: I4e5f772d68484b9cb178ca8a1d63ad99839f3993 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13852 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-03src/device/dram/ddr3: Parse additional informationPatrick Rudolph
Parse manufacturer id and ASCII serial. Required for SMBIOS type 17 field. Change-Id: I710de1a6822e4777c359d0bfecc6113cb2a5ed8e Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13862 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-02nb/intel/sandybridge/romstage: Read fuse bits for max MEM ClkPatrick Rudolph
Instead of hardcoding the maximum supported DDR frequency to 800Mhz (DDR3-1600), read the fuse bits that encode this information. Test system: * Intel IvyBridge * Gigabyte GA-B75M-D3H Change-Id: I515a2695a490f16aeb946bfaf3a1e860c607cba9 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13487 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-02src/arch/x86/smbios: Add vendorsPatrick Rudolph
Add more manufacturer IDs for vendor: * GSkill * OCZ * Transcend Change-Id: Ic7df76b1310b2c1abea9c5d2d8fd688cb2a713b8 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13863 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-03-02nb/intel/sandybridge/raminit: Make discover_timC_write non cyclicPatrick Rudolph
The code can't handle cyclic zero runs. Make sure it will never wrap around by setting the top-most bit to constant one. Fixes "Mini channel test failed (2)". Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 Change-Id: I55e610d984d564bd4675f9318dead6d6c1e288a3 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13853 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-01Skylake: Support Intel Speed Shift Technology based on configSubrata Banik
Intel Speed Shift Technology is a new mechanism that replaces Legacy P-state. ISST allows OS hints about energy/performance preference. H/W performs the actual P-state control (autonomous) 1. Optimization frequency seclection for low residency workloads, no longer a static knee point. 2. Optimized frequency selection for best energy to performance trade offs. 3. Kick down frequency (from idle) fpr best responsiveness while taking energy consumption init account. Coreboot's responsiblity is to configure MSR 0x1AA ISST_EN bits which will reflect in CPUID.06h:EAX[Bit 7] that driver checkes and enable HWP accordingly. BUG=chrome-os-partner:47517 BRANCH=None TEST=Booted kunimitsu and verify HWP getting enabled/disabled using Intel P-state driver. Change-Id: I91722aa1077f4ef6c8620b103be3e29cfcd974e5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: aa7d004cb2e19047e4434e3e2544cf69393ce28f Original-Change-Id: Ie617da337babde7f196a7af712263e37f7eed56f Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313107 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Wenkai Du <wenkai.du@intel.com> Reviewed-on: https://review.coreboot.org/13835 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-01Skylake boards: Enabling HWP (hardware P state control)Subrata Banik
This patch provides config options to enable/disable Intel SST (Speed Shift Technology). BUG=chrome-os-partner:47517 BRANCH=None TEST=Booted kunimitsu/lars, verified HWP driver load successfully. CQ-DEPEND=CL:313107 Change-Id: I9419a754384f96d308a5ac2ad90bbb519edc296e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 5efb7978e9d3ca9a709a4793ad213423a1c3c45d Original-Change-Id: I328b074b4f56ebe3caa8952ce3df7f834c1cf40f Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/326650 Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Benson Leung <bleung@chromium.org> Reviewed-on: https://review.coreboot.org/13843 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-29google/chell: Update DPTF configurationDuncan Laurie
Update the DPTF configuration for the chell mainboard: 1) Enable DPTF charger control, set max current to 1975mA according to the battery specification. 2) Enable charger effect on charger temp sensor in TRT 3) Set PL2 to 15W which is the same value configured in the CPU. BUG=chrome-os-partner:49859,chrome-os-partner:50306 BRANCH=glados TEST=build and boot on chell Change-Id: I644256b9596cc5295513c48f5e3a18e6ce8b0a6b Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: c19740a227f932bf80e9243341ec81763779719c Original-Change-Id: Icff5edc9d659bea6370ff8de1334ebf0983340da Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/329187 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13842 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-29google/chell: Update GPIOs for DVT2Duncan Laurie
Add new GPIOs for touchscreen enable and reset pins and define the one missing unconnected pin for GPP_E10. BUG=chrome-os-partner:50518 BRANCH=glados TEST=build and boot on chell DVT1 Change-Id: I565a742ff266ee65a5d33f052606fe77c24b6ac8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 32a890af8c32aa30adac256d2c4ceaeefa30bd0d Original-Change-Id: I16546d38cc4e926e169f61ae1843106d1e14936b Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/329297 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13841 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-29vboot: Set S3_RESUME flag for vboot context if necessaryDuncan Laurie
If a platform does verification of the memory init step, and it must resume with the same slot that it booted from then it needs to set the vboot context flag when resuming instead of booting. This will affect the slot that is selected to verify and resume from. BUG=chromium:577269 BRANCH=glados TEST=manually tested on chell: 1) ensure that booting from slot A resumes from slot A. 2) ensure that booting from slot B resumes from slot B. 3) do RW update while booted from slot A (so the flags are set to try slot B) and ensure that suspend/resume still functions properly using current slot A. 4) do RW update while booted from slot B (so the flags are set to try slot A) and ensure that suspend/resume still functions properly using current slot B. Change-Id: I77e6320e36b4d2cbc308cfb39f0d4999e3497be3 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 4c84af7eae7b2a52a28cc3ef8a80649301215a68 Original-Change-Id: I395e5abaccd6f578111f242d1e85e28dced469ea Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/328775 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13834 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-29skylake: Increase IGD stolen size to 64MBDuncan Laurie
The FBC hardware for skylake does not have access to the bios_reserved range so it always assumes 8MB is used and so the kernel will therefore need to avoid using the last 8MB of the stolen window. With the default stolen size of 32MB(-8MB) there is not enough space for FBC to work with a high resolution panel. Kernel reference: http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=a9da512b3ed73045253afd778e40d4298f42905b BUG=chrome-os-partner:50396 BRANCH=glados TEST=build and boot on chell DVT Change-Id: I3049d7d9e7c551aad5b8fd1630d5fbd88ccb2692 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: fff1f4b35e23e77cdc72c5bcc290f199494cdbbb Original-Change-Id: If468cca5759a320f3cd2d7eb09f4bcc0117b24cb Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/328813 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13833 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-29mainboard/google/chell: provide configuration for all padsAaron Durbin
Instead of relying on power-on-reset values provide configuration for all pads. PAD_CFG_NC() was used for all pads which had no nets routed on the board. PAD_CFG_GPO(0) was used for pads which had nets routed on the board in order to terminate them. BUG=chrome-os-partner:50301 BRANCH=glados TEST=Built and booted chell. Suspended and resumed on EVT. Change-Id: I7960442d5c06f58a1b671cdefac71ef0bc3b0cd5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 6a167cd0a747402bfc3cc9b6fbaaceceda766ee9 Original-Change-Id: I519011b049235dc2a960939c0bed274252dbffa8 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/327835 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/13831 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-29mainboard/intel/galileo: Enable USBLee Leahy
Enable the EHCI and OHCI controllers. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Edit .config file and add the following lines: * CONFIG_PAYLOAD_ELF=y * CONFIG_PAYLOAD_FILE="path to UEFIPAYLOAD.fd" * Testing successful when at the UEFI shell prompt: * After issuing: * "connect -r" * "map -r" * The "dir" command displays the contents of the USB flash drive * A USB keyboard can issue shell commands * The "drivers" command shows an EHCI and OHCI connection Change-Id: Iad9abced98d9b645e8b12fa0845c97260cf62a72 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13857 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-29soc/intel/quark: Reserve non-MMIO spaceLee Leahy
Adjust the memory map to allocate MMIO from non-memory addresses. TEST=None Change-Id: Icb6863665c466e8609af73eb9338165c7d6f46bf Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13856 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-29soc/intel/quark: Initialize some of the FADT base registersLee Leahy
Initialize the base addresses for: * Power management control * Power management status * Reset * Power management timer * General-Purpose Event 0 Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Edit .config file and add the following lines: * CONFIG_PAYLOAD_ELF=y * CONFIG_PAYLOAD_FILE="path to UEFIPAYLOAD.fd" * Testing successful when: * Register address are properly displayed by the payload * "reset -c" performs a reset and reboots the system * "reset -w" performs a reset and reboots the system * "reset -s" performs a reset and turns off the power Change-Id: I9d043f4906a067b2477650140210cfae4a7f8b79 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13764 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-28northbridge/intel: add missing #include guardsIru Cai
I first found the missing of #include guards when I tried to include both sandybridge/gma.h and sandybridge/sandybridge.h, but sandybridge.h includes gma.h in it and gives a compile error. Change-Id: I13fdb8014b82e6065be2064137b7ea10062deaca Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/13775 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-02-26During DRAM initialization on certain ASpeed devices, an incorrectTimothy Pearson
bit (bit 10) was checked in the "SDRAM Bus Width Status" register to determine DRAM width. Query bit 6 instead in accordance with the Aspeed AST2050 datasheet v1.05. Change-Id: I05c3c7877015d95eb8d512f7410604b9af043b26 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13807 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-26nb/intel/sandybridge/raminit: Adjust timB to prevent overflowPatrick Rudolph
Improved version of I1a115a45d5febf351d89721ece79eaf43f7ee8a0 The first version wasn't well tested due to the lack of hardware and it was to aggressive. With timC being direct function of timB's 6 LSBs it's critical to match timC and timB. Some tests increments the value of timB by a small value, which might cause the 6bit value to overflow, if it's close to 0x3F. Increment the value by a small offset if it's likely to overflow, to make sure it won't overflow while running tests and bricks the system due to a non matching timC. In comparission to the first attempt, only 4 out of 128 timB values are considered bad. Needs test on real hardware ! Fixes a "edge write discovery failed" on my test system. Test system: * Intel IvyBridge * Gigabyte GA-B75M-D3H Change-Id: If9abfc5f92e20a8f39c6f50cc709ca1cedf6827d Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13714 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-01 00:52:51 +0000