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2018-04-17soc/intel/apollolake: Configure PCIe root port #1 for APL WiFiVenkateswarlu Vinjamuri
APL uses PCIe root port 1 (PCIe ID 14.0) for discrete PCIe wifi card. BUG=None BRANCH=None TEST=Use Stone Peak discrete wifi card and test s0ix. Change-Id: Ia81722f4533916fe93009a73d86765e5de9dab08 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/25637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-17nb/intel/x4x/rcven.c: Change the verbosity of some messagesArthur Heymans
Displaying the whole receive enable procedure is very verbose should only be done if CONFIG_DEBUG_RAM_SETUP is selected. Change-Id: Ib568621e6d044624c1c0aeb6fb08945f561395c7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-04-17nb/intel/x4x: Add a convenient macro to loop over bytelanesArthur Heymans
During raminit a lot of procedures need to be done for each bytelane. Change-Id: Ib9a30ffabaf5c845e962e3e79cf4a20faa1d9857 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-17nb/intel/x4x: Clarify the raminit memory mappingArthur Heymans
This replaces magic values by macros and adds some comments to improve readability. Adds a convenient function to fetch the test address of a rank. Also fixes the temporary memory map by changing a write to MCHBAR 0x100 to 0x110, since this is what vendor does. (No difference observed thus far) TESTED on DG43GT Change-Id: I58923e4a8a756f4ae65f759e7d46e03fad39fab7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-04-17nb/intel/x4x: Refactor setting default dll settingsArthur Heymans
This patch pushes these large default delay tables to a different file to reduce cluttering up the actual raminit source. While doing so it also uses more but smaller arrays and also adds the respective default delays for DDR3 which are not yet used in this patch. This patch add a function to set the read DQS delays instead of just programming magic values. (This will prove useful for DQS read training) To prepare for adding trainings on the delay values it stores these default delays in the sysinfo struct to program those. Later when trainings are implemented those trained values will be used instead of these safe default values, via using the cached sysinfo in 'mrc' cache. TESTED on DG43GT (still works fine) Change-Id: I0e3676e06586ea84fc0729469946dbc9a8225934 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-17nb/intel/x4x: Use SPI flash to cache raminit resultsArthur Heymans
Stores information obtained from decoding dimms and receive enable results for future use. Depreciates using rtc nvram to store receive enable settings. A notable change is that receive enable results are always reused, not just on a resume from S3. This requires cbmem to be initialized a bit earlier, right after the raminit finished to be able to add the sysinfo struct to cbmem which gets cached to the SPI flash in ramstage. TESTED on Intel DG43GT with W25Q128.V. With 4 ddr2 dimms time in raminit goes from 133,857ms (using i2c block read to fetch SPD) to 21,071ms for cached results. Change-Id: I042dc5c52615d40781d9ef7ecd657ad0bf3ed08f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-17mb/google/poppy/variants/nami: Enable DPTF and configure DPTF parametersFrank Wu
The commit enables DPTF function. The DPTF parameters are provided by thermal team. BUG=b:72974136 BRANCH=poppy TEST=emerge-nami coreboot then check the parameters in DPTF ui tool Change-Id: I9b7ae34ee64f19ef783a8c1571831b2293105a18 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-17soc/intel/skylake: check DPTF_TSR0_ACTIVE_AC* in _ACx methodsFrank Wu
Because thermal table is not included the values of DPTF_TSR0_ACTIVE_AC5 and DPTF_TSR0_ACTIVE_AC6 from internal nami/vayne thermal team. Add conditional compilation in _ACx methods if DPTF_ENABLE_FAN_CONTROL is defined in the dptf.asl. BUG=b:72974136 BRANCH=poppy TEST=emerge-nami coreboot and booted on nami board. Change-Id: I3e36ce94f714ff13f8ccee65992d7a9c7e0bb5b2 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25614 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-16drivers/pc80/tpm: Add some optional delay to tis_readresponse()Bill XIE
Certain TPMs (observed on Infineon SLB9635 installed on revolve 810 g1) seem to need some delay between tis_wait_valid() and tis_has_valid_data(), or tis_has_valid_data() may invalidly return 0, ending the loop immaturely with some bytes left unread, and fail to pass the check below, causing the current command not finalized by tis_command_ready(), and blocking any later tis_wait_ready(). This time the added delay is controlled by a Kconfig option TPM_RDRESP_NEED_DELAY. Change-Id: Ic2a2f252e72a0bbce51e2863f8e46647b1570ba5 Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/25322 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-16nb/intel/i945/gma: Log native graphics init in level INFOPaul Menzel
This information is not spew but useful to users. Change-Id: I195c6913b7f0b96680b433ff3251aebb7e0f70f3 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/25675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-04-16nb/intel/i945/gma: Fix aligment of equal signPaul Menzel
Change-Id: I4251071fc8d41a923b4e12de214670764097d47c Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/25674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-04-16mb/google/octopus: Add Write Protect GPIO to cros_gpiosHannah Williams
This will enable crossystem to access WP GPIO BUG=b:78009842 TEST= wpsw_cur in crossystem reads the correct gpio Change-Id: Iedd0057d6bdfd5a666ff282bc784f7b98e8c96e8 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/25673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-16nb/intel/sandybridge: support more XMP timingsDan Elkouby
Tested with a pair of GSkill F3-1866C9-8GSR. This makes sure in particular that we honor the CMD rate requested by the XMP profile. This memory kit needs a CMD rate of 2 to be stable at DDR3-1600 and up, even though it passes training at 1. Also respect requested CWL to match vendor firmware and for a potential increase in performance. The tested kit requests a tighter value than the per-frequency table provides and has shown to be stable using that setting. Change-Id: I634bed764d76345c27f02a2fae5abb2d81b38fd9 Signed-off-by: Dan Elkouby <streetwalkermc@gmail.com> Reviewed-on: https://review.coreboot.org/25664 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-16device/dram/ddr3: improve XMP supportDan Elkouby
- Fix offsets for supported CAS latencies - Add support for reading CWL and CMD rate from the profile Change-Id: Ie4f545ed1df92c146be02f56fea0ca9037478649 Signed-off-by: Dan Elkouby <streetwalkermc@gmail.com> Reviewed-on: https://review.coreboot.org/25663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-16soc/amd/stoneyridge/northbridge.c: Fix bit definitionsRichard Spiegel
The latest public BKDG (3.6) releases some previously undefined (reserved) bits. Fix these definitions, including the header file where they are defined. BUG=b:77940747 TEST=Build and boot grunt. Change-Id: Icb5334110248d7806421200a161fa3befefcea8a Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25665 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-16soc/amd/stoneyridge/lpc.c: Fix bit definitionsRichard Spiegel
The latest public BKDG (3.6) releases some previously undefined (reserved) bits, also some bits were wrongly named (possibly copied from previous chip). Fix these definitions, including the header file where they are defined. BUG=b:77940747 TEST=Build and boot grunt. Change-Id: Ie8d3fcccb8443c1a6db828bdc2624778bad6ba9f Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-16mb/google/poppy/variants/nami: Add SPD file for PantheonChris Zhou
Add SPD file for sdp hynix_dimm_H5AN8G6NCJR-VKC (ram id: 15). BUG=b:77893710 TEST=Verified that the device with this memory part boots to OS fine. Change-Id: I434d42ff12e6dae39e5676f36ba6cf00b3a48b06 Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-16mb/google/poppy/variants/nami: Add SPD file for PantheonChris Zhou
Add SPD file for sdp micron_dimm_MT40A512M16LY-075E (ram id: 14). BUG=b:77930401 TEST=Verified that the device with this memory part boots to OS fine. Change-Id: Ia44e70948e57c2f19664d874ae005ac39d748f92 Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-16lib/bootmem: tightly couple bootmem_init to bootmem_write_memory_tableAaron Durbin
In https://review.coreboot.org/25383 people were confused about the ordering of bootmem calls w.r.t. when entries are exposed to the OS. To alleviate this add a notion of bootmem being initialized. In addition to that, only mark bootmem initialized when bootmem_write_memory_table() is called. Any other calls to bootmem before that will report an error on the console. Change-Id: I5bc31f555038ccabb82d902c54f95858679b1695 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-04-16soc/intel/skylake: Hook up libgfxinitNico Huber
Also base the FSP/GOP related bail-out on the correct Kconfig option to allow adding a VBT along with libgfxinit. Most things should work, what doesn't is backlight control because coreboot misses the settings (moved to FSP and need backporting). Also, Kaby Lake is still unsupported. TEST=Booted yet to be upstreamed Skylake-S port (Kontron/bSL6) both with text and linear framebuffer mode and viewed a FILO menu. Change-Id: I79fbfed7732cf02d054530ea7ec0d34de32836ba Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-04-16google/kahlee: Resume on AC insertionMarshall Dawson
The EC should wake the system from S3 when the AC connector is plugged. BUG=b:77602394 TEST=verify resume on insert with Grunt Change-Id: I4bcaef2fe75283aaa6260b5b9efd408ff4b05f4c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/25647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-16vendorcode/amd/pi/00670F00: Remove unused headersGarrett Kirkendall
Remove unused header files in src/vendorcode/amd/pi/00670F00/agesa_headers.h. This is a first clean up. Hopefully more headers will be removed in other commits. Header files cannot be removed at this time. They are used by files in vendorcode/amd/pi/00670F00/. BUG=b:77944801 BRANCH=none TEST=build Gardenia and Grunt Change-Id: I99b77f6ba41ded30122a01bbe709681312561436 Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25644 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-16vendorcode/amd/pi/00670F00: Remove unused headersGarrett Kirkendall
Remove unused AGESA header files from vendorcode/amd/pi/00670F00/binaryPI/AGESA.c BUG=b:77905293 BRANCH=none TEST=build Gardenia. Change-Id: Ic38424d489dcc37a4074159e33fca0d49c71f701 Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-16mb/google/kahlee: Select BT I2S PAD on ACP_BT_UART muxAkshu Agrawal
bt-pad-enable property is used by kernel driver to set BT I2S PAD on ACP_BT_UART_PAD_SEL mux, for those platforms which use these pins for BT I2S. By default the pins are set for UART. BUG=b:72360151 TEST=Tested playback and capture on audio device connected to BT I2S Change-Id: Id76bfa1fa1dde904f02a03b0c15986ecb1bbcc97 Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/25653 Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-16intel/fsp_broadwell_de: Set FSP serial speed to match coreboot'sDavid Hendricks
This makes FSP use the same baud rate as coreboot so that the user can more easily change it without having to modify the FSP binary. Change-Id: I0084aa9a0394ad7eabdd88809b66fc21a25ba316 Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/25666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-04-16soc/intel/apollolake: Fix CPU address bitsHannah Williams
APL and GLK have 39 address bits Change-Id: I9b761492332c545c13a0594d8f5937ca84bc0699 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/25682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-16Revert "mb/google/reef/sand: Override USB2 phy settings"Katherine Hsieh
This reverts commit aef0d6b0a7ec867ee29acf9e1c695be27626f239. This commit can only pass far-end USB eye diagram but will fail on near-end. Confirmed with Intel we should revert it. Change-Id: I2eb1d5ddb05ca6bbf6512edf48e3e0d8396ce6a7 Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com> Reviewed-on: https://review.coreboot.org/25651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-16soc/intel/apollolake: update cache options for glkAaron Durbin
On glk there's a 4MiB L2 cache all the time. Take advantage of that by initializing a 1MiB cache-as-ram area. BUG=b:72728953 Change-Id: Ia4e777a13607d8b70c05534b0a172f0ec6b04c51 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25645 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-16intel/fsp_broadwell_de: Remove buggy code for SMBus clock gatingWerner Zeh
The pch_smbus_init() function contains code to enable clock gating for the SMBus controller. Unfortunately this code is buggy and leads to a hanging system with the latest microcode version. The hang occurs as follows: The clock gate register is mapped into RCBA space. After reading the RCBA address from the LPC device config space no mask is applied to the value (only bits 31..14 are valid while bit 0 is the enable bit). For this reason the final address is off by one. The old microcodes at least allowed this unaligned access to the RCBA space. With the latest microcode this access leads to CPU hang. Once this is fixed the next issue occurs: After setting the clock gating bit for SMBus (bit 5) the SMBus controller disappears from the PCI bus completely and hence no usage of it is possible anymore. To fix this issue the clock gating code is completely removed as it was intentionally meant to enable clock gating on the SMB_CLK line and not the clock gating on the PCIe interface of the SMBus controller. This issue is known already and was discussed on the mailinglist: [coreboot] BDX-DE PCI init fail https://mail.coreboot.org/pipermail/coreboot/2018-January/085908.html TEST=Boot mc_bdx1 with microcode version M1050663_07000012. Change-Id: Icb86f4516f8a6e72552a44618737e682b0fdef33 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/25652 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-13nb/intel/sandybridge/peg: Add PEG driver stubPatrick Rudolph
Required for other ACPI generators, like the one used for _ROM. * Add ACPI code for PEG10/PEG11/PEG12/PEG60 and include it on all platforms. * Add PCIe driver for PEG. The driver returns ACPI names for ssdt generators. Needs test on real hardware. Change-Id: I96835c43522580c95fd4f250c56bf9438e993bc1 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22337 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-13src/mainboard/kahlee: Turn on keyboard backlight on gruntMartin Roth
Turn on keyboard backlight in romstage to indicate that the system is booting. BUG=b:77921345 TEST=Boot grunt, keyboard backlight comes on. Change-Id: Ib215b19ebdee2f8c4f431af775905eca42436d1c Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/25636 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-13soc/amd/stoneyridge: add a romstage hook for mainboardsMartin Roth
There wasn't previously a way for Stoney platforms to run mainboard specific code in romstage. This adds an early call for configuration and passes along whether the system is currently resuming from S3. BUG=b:77921345 TEST=Build, verify that weak function implementation gets called. Change-Id: Id94855e1084814ec37956e603cd093d70f01a559 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/25635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-13drivers/uart/pl011.c Add read supportMarcello Sylvester Bauer
Implement uart_rx_byte Change-Id: I5a33b3cd4b333fb244bc55747014a301021e25e0 Signed-off-by: Marcello Sylvester Bauer <info@marcellobauer.com> Reviewed-on: https://review.coreboot.org/25623 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-13siemens/mc_apl1: Fix accuracy issue with IDT PMICMario Scheithauer
Due to an accuracy issue on IMON in the IDT PMIC, the reported system power consumption was higher than the actual consumption. To prevent this problem, a logic must be implemented in mainboard_init(). This logic consists of slope and offset as constants for Vcc and Vnn, which need to be programmed by coreboot. This fix compensates for the accuracy issue. Change-Id: I77faf95951d03ac6ce97a6721dba6e8466122a25 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/25585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-04-13Revert "mb/google/reef: Override USB2 phy settings"Tim Chen
This reverts commit 70ba1b7e78930acca578114cdadcbcec367730e8. This commit can only pass far-end USB eye diagram but will fail on near-end. Confirmed with Intel we should revert it. Change-Id: I6de44d5240393409d9ec5835a9de0c23453300f7 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25630 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-13mb/google/kahlee: Fix IRQ routingRichard Spiegel
ACPI interrupt routing file routing.asl is not reflecting AGESA settings to the NB Interrupt Routing Registers. The AGESA settings are: Device self INTA INTB INTC INTD GPP 0 23 0 1 2 3 GPP 1 24 8 9 10 11 GPP 2 25 16 17 18 19 GPP 3 26 24 25 26 27 GPP 4 23 3 0 1 2 HDA none 22 23 20 21 GBIF none 6 7 4 5 Fix the routing table, considering that NB IOAPIC starts at interrupt 24. BUG=b:74104946 TEST=Build and boot to a modified grunt board to enable the emmc. Then used "cat /proc/interrupts" to get active interrupts. Also checked IOAPIC redirection registers, which are now being programmed. Change-Id: I60847c46f3f938f9e97d7b323b27d20e36aa2d02 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-133rdparty/libgfxinit: Update submodule pointerNico Huber
Update libgfxinit to current master. Changes include: * a fix to decode the size stolen memory correctly on pre-SandyBridge hardware, * a PCI id based generation check, obsoleting the old check based on PCH audio ids, * some minor improvements around rarely used DDI ports (D and E), and * added support for tiled and rotated framebuffers on Skylake+ hardware (less interesting for coreboot, I guess?). TEST=Booted kontron/ktqm77 (Ivy Bridge) and pending kontron/bsl6 (Skylake) both with text and linear framebuffers and observed FILO's prompt showing up. Change-Id: I9a3c35c60b9edf8775f3a489df7577092910e127 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/25453 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-13Revert "mb/google/coral: add usb2 phy setting override for some variants"Tim Chen
This reverts commit 06e3e1f055593bd2e2906f43040a703bc471cde4. This commit can only pass far-end USB eye diagram but will fail on near-end. Confirmed with Intel we should revert it. Change-Id: Ie987061e27996b0acc8345bf9aadb42d2c940808 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25629 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-13mb/scaleway/tagada: Document what the selected SMBIOS enclosure type meansJonathan Neuschäfer
This makes the Kconfig file more informative to read. Change-Id: Icdf4184c8db9cfed4863d9e9f3b714d67f44a4bd Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-04-12include/memory_info.h: Change serial number field from 5 bytes to 4Raul E Rangel
dimm_info.serial had a strange contract. The SPD spec defines a 4 byte serial number. dimm_info.serial required a 4 character ascii string with a null terminator. This change makes the serial field so it matches the SPD spec. smbios.c will then translate the byte array into hex and set it on the smbios table. There were only two callers that set the serial number: * haswell/raminit.c: already does a memcpy(serial, spd->serial, 4), so it already matches the new contract. * amd_late_init.c: Previously copied the last 4 characters. Requires decoding the serial number into a byte array. google/cyan/spd/spd.c: This could be updated to pass the serial number, but it uses a hard coded spd.bin. Testing this on grunt, dmidecode now shows the full serial number: Serial Number: 00000000 BUG=b:65403853 TEST=tested on grunt Change-Id: Ifc58ad9ea4cdd2abe06a170a39b1f32680e7b299 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/25343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-12mb/google/octopus: Configure SMI for ESPIShaunak Saha
This patch enables EC SMI when ESPI is enabled. BUG=b:77857802 TEST= SMI is working in depthcharge. Change-Id: I52726194b8346488e5ad781e78e33c5d286d132f Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/25569 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-11soc/amd: Fix generating SMBIOS Type 17Raul E Rangel
The converter was setting SMBIOS values when dimm_info expects SPD values. dmidecode now shows the following: Memory Device Array Handle: 0x0000 Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 8192 MB Form Factor: SODIMM Set: None Locator: Channel-0-DIMM-0 Bank Locator: BANK 0 Type: DDR4 Type Detail: Synchronous Speed: 933 MT/s Manufacturer: Hynix/Hyundai Serial Number: 00000000 Asset Tag: Not Specified Part Number: HMAA51S6AMR6N-UH Rank: 1 Configured Clock Speed: 933 MT/s Minimum Voltage: Unknown Maximum Voltage: Unknown Configured Voltage: Unknown Example debug output: AGESA TYPE 17 DMI INFO: Handle: 1 TotalWidth: 64 DataWidth: 64 MemorySize: 8192 DeviceSet: 0 Speed: 1200 ManufacturerIdCode: 44416 Attributes: 1 ExtSize: 0 ConfigSpeed: 933 MemoryType: 0x1a FormFactor: 0xd DeviceLocator: DIMM 0 BankLocator: CHANNEL A SerialNumber(8): ' 00000000' PartNumber(20): 'HMAA51S6AMR6N-UH ' CBMEM_ID_MEMINFO: dimm_size: 8192 ddr_type: 0x1a ddr_frequency: 933 rank_per_dimm: 1 channel_num: 0 dimm_num: 0 bank_locator: 0 mod_id: 44416 mod_type: 0x4 bus_width: 3 serial: 0x00000000 module_part_number(18): 'HMAA51S6AMR6N-UH ' The serial number we get from AGESA (at least on my board) is always 00000000. I'm assuming this is because the SPD info is compiled in. `mosys memory spd print all` is still failing though. I will look into that next. BUG=b:65403853 BRANCH=dimm-info TEST=Test output above Change-Id: I076bc3f965f81a9374c8976da48c7fdce014dc0c Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/25304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-11lib/memrange: Introduce method to clone memrangePatrick Rudolph
Add a new method to clone an existing memrange with all of its entries. Required for new bootmem type LB_MEM_RAM_DONT_OVERLAP. Change-Id: I64b27bf2611ca310385ef680f030a3e4aa0c2680 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25582 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-11mb/google/octopus: enable MRC recovery cacheAaron Durbin
Enable the recovery cache to speed up recovery flows. Also enable clearing of the normal mrc cache on recovery forced retrains. BUG=b:77871444 TEST=went into recovery twice. 2nd time it boots faster. Change-Id: Idfce42ac835637fa521545fadfedecd65df91d4c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-11mb/google/octopus: Select DRIVERS_SPI_ACPIFurquan Shaikh
This change selects DRIVERS_SPI_ACPI which is required to add SSDT node for SPI TPM. BUG=b:75306520 BRANCH=None TEST=None Change-Id: I0728062dae017522ba91a4b5cb16acf9f6bf4f28 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25611 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-11src/lib/dimm_info_util.c: Add methods to convert from SMBIOS to SPDRaul E Rangel
AMD AGESA returns DIMM info in SMBIOS format. dimm_info expects the data in SPD format. These methods will be used to update amd_late_init.c so it sets the correct values. BUG=b:65403853 TEST=Built and booted grunt. Methods are not called in this commit. So they were tested with the later commit by verifying the output of dmidecode. Change-Id: Id9fa98e9aad83dfd0a86f45e18b3c312665dce9b Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/25412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-11src/amd/stoneyridge: Fix a typo (EDGEL_TRIG -> EDGE_TRIG)Jonathan Neuschäfer
Fixes: 2269a3c328 ("soc/amd/stoneyridge: Add functions for GPIO interrupts") Change-Id: I5730259bc6819defc482d31644e1f476679257b2 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25588 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Chris Ching <chingcodes@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-11mainboard/intel/cannonlake_rvp: include correct SND related DT entriesSathyanarayana Nujella
For cannonlake_rvp, want to support two sound configurations based on relevant daughter board connected (either of these configurations: SND_MAX98373_NHLT and SND_MAX98357_DA7219_NHLT). By default SSDT included all codec entries. This patch corrects and includes relevant codec entries in SSDT BUG=None BRANCH=master TEST=Verify 'emerge-cnlrvp coreboot' compiles successfully. Change-Id: I4f9487f3a81ef2d24315f75ec1d34bfab8560224 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/24918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-11siemens/mc_apl1: Make DRAM configuration more flexibleMario Scheithauer
By storing the FSP-M DRAM configuration parameter in the hwinfo block, one becomes more flexible in case of a change of the DRAM type. The configuration data from hwinfo block is a one-to-one representation of the FSPM_UPD data starting with parameter 'Package' (offset 0x4d) and ending before parameter 'Ch0_Bit_swizzling' (offset 0x88). Change-Id: I58c1df0954a436710ecb59487ece07a0832b0de6 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/25586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-04-11amd/stoneyridge: Reorder temp mtrr for flashMarshall Dawson
Relocate setting the temp range MTRR, for the SPI flash device, to after completion of mp_init. The mp_init functionality mirrors the BSP's exact MTRR settings into the AP cores. The ranges need to be the correct calculated values and not some temporary setting. This solves an MTRR sync issue on APUs with more than two cores, i.e. more than a single compute-unit. MTRRs within a CU are shared so the AP always stays in sync. BUG=b:77457944 TEST=run on Kahlee Change-Id: Idc4cccdf721e252bc87d6cba62a3406a9f19b940 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/25575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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