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2020-04-20drivers/pc80/rtc: Drop CMOS_POST_EXTRA optionKyösti Mälkki
Change-Id: I379a5664776624600ff1c2919bffa77c877d87ab Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-20drivers/pc80/rtc: Clean up post_log_path()Kyösti Mälkki
Change-Id: I605d39d907e083e73af4c72607216384e7ce166a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38190 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-20drivers/elog,pc80: Move cmos_post_log()Kyösti Mälkki
Do this to remove elog header dependency from pc80/ and remove some preprocessor guards. Change-Id: I98044a28c29a2b1756fb25fb593f505e914a71c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-20mb/intel/jasperlake_rvp: Add SD Card gpio config for JSLRVPRonak Kanabar
Configure write protect and card detect SD Card GPIO for JSLRVP as per schematics. BUG=None BRANCH=None TEST=Build, boot JSLRVP and verified SD Card detection. Change-Id: I8114d6980a2a542538b05f812ca2cffc15c88c22 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39492 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-20vboot/secdata: remove retries, readback, and CRC checkJoel Kitching
Depthcharge trusts that our TPM driver is working reliably, and so should we. Also remove CRC check -- the value returned by antirollback_read_space_firmware() is dropped in vboot_logic.c verstage_main(), and vboot handles this check internally. BUG=b:124141368, chromium:972956 TEST=make clean && make test-abuild BRANCH=none Change-Id: I5d3f3823fca8507fd58087bb0f7b78cfa49417ab Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-04-20vboot: remove leftover TPM_PCR_GBB constantsJoel Kitching
These constants were left behind after the code using them was relocated in CB:34510. BUG=b:124141368, chromium:972956 TEST=make clean && make test-abuild BRANCH=none Change-Id: I6ce7c969a9e9bdf6cdce3343ba666a08b3521f27 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-04-20mb/tglrvp: Configure intel common configWonkyu Kim
Configure lockdown and i2c speed setting. BUG:b:151161585 BRANCH=none TEST=build and boot tglrvp and check FSP logs to lockdown parameters Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Id7a1e9bd94ff86faa390b5de0518e8b3cb668bff Reviewed-on: https://review.coreboot.org/c/coreboot/+/40116 Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-20mb/google/deltaur: Enable Cirque touchpad for DeltanEric Lai
Reference Arcada to add device tree for Cirque touchpad. BUG=b:152931802 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia354702c8054b5826d45896f7bff268335726028 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-20mb/google/drallion: Increase Melfas touchscreen stop delay to 115msJohn Su
Modify stop_delay as 115ms to waiting for Melfas device I2C interface ready after touch fw auto update and rebind driver. BUG=b:153708773 BRANCH=drallion Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Ib392190d2b4188ee228d8ca4873e03176d2f127f Reviewed-on: https://review.coreboot.org/c/coreboot/+/40357 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-19nb/intel/sandybridge: Refactor get_mem_min_tckAngel Pons
It is not necessary to pass its value around various function calls. Move it closer to where it is actually used, so as to make it static. Also, use config_of_soc and flip the branches of the first conditional. Tested on Asus P8Z77-V LX2, still boots. Change-Id: I5c49c943c87218d4d40d3168bd8b7b900b0ec2e9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39851 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-18drivers/pc80/rtc: Turn comment into warning messageNico Huber
Change-Id: I80786042b1c464268cae8093bd5d3e8d73be5aee Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-18mb/qemu-i440fx,q35: Fix option tableNico Huber
Reserve bytes 50 and 55 as they are handled as century bytes by QEMU. Change-Id: I9271253bce560d4ec8a51a24c45473acec469187 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-18mb/qemu-q35: Select `HAVE_CMOS_DEFAULT`Nico Huber
Change-Id: If4c4dc9467154a18168550538fc8e655636e87a0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-18mb/intel/harcuvar: Fix board_id() return typeJacob Garber
The weak definition of board_id() in coreboot_table.c returns a uint32_t, so update this function to match. This fixes a compiler error when using LTO. Change-Id: I6ad03ecedcf4a4d9f0c917cdc760f81ddde06d11 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Guckian Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-18vc/amd/agesa/f15tn,f16kb: Fix array typesJacob Garber
These variables are declared to be arrays of MICROCODE_PATCHES_4K (which is a struct containing a UINT8 array). However, the actual definitions of these arrays ignore the wrapping struct and just use the underlying UINT8 arrays directly, which causes a compiler error when using LTO because of the type mismatch. Fix the type declaration so that it matches. Change-Id: I6bef27507092fe72fe2f836c427ebb2c19009e78 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-18vc/amd/agesa/f14: Fix array lengthJacob Garber
This array is declared to have length MAX_FF_TYPES (aka 6) in several other places, so update it here so the length matches. This fixes a -Wlto-type-mismatch compiler error when using LTO. Extending the length is harmless, since the only code that uses this array will stop once it reaches the NULL pointer. Change-Id: Ie00e969fa8cda88a934bf416c8775f7ae0b2747e Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39014 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-18mb/lenovo/t420(s): Do minor cosmetic changesPeter Lemenkov
Align the whitespace and do some cosmetic changes. This makes it easier to fold these two boards into a variant setup. Change-Id: I53bdd90ae47b52dfdfec27229c6b904487fa2081 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-18asus/p2b*: Declare \_SB.PCI0.MBRS in DSDTKeith Hui
sb/intel/i82371eb/isa.c has code that fills this path with CPU info. Because it was not declared in the DSDT, Linux kernel 4.4.18 as used in Slackware 14.2 complains. Change-Id: Ib85dd02504b068bb7ea71be2f22e425f3831595a Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38601 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-18i82371eb: Drop KB/Mouse/FDC declarationsKeith Hui
These are declared by superio. Change-Id: I1db4aca7d682ec298b8f53cfab6ffe661e8ff6e0 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38600 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-18asus/p2b*: Move serial init into mainboard bootblockKeith Hui
With this bootblock messages are transmitted over serial too. TEST=Serial messages transmitted normally on asus/p2b-ls. Change-Id: I6f3ee68e7c76a8c6db6d75956e6a7fb75ef83850 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-18asus/p2b-ds: Transform into variantKeith Hui
TEST=build with BUILD_TIMELESS=1, binary does not change Change-Id: I864f939a84ee9e90013ba9d3fcc8a7e4bf03e4ee Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39904 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-18asus/p2b-d: Transform into variantKeith Hui
TEST=build with BUILD_TIMELESS=1, binary does not change Change-Id: I1161c726c8c752b5b1e152e1617811989631096e Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39903 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-18asus/p2b-ls: Transform into variantKeith Hui
Boot tested on hardware. Change-Id: I24afd67dada135a8c2597f5ac1c7e91ce43897c9 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39901 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-18soc/intel/*/vr_config.c: Use __func__ in error messageAngel Pons
The error message has been copy-pasted across various functions, so it is nearly impossible to know which function printed it. So, use __func__ to print that information. Change-Id: I55438c2b36cc3b21f3f168bf98b0aca5fd50bbbc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40446 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-18vc/amd/agesa/f14: Fix function return typeJacob Garber
F14GetNbCofVidUpdate() is declared elsewhere to be of type F_CPU_IS_NBCOF_INIT_NEEDED, which is supposed to return a boolean value (not an AGESA status). This is fixed in the corresponding f15tn and f16kb code, so apply the same change here. This fixes a compiler error when using LTO. Change-Id: Ifc44e2c0467f8bd1f537b5a69c501ba51053d3d9 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-18soc/amd/picasso: Move BERT region to cbmemMarshall Dawson
Allocate storage for the BERT reserved memory in cbmem, and add it in response to a romstage hook. Add a Kconfig option for adjusting the size reserved. This is different from the Stoney Ridge implementation where it was intentionally oversized to ease MTRR use and to keep TSEG aligned. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4759154d394a8f5b35c0ef0a15994bbef25492e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38694 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-18mb/ocp/tiogapass: Pull POST complete pinBryantOu
Tioga Pass platform use GPIO pin of GPP_B20 for POST complete, BIOS needs to configure this pin for BMC to poll, so it knows when to start to access other components. Tested=Read GPIO status (GPIOAA7) in OpenBMC, the value is 0, the command and result are shown as below, root@bmc-oob:~# cat /tmp/gpionames/FM_BIOS_POST_CMPLT_N/value 0 root@bmc-oob:~# Change-Id: I134f80153461c5acd872587038a2207586b658dd Signed-off-by: BryantOu <Bryant.Ou.Q@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-04-17ec_sync: Run EFS2 in romstagednojiri
EFS2 allows EC RO to enable PD for special cases. When doing so, it sets NO_BOOT flag to avoid booting the OS. AP needs to get NO_BOOT flag from Cr50 and enforce that. This patch makes verstage get a boot mode and a mirrored hash stored in kernel secdata from Cr50. This patch also makes romstage write an expected EC hash (a.k.a. Hexp) to Cr50 (if there is an update). BUG=b:147298634, chromium:1045217, b:148259137 BRANCH=none TEST=Verify software sync succeeds on Puff. Signed-off-by: dnojiri <dnojiri@chromium.org> Change-Id: I1f387b6e920205b9cc4c8536561f2a279c36413d Reviewed-on: https://review.coreboot.org/c/coreboot/+/40389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-04-17TPM: Add tlcl_cr50_get_boot_modednojiri
tlcl_cr50_get_boot_mode gets the boot mode from Cr50. The boot mode tells coreboot/depthcharge whether booting the kernel is allowed or not. BUG=b:147298634, chromium:1045217, b:148259137 BRANCH=none TEST=Verify software sync succeeds on Puff. Signed-off-by: dnojiri <dnojiri@chromium.org> Change-Id: Iadae848c4bf315f2131ff6aebcb35938307b5db4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40388 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-17soc/intel/tigerlake: Remove eMMC/SD supportDuncan Laurie
Tigerlake platform does not have built in eMMC/SD support so all this code is unused and can be removed. Change-Id: I70ff983d175375171d5a649378f32f1062c0876d Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40372 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-17soc/intel: Disable config option for SCS by defaultDuncan Laurie
The eMMC/SD interface is not present in all Intel platforms so this change removes the default enable for the storage controller and instead enables it in the specific SoCs that do provide it. Currently this includes all platforms except Tigerlake. Change-Id: I8b6cab41dbd5080f4a7801f01279f47e80ceaefd Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-17ec/google/chromeec: Update the USBC ACPI device hierarchyKarthikeyan Ramasubramanian
Type C connector class driver in kernel (v5.4) expects the Type C ACPI device under ChromeEC ACPI device scope. Currently the Type C ACPI device is populated under ChromeEC device's parent. This leads to incorrect casting of Type C's parent device and hence a crash. Move the Type C device under ChromeEC ACPI device. BUG=b:153518804 TEST=Build and boot the mainboard. Ensure that the USBC ACPI device is populated under ChromeEC ACPI device. Scope (\_SB.PCI0.LPCB.EC0.CREC) { Device (USBC) { Name (_HID, "GOOG0014") // _HID: Hardware ID ... } } Change-Id: I628489bc420d7a3db4ad3cb93d085d568c6de507 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-17intel/common: add a macro to set ownership for GPIMaxim Polyakov
Adds a new macro that allow to set the DRIVER or ACPI as host software ownership for the GPI pad using the parameter own. Thus, this macro can define more variants for pad configuration than others. This is necessary to describe in more detail the configuration for the Tioga Pass OCP server [1] and other boards. In addition, these changes will be used to automatically generate macros [2] and great simplify this task. [1] https://review.coreboot.org/c/coreboot/+/39427 [2] https://review.coreboot.org/c/coreboot/+/35643 Change-Id: I9c191fb6935e94da6e296f8fee0b91a973534e1a Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-17ec/google/chromeec: Add host command EC_CMD_GET_KEYBD_CONFIGRajat Jain
Add command to query the EC for the keyboard layout. Also add supporting data structures for the exchange. Signed-off-by: Rajat Jain <rajatja@google.com> Change-Id: I26aff6dd0e701e0cecb3b66bc54c5a23688f0109 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-16vc/amd/fsp/picasso: Add file for GUIDsMarshall Dawson
Begin a file for GUIDs used by the FSP. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ied5c5085ea8ed55439192be8a44fa401aeb559a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38697 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-16soc/amd/common/psp: refactor psp_print_cmd_status parametersFelix Held
psp_print_cmd_status only needs data from the mbox buffer header and not the whole buffer. This avoids type casts when the buffer type isn't mbox_default_buffer. BUG=b:153677737 Change-Id: I8688b66fefe89fc4f3ce2207d4360ceb2dbaef12 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40412 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-16soc/amd/picasso: Notify PSP system is going to sleep stateMarshall Dawson
BUG=b:153677737 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ic72bd5f5710181ca4f282feba5f7531b098c907a Reviewed-on: https://review.coreboot.org/c/coreboot/+/40298 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-16soc/amd/common/psp: Add notify_sx_infoFelix Held
Add the command to tell the PSP the system is going to a sleep state. BUG=b:153677737 Change-Id: I50da358e1f8438b46dbb1bda593becf6dd4549ea Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/2020367 Reviewed-on: https://chromium-review.googlesource.com/2110764 Reviewed-on: https://chromium-review.googlesource.com/2121159 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-16soc/amd/psp: Add SmmInfo commandMarshall Dawson
Implement the MboxBiosCmdSmmInfo function to inform the PSP of the SoC's SMM configuration. Once the BootDone command is sent, the PSP only responds to commands where the buffer is in SMM memory. Set aside a region for the core-to-PSP command buffer and the PSP-to-core mailbox. Also add an SMM flag, which the PSP expects to read as non-zero during an SMI. Add calls to soc functions for the soc to populate the trigger info and register info (v2 only). Add functions to set up the structures needed for the SmmInfo function in Picasso support. Issue a SW SMI, and add a new handler to call the new PSP function. BUG=b:153677737 Change-Id: I10088a53e786db788740e4b388650641339dae75 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-16intel/common/block/lpc: Add new device IDs for Lewisburg PCHBryantOu
Add C621A, C627A and C629A SKU IDs. C621A is used in the Whitley Product. We need to add device ID for setting LPC resources. Refer to Intel C620 series PCH EDS (547817). Change-Id: I19a4024808d5aa72a9e7bd434613b5e7c9284db8 Signed-off-by: BryantOu <Bryant.Ou.Q@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40395 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-16mb/google/hatch/var/kindred: Override VBT selection for kledDavid Wu
Override VBT to fix CRC error issue with psr2 panel for kled. Cq-Depend: chrome-internal:2877637 BUG=b:145963505 BRANCH=hatch TEST=FW_NAME=kindred emerge-hatch coreboot chromeos-bootimage Change-Id: If201d449e910f80dc514c142aec4808a44fa31a9 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-04-16ec/google/chromeec: add BOARD_VERSION CBI supportAaron Durbin
Obtaining the CBI_TAG_BOARD_VERSION value wasn't in the code base. Add the binding for it so it can be used. BUG=b:153640981 Change-Id: Ie2f289631f908014432596448e56b5048a196a10 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-16mb/google/puff: Add variant specific DPTF parametersTim Chen
Modify DPTF parameters for OEM EVT build from thermal team. BUG=b:153589525 BRANCH=None TEST=emerge-puff coreboot chromeos-bootimage and boot on puff board Change-Id: I36db172e4d2ccc854856641c510cff9fe04ea235 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-04-15mb/google/hatch: Add Kaisa variantAndrew McRae
A verbatim copy of variants/puff V.2: rebased on duffy. BUG=b:152951180 BRANCH=none TEST=none Change-Id: I7ea28e96c8b6867e17097a8bfab848928195654d Signed-off-by: Andrew McRae <amcrae@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2020-04-15mb/google/hatch: Add Duffy variantEdward O'Callaghan
A verbatim copy of variants/puff. BUG=b:152951181 BRANCH=none TEST=none Change-Id: I9ac262bba60a8d0059722e947ed1b47dddb94f55 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40223 Reviewed-by: Daniel Kurtz <djkurtz@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-15mb/kontron/ktqm77: Extend SATA CMOS option with "legacy" modeNico Huber
TEST=Booted Linux 2.6.12 w/o native Intel IDE driver and confirmed working SATA drive. Change-Id: I85f72a172bcbc4c8b4bfb7a2baed7c6739b2d9f8 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-15sb/intel/bd82x6x/sata: Clean up IDE modesNico Huber
Don't set legacy timing values that don't affect the hardware but enable the OOB retry mode as already done on the AHCI path. Change-Id: I0b078d7790ca801a89066ef6a161d900be5eb778 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-15trogdor: add support for Bubs variantT Michael Turney
Change-Id: I4d9bc98863c4f33c19e295b642f48c51921ed984 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37069 Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-15Do not select USE_BLOBSNico Huber
The `USE_BLOBS` config only exists for idealistic reasons. If we would allow us to use blobs by default, we wouldn't need that option and could just always do it. It's generally debatable for the project as a whole, but not per board/subject. Change-Id: I8591862699aef02e5a4ede32655fc82c44c97555 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-15soc/intel/apl/report_platform.c: Fix typoAngel Pons
"Aplollolake" => "Apollolake" Change-Id: I1881d40b5f71d07d5d217b4380241cc14467fb1a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40407 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-02 21:15:42 +0000