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2010-11-07DSDT.asl should not report the AMD SB600/SB700 RTC as Intel PIIX4Scott Duplichan
compatible. The extended cmos is accessed differently for AMD and Intel RTCs. Not sure what if any OS cares about this distinction, but non-Intel compatible seems like a safer way to report the AMD RTC. Tested with Win7 on Mahogany_fam10 and kino-780am2-fam10. Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6046 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07Should be part of 6044. I forgot to add the directory :/Tobias Diedrich
This adds the m2v directory and necessary files to src/mainboards/asus and adjusts the Kconfig. Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6045 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07This adds the m2v directory and necessary files to src/mainboards/asus andTobias Diedrich
adjusts the Kconfig. Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6044 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07Depends on the "Introduce get_vt8237_lpc() function" andTobias Diedrich
"Use get_vt8237_lpc() in vt8237_sb_enable_fid_vid()" patches. This adds VT8237A specific VLINK/LPC init in vt8237r_early_smbus.c I ran some tests and apparently both the | /* So the chip knows we are on AMD. */ | pci_write_config8(devctl, 0x7c, 0x7f); and | /* | * Allow SLP# signal to assert LDTSTOP_L. | * Will work for C3 and for FID/VID change. | */ | outb(0x1, VT8237R_ACPI_IO_BASE + 0x11); in vt8237r_early_smbus.c are needed on VT8237A, otherwise I get a (non-fatal) fid/vid change error on boot. While vt8237a_vlink_init() in vt8237_ctrl.c is a modified vt8237r_vlink_init(), vt8237a_init() in vt8237r_lpc.c is a modified vt8237s_init(). Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6043 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07This adds the VT8237A LPC pci_locate_device call in vt8237r_early_smbus.cTobias Diedrich
Depends on the "Introduce get_vt8237_lpc() function" patch. Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6042 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07Use get_vt8237_lpc() in vt8237_sb_enable_fid_vid() too.Tobias Diedrich
I broke this out into a seperate part to keep the other half as straight-forward as possible. Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6041 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07Instead of duplicating the pci_locate_device calls multiple times,Tobias Diedrich
add a get_vt8237_lpc() function. Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6040 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07Add pointer to public PCIe bridge documentation onTobias Diedrich
http://linux.via.com.tw/ as VX800 seems to be compatible. Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6039 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07This adds VT8237A specific VLINK/LPC init functions in vt8237_ctrl.cTobias Diedrich
and vt8237r_lpc.c. While vt8237a_vlink_init() in vt8237_ctrl.c is a modified vt8237r_vlink_init(), vt8237a_init() in vt8237r_lpc.c is a modified vt8237s_init(). Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6038 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07Remove empty files added by accident. Sorry about that.Rudolf Marek
Rudolf Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6037 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07Move K8_ALLOCATE_IO_RANGE to Kconfig.Patrick Georgi
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6036 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07This adds the VT8237A LPC device id and the pci_driver struct inTobias Diedrich
vt8237r_lpc.c Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6035 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07FIRST_CPU, SECOND_CPU, TOTAL_CPUS are only used in onePatrick Georgi
other place, and that defines these symbols itself (and identical, too). Drop them. Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6034 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07Fix a few incorrect GIGABYTE board names (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6033 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07ECS P6IWP-Fe: Fix typo, add missing license header.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6032 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07Remove unused defines (UART_*)Patrick Georgi
All other uses of these symbols have their own (identical) definitions. abuild-tested and trivial Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6031 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-06Various Super I/O fixes and corrections.Uwe Hermann
- VIA VT1211: - Add missing LDNs and respective code to handle them. - Add some TODOs for other stuff that needs fixing. - Use VT1211_SP1 instead of hardcoding the LDN number (2). - Fixup pnp_dev_info[] as per datasheet, but some TODOs remain. - Various coding style fixes and changes to u8/u16/etc. - Serverengines Pilot: Various coding style fixes and changes to u8/u16/etc. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6030 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-06Remove comments that are obsolete since r6028.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6029 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-05Move QRANK_DIMM_SUPPORT to Kconfig, removing it from romstage.cPatrick Georgi
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6028 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-05Various PIRQ/MPTABLE/ACPI Kconfig fixes.Uwe Hermann
- Use HAVE_ACPI_TABLES, HAVE_MP_TABLE, and HAVE_PIRQ_TABLE (instead of GENERATE_*) in the board's Kconfig file, as all other boards do. - Add missing HAVE_ACPI_TABLES/HAVE_MP_TABLE/HAVE_PIRQ_TABLE to boards which have the respective files. The only exception: EPIA-M700 doesn't select ACPI, as it doesn't have dsdt.asl. Added a comment that the user is supposed to run the 'get_dsdt' script and edit Kconfig afterwards. - Fix minor warning/error in src/mainboard/msi/ms9652_fam10/acpi_tables.c, now that the file is actually used. - msi/ms9652_fam10: use #include instead of Include() as we usually do now. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6027 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-05Follow-up for r6025, do 0x87 twice in superio.c, too.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6026 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-05According to the description in datasheet of f71889,Zheng Bao
"To enable configuration, the entry key 0x87 must be written to the index port" " -o 4e 87 -o 4e 87 (enable configuration) -o 4e aa (disable configuration) " This piece of text appears in most of the datasheet of fintek superio. It doesnt say it quite clear, but it seems that the 0x87 should be written twice. I tried on f81865, which is not in the coreboot tree yet. If the 0x87 is only written once, you can only R/W the index/data port once. All the subsequent RW will fail. Writing twice will be ok. Plus, in the superiotool, the function enter_conf_mode_winbond_fintek_ite_8787 also write 8787. The fintek superio chips seem to enable the UART automatically when the power is on. So I didnt find it failed to access. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6025 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-05Add Kconfig CPU speed selection to Geode GX2 boards.Nils Jacobs
This is Abuild and boot tested. Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6023 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-05GX2: Define the unused DIMM1 to 0xFF to make it obvious it is a bogus value.Nils Jacobs
This is Abuild and boot tested. Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6022 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-05Remove banner wrapper function and unify print(k) usage.Nils Jacobs
- Drop banner(), use printk()s instead. - Uncomment a few printk()s, if a users doesn't want to see them he/she can lower the debug level. - Replace print_emerg() with printk(BIOS_EMERG) etc. Also change 'Assymetirc' into 'Asymmetric', thanks to Idwer for spotting. This is Abuild and boot tested. Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6021 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-05Fintek and Intel i3100 Super I/O cleanups.Uwe Hermann
- Drop commented out "config chip.h" and a duplicate link to a datasheet. - F71805F -> F71805F/FG, to mention all variants. - Use u8/u16/ etc. everywhere. - Add a missing (C) line. - Fix up a bunch of pnp_dev_info[] structs according to the datasheets. - Fintek F71889: Drop res1/PNP_IO1 from KBC, there's no 0x62/0x63 register pair on this Super I/O. - Fintek F71863FG: This Super I/O _does_ have a keyboard/mouse LDN, add the respective code in superio.c. Also: Add missing LDNs to f71863fg.h. - i3100: Add some more comments and datasheet infos. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6020 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-04Various cosmetic and coding style fixes in src/devices.Uwe Hermann
Also: - Improve a few code comments, fix typos, etc. - Change a few more variable types to u8/u16/u32 etc. - Make some very long lines fit into 80chars/line. - Drop a huge duplicated comment, use "@see" to refer to the other one. - Reduce nesting level a bit by restructuring some code chunks. - s/Config.lb/devicetree.cb/ in a few places. Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6019 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-04Add a rom_enable() function to via/vt8231 and call it from via/epia/romstage.cUwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6018 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-03Add Fintek F71889 Super I/O support.Alec Ari
Untested, but should work mostly (even though some TODOs remain). Signed-off-by: Alec Ari <neotheuser@ymail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6017 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-03Remove some unused code from gx2/raminit.c.Nils Jacobs
This is Abuild and boot tested. Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6016 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-03Clean up some more comments and white space in model_gx2/cpureginit.c.Nils Jacobs
This is Abuild and boot tested. Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6015 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-03Clean up some comments and white space in gx2/northbridgeinit.cNils Jacobs
and gx2/raminit.c. This is Abuild and boot tested. Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6014 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-02Need to clear downstream read cycle retry bit, or the bus scan willTobias Diedrich
hang. Also need to set lane config to 0x00 for autonegotiation. Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6013 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-02This adds pci device ids and pci_driver structs for the K8T890 CFTobias Diedrich
variant. It also adds additional dev_find_device calls in k8t890_ctrl.c for subfunctions 3 and 7. Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6012 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-01Change Geode GX2 to use the auto DRAM detect code from Geode LX.Nils Jacobs
Also, change the GX2 boards to use it. Add a processor speed setting function in human readable MHz and remove the useless and broken PLLMSR settings (the processor speed was hardcoded to 366MHz in pll_reset.c). Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6011 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-01Remove some unused code.Nils Jacobs
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6010 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-01GX2: Clean up some white space and comments.Nils Jacobs
Also, add a copyright header to pll_reset.c. Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6009 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-01GX2: Change MSR register numbers into more descriptive names.Nils Jacobs
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6008 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-31Remove definitions of ACPI_SSDTX_NUM to 0, that's the default anyway.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6007 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-31Remove incorrect IOAPIC lines from some mptable.c files.Uwe Hermann
- via/epia-n/mptable.c - intel/eagleheights/mptable.c (commented out anyway) - asus/p2b-d/mptable.c - asus/p2b-ds/mptable.c Some files still incorrectly contain some smp_write_ioapic() lines from the original mptable utility target (Supermicro P4DPE), which has one IOAPIC in the southbridge (Intel ICH3-S), two IOAPICs contained in the first P64H2, and two more in the second P64H2, i.e. 5 IOAPICs in total. However, none of the boards where this chunk of code is present has multiple IOAPICs (and even if they had, the PCI devices where those are located would probably be different anyway), so drop the incorrect mptable.c contents. Also drop the lines from the mptable utility, so that future mptable.c files don't incorrectly inherit any of this stuff. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Jonathan Kollasch <jakllsch@kollasch.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6006 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-31Fix AMD family 10h engineering sample is reported as 'thermal test kit'.Scott Duplichan
Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6005 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-30Mptable related fixes for ASUS P2B-DS.Uwe Hermann
- Add "select IOAPIC" in the board's Kconfig file. - Set CONFIG_MAX_PHYSICAL_CPUS to 2 on the board. There are two CPU sockets (Slot 1) and each CPU can only have one core, multi-core CPUs didn't exist in that era (CONFIG_MAX_CPUS was set to 2 already). - Drop useless/duplicated enable_lapic() call from ASUS P2B-DS's romstage.c, that function is always called if either CONFIG_SMP and/or CONFIG_IOAPIC are set. - Rework ASUS P2B-DS mptable.c to fix a number of things: - Convert it to use mptable_write_buses() as all mptable.c files should do. - Fix incorrect IOAPICID (it's 0x11 for the external 82093AA IOAPIC). - Fix a bunch of hardcoded bus IDs, remove incorrect entries, etc. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6004 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-29Use common code to set PCI subsystem in mcp55.Jonathan Kollasch
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6003 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-29Deduplicate ck804 subsystem-setting functionality.Jonathan Kollasch
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6002 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-29Drop duplicate HAVE_ACPI_TABLES (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6001 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-28The no point in having a non-NULL ops_pci pointer when the set_subsystem ↵Jonathan Kollasch
operation within is NULL anyway. Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net> Acked-by: Jonathan Kollasch <jakllsch@kollasch.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6000 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-28Fix broken build due to missing #if CONFIG_IOAPIC.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5999 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-28Add IOAPIC support for Intel 82371EB and fixup SMP on ASUS P2B-D.Uwe Hermann
- Add enable_intel_82093aa_ioapic() which enables IOAPIC usage in the Intel 82371EB southbridge (sets the proper chip-select) and sets an IOAPIC ID. - We only call enable_intel_82093aa_ioapic() if a board does "select IOAPIC" as on 82371EB-based boards the IOAPIC is an external chip (not integrated in the southbridge) and it's only populated on multi-CPU boards. That is, we cannot unconditionally enable it, only on SMP-capable boards. - Due to the reason explained above, remove "select IOAPIC" from src/southbridge/intel/i82371eb/Kconfig, and add it to src/mainboard/asus/p2b-d/Kconfig. - Also set CONFIG_MAX_PHYSICAL_CPUS to 2 on ASUS P2B-D. There are two CPU sockets (Slot 1) and each CPU can only have one core, multi-core CPUs didn't exist in that era (CONFIG_MAX_CPUS was set to 2 already). - Drop useless/duplicated enable_lapic() call from ASUS P2B-D's romstage.c, that function is always called if either CONFIG_SMP and/or CONFIG_IOAPIC are set. - Rework ASUS P2B-D mptable.c to fix a number of things: - Convert it to use mptable_write_buses() as all mptable.c files should do. - Fix incorrect IOAPICID (it's 0x11 for the external 82093AA IOAPIC). - Fix a bunch of hardcoded bus IDs, remove incorrect entries, etc. This is build-tested on ASUS P2B-D, and also boot-tested successfully there. On Linux I now get two entries in /proc/cpuinfo (where only one appeared before this patch), i.e. both populated CPUs are found. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-27Enable CK804 AC'97 audio interface and explicitly enable NIC on A8N-E.Jonathan Kollasch
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5997 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-27Correct an apparent copy-paste error that shows up at compile time onJonathan Kollasch
boards using ck804_early_setup.c that select CK804_USE_NIC. Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5996 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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