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2015-11-20google/veyron_danger & veyron_emile: Fix Kconfig warningsMartin Roth
These platforms needed to be adjusted to fix various Kconfig warnings. Both platforms needed MAINBOARD_HAS_NATIVE_VGA_INIT because they're setting MAINBOARD_DO_NATIVE_VGA_INIT. veyron_emile needed a few symbols that depend on CHROMEOS to be moved into a new config CHROMEOS section. This matches the other CHROMEOS platforms. veyron_danger needed to select MAINBOARD_HAS_CHROMEOS before the CHROMEOS symbol was set. Change-Id: I8c7f594ba572a02513a68095c16314006fb4e379 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12462 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-11-20google/lars & intel/kunimitsu: Fix Kconfig warningsMartin Roth
EC_SOFTWARE_SYNC depends on CHROMEOS, so move it into the CHROMEOS section. This fixes the kconfig warning: warning: (CHROMEOS && BOARD_SPECIFIC_OPTIONS ...) selects EC_SOFTWARE_SYNC which has unmet direct dependencies (MAINBOARD_HAS_CHROMEOS && CHROMEOS && VBOOT_VERIFY_FIRMWARE) Change-Id: I459f48fd18c7568c4584df7d4aefa69dec3e4907 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12460 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-19nb/intel/sandybridge/raminit: Factor out code into toggle_io_resetPatrick Rudolph
Found while doing code review. Use a function to toggle IO reset signal. Change-Id: I4cb0885ed9be763fbc4069e4d015a36a7183c823 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: http://review.coreboot.org/11916 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-11-19vendorcode/google/chromeos: Cache VPD data into CBMEMHung-Te Lin
There are few drawbacks reading VPD from SPI flash in user land, including "lack of firmware level authority" and "slow reading speed". Since for many platforms we are already reading VPD in firmware (for example MAC and serial number), caching the VPD data in CBMEM should will speed up and simplify user land VPD processing without adding performance cost. A new CBMEM ID is added: CBMEM_ID_VPD, referring to a structure containing raw Google VPD 2.0 structure and can be found by the new LB_TAG_VPD in Coreboot tables. BRANCH=smaug BUG=chrome-os-partner:39945 TEST=emerge-smaug coreboot chromeos-bootimage # and boots successfully. [pg: lots of changes to make it work with what happened in upstream since 2013] Change-Id: If8629ac002d52abed7b480d3d06298665613edbf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 117a9e88912860a22d250ff0e53a7d40237ddd45 Original-Change-Id: Ic79f424a6e3edfb6c5d168b9661d61a56fab295f Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/285031 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12453 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-11-19edid: Don't half parse (and wrongly print) more detailed timingsDouglas Anderson
The EDID parsing code continued to update _some_ fields of the output edid but not others if "did_detailed_timing" was already set. It also then went on to print out this halfway mix of modes each time, despite the fact that it didn't really update everything. Let's fix that. We'll reduce code changes by using a temporary copy of data in detailed_block() and then we'll copy it back if we decide we should update. BRANCH=none BUG=chrome-os-partner:46998 TEST=No more bogus printouts Change-Id: Idbfa233e0997244c22ef21c892c4473a91621821 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4d69999cdd7ce3cd2c9332ab3f22ea8eb4b6f2e9 Original-Change-Id: Ia72cac7fda2772f26477e43237678fa30feca584 Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/309541 Original-Reviewed-on: https://chromium-review.googlesource.com/309609 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/12444 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-19edid: Use a better mode for 640x480Douglas Anderson
The hardcoded clock value for 640x480 was 25.175 MHz. That's a valid clock to use, but is quite hard to make a non-jittery clock from PLLs. It's much easier to make 25.200 MHz, so let's do that. The difference between the two modes is 59.9 Hz vs. 60 Hz and it seems better to make a non-jittery 60 Hz rather than a very jittery 59.9 Hz. BRANCH=none BUG=chrome-os-partner:46256 TEST=Insignia monitor works, so do others Change-Id: I8aa124d04a90f5dcf9cfa923ed3b693fbb4a06d8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e32ce13462101dc60cfed60b6948b7597e93525a Original-Change-Id: Ia9804afe8011a915e4bec306e863d34ad7e27be5 Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/309540 Original-Reviewed-by: Stphane Marchesin <marcheu@chromium.org> Original-(cherry picked from commit 7f32c9f460991e5e3b947117d6ae4080e630a532) Original-Reviewed-on: https://chromium-review.googlesource.com/309576 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/12443 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-19edid: Don't set standard timings as supported if they're notDouglas Anderson
The set to say that a standard timing was supported was not properly in the "if" test. That meant that even when standard timings weren't supported, we thought that they were. That had the side effect of never using the detailed mode. BRANCH=none BUG=chrome-os-partner:46998 TEST=Adafruit panel works now Change-Id: Ide3ed6c5682840f808d854755dac58e9057e6bda Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c99d3ee8d163fc6be207c5a7df2a7aecd7af7849 Original-Change-Id: Ib67735219fd28516857d9b63f1ba156573f1bea3 Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/309521 Original-(cherry picked from commit 4e4c2816e2239299bc02e3a57fb18056db62b56c) Original-Reviewed-on: https://chromium-review.googlesource.com/309552 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/12442 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-19edid: Remove useless parameter from detailed_cvt_descriptor()Douglas Anderson
The detailed_cvt_descriptor() function takes a parameter "out" for no good reason. Remove it. BRANCH=none BUG=chrome-os-partner:46998 TEST=Build and boot Change-Id: I1042dba9ddf2b4b543bd07615013088be5055950 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5c3474c9b1f9fb73f44d64d3a0592f92339da2df Original-Change-Id: I4d695a6dba6606d2132578ce0ab4cb612c83d0f4 Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/309598 Original-(cherry picked from commit 39122e242e808d71a4e274e8a23e9a63f4984388) Original-Reviewed-on: https://chromium-review.googlesource.com/309496 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/12441 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-19mainboard/asus/kgpe-d16: Fix I/O link detectionTimothy Pearson
Change-Id: Ibefc9dc2e1e0267389eb8d716408bae6026ce084 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12024 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-19northbridge/amd/amdmct/mct_ddr3: Move K10D configuration into separate fileTimothy Pearson
Change-Id: Id45888f266fac7810a63fef43b8d7a0ee40cbf70 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12023 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-19cpu/amd/fam10h-fam15h: Bring HT register configuration in line with BKDGTimothy Pearson
The existing HyperTransport register configuration values were incorrect in many spots. Apply the correct values from the BKDG on Family 10h and Family 15h processors. Change-Id: I009b6f478340e2dbfcda2b4534473d4397f9ecef Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12022 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-19nb/intel/sandybridge/raminit: Comment the codePatrick Rudolph
Add lots of comments for better documentation. Change-Id: Ia203cb649857f979bb6c1c2d405b74f2ccc8f99d Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: http://review.coreboot.org/11915 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2015-11-19device/device.c: remove warning for missing apic read resourcesMartin Roth
We have had the "APIC: 00 missing read_resources" messages for many years. It's obviously not an error, and also doesn't cause boot failures. Therefore, remove the message. Change-Id: I7f99c5950a3457df04e7ef6edb456b70dba9680c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12471 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-11-19lenovo/r400: Add clone of Lenovo T400Michał Masłowski
The existing code for the Lenovo T400 works without changes on the Lenovo R400. Same HDA verbs are provided by Lenovo BIOS on both laptops. Change-Id: I1dadddd7250ab80a4c40c2435865d72e3e5d99c9 Signed-off-by: Michał Masłowski <mtjm@mtjm.eu> Signed-off-by: Francis Rowe <info@gluglug.org.uk> Reviewed-on: http://review.coreboot.org/8393 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-11-19AMD Hudson: Use amdfwtool to integrate firmwares.Zheng Bao
Change-Id: Ie17a744b6ef4e5405b3dfcecc1deb6462220ec60 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12435 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-19pcengines/apu1: enable use of clkreq pinsFelix Held
only enable pcie gpp clocks when the corresponding clkreq pin is asserted Change-Id: I7822d011bb94867d470c0194e6b652833c395cb2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: http://review.coreboot.org/12353 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-11-19pcengines/apu1: disable unused clock outputsFelix Held
disable unconnected FCH clock outputs to save some power Change-Id: Ib3efebb8656392d58d762c23827168017d273de8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: http://review.coreboot.org/12082 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-11-19x86: Add Kconfig to disable early bootblock postcodesMartin Roth
The Intel cave creek chipset needs to have port 80 routing configured before any post codes can be sent to port 80h. Sending post codes out before the routing is done will hang the system. This patch allows us to disable the first couple of post codes that go out before the routing can be configured. The Kconfig symbol is selected by the cave creek chipset (fsp_i89xx). Change-Id: I9bf41669ec32744f87a1ed2de011d31c72ea38da Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12422 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: York Yang <york.yang@intel.com>
2015-11-18Remove dependency for HAS_PRECBMEM_TIMESTAMP_REGIONMartin Roth
HAS_PRECBMEM_TIMESTAMP_REGION was dependent on COLLECT_TIMESTAMPS, but should be allowed to be selected independently. My thought is that the code may only be used when collecting timestamps, the HAS prefix signifies that this is a platform configuration option. This fix could also be done by adding 'if COLLECT_TIMESTAMPS' everywhere that 'select HAS_PRECBMEM_TIMESTAMP_REGION' is used Change-Id: Iaf4895475c38a855a048dc9b82d4c97e5e3f4e5c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11338 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-18Kconfig: fix typo in description of the TRACE optionBen Gardner
Change-Id: Icec6d047530e64228a3e71a636af4266ed5a73f0 Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: http://review.coreboot.org/12457 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-18fsp1_0: Update rangeley to revision POSTGOLD4Marcin Wojciechowski
Alignment of Intel Firmware Support Package 1.0 Rangeley header and source files to the revision: POSTGOLD4 Detail changelog can be found at http://www.intel.com/fsp FSP release date September 24, 2015 Change-Id: If1a6f95aed3e9a60af9af8cf9cd466a560ef0fe2 Signed-off-by: Marcin Wojciechowski <marcin.wojciechowski@intel.com> Reviewed-on: http://review.coreboot.org/12418 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-18cpu/amd/fam10h-fam15h: Update Fam15h APIC config and startup sequenceTimothy Pearson
This fixes Family 15h multiple package support; the previous code hung in CAR setup and romstage when more than one CPU package was installed for a variety of loosely related reasons. TEST: Booted ASUS KGPE-D16 with two Opteron 6328 processors and several different RDIMM configurations. Change-Id: I171197c90f72d3496a385465937b7666cbf7e308 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12020 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-18AMD/Bettong: add FCH's GPIO, UART & I2C supportZheng Bao
Merlin Falcon's FCH has GPIO, UART and I2C. All of them are controlled by registers mapped at MMIO space. This ASL code is used for Windows drivers. TEST: 1. Boot Windows 8 or Windows 10. 2. Install AMD Catalyst driver. 3. AMD FPIO, UART and I2C can be found in device manager. 4. I2C passed Multi Interface Test Tool (MITT) test. Change-Id: I7ffe3fe0046d9a078cc38176c29a8e334646a5a3 Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/11750 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2015-11-18google/veyron_emile: retrieve the MAC address from vpdZhengShunQian
Emile has a on board ethernet. BUG=chrome-os-partner:47465 TEST=vpd -s ethernet_mac0=001122334455 build and check the MAC address Change-Id: I90ed0ed1253c804568fcdd3dd212bb062a48c836 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 99b275c594196de0811f68380e66c226d2649927 Original-Change-Id: I1690a1f39090c57c64d4965092c80eef9070babf Original-Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311900 Original-Commit-Ready: Shunqian Zheng <zhengsq@rock-chips.com> Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/12452 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-18google/veyron*: Pulse the i2c clock once if sda was lowDouglas Anderson
On one particular TV the TV was holding SDA low when it came up. It would release the SDA when the SCL went low the first time. Unfortunately the HDMI i2c port wouldn't transmit until the SDA was released. Let's detect this case and insert a bogus clock pulse to try to get the other side to release SDA. It's unclear why the kernel doesn't have this problem. BRANCH=none BUG=chrome-os-partner:46256 TEST=Insignia TV works now Change-Id: Ic9d27eb69bdc9c5fb11a68258e0c755cdc8b79d7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 356ee7503f04e741a41be37ad573b588067b7114 Original-Change-Id: I4b6361877e0576cc4ea2f643f073f1aab660e434 Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/309258 Original-Reviewed-by: Agnes Cheng <agnescheng@google.com> Original-Commit-Queue: Agnes Cheng <agnescheng@google.com> Original-Trybot-Ready: Agnes Cheng <agnescheng@google.com> Original-Tested-by: Agnes Cheng <agnescheng@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/309546 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/12451 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-18google/lars: enable wakeup from S0ix using headset buttondavid
Kernel needs to set Audio IRQ as wake capable. BUG=None BRANCH=None TEST=emerge-lars coreboot Change-Id: Ib7f0fc52baa006d992a2f91a63417e3f76817634 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 32d82ac48c6f830fbb09b776d0adaf6b7a727416 Original-Change-Id: I3fd70ac99c623a99b07fa1a185ebace8c1fc3d69 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/312172 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12450 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-18google/lars: Enable wake from touch paddavid
This patch enables GPP_B5 as ACPI_SCI for wake. It also defines touchpad wake device in ACPI with GPE0_DW0_05 for _PRW. BUG=none BRANCH=none TEST=emerge-lars coreboot Change-Id: I2b65f6a37783ecdbdbc32ebe613243e042c865e9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ec5b629f920984564f12f2c09458ed300d031f69 Original-Change-Id: I9bd2b3595ae833fa5d07d97a7cda4a29041be837 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311890 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/12449 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-18google/chell: Turn on keyboard backlight in romstageDuncan Laurie
Use the keyboard backlight to provide indication that the system is booting. This is useful for determining that a system is in S0 and is running BIOS code. BUG=chrome-os-partner:47435 BRANCH=none TEST=boot on chell and see keyboard backlight come on early Change-Id: I43e699bcc2f34998d3d6ce33ce72c7b04b55c146 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a3a0147b6de681365a9c995175076d5f397016fb Original-Change-Id: I2441c28431e71b13b70e6533e175d29ccfd8d7e9 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/312358 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12448 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-18google/chell: Set USB current limit to 2ADuncan Laurie
The GPIO for USBA_1_ILIM_SEL_L should be low to enable 2A charging from the Type-A port. BUG=chrome-os-partner:47172 BRANCH=none TEST=emerge-glados coreboot Change-Id: I1bbcdd467684e7c1372c8ca862d498fb6cbb966c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c8a8fbed6d0fd7aea0a41db2bde104fe7a05cabe Original-Change-Id: I3b18cbb204cfa19e50f34ea9533018e286342513 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/312451 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12447 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-18google/chell: disable power rails in sleep pathAaron Durbin
For the rails controllable by the host processor through gpios turn them off in the sleep paths. The result is that S3 and S5 will turn off those rails. BUG=chrome-os-partner:47228 BRANCH=None TEST=Built for chell. Change-Id: I5843f13be43a6ec143600585a5a0c47563e533dd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ddd5860dc0cfee68ec2f77f4931665740bede08c Original-Change-Id: Ife0e2fb11373dd129e20b914b45cd5b56c3493f7 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/312321 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/12446 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-18google/glados: disable power rails in sleep pathAaron Durbin
For the rails controllable by the host processor through gpios turn them off in the sleep paths. The result is that S3 and S5 will turn off those rails. BUG=chrome-os-partner:47228 BRANCH=None TEST=Built and booted glados. Suspended and resumed. Change-Id: I6d45683b64ca5f7c3c47e11f95951bd2d9abf31e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ed432e2b5535da6f872a53b76886d983f00b4e8e Original-Change-Id: I94d7e0b00bf7e7da8dc59f299e41b72e8fcb64f4 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/312320 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/12445 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-18mb/roda/rk9: Fix cbmem recovery on resume pathNico Huber
By calling cbmem_recovery() with `0`, we rewrote the cbmem table even on the resume path. By that, we lost the OS' resume vector and ended up loading the payload. Change-Id: Ic24a12d4143d6924321b1d01f07a467c58c4e9ea Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: http://review.coreboot.org/12420 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-18nb/intel/sandybridge: Fix PEG disablementPatrick Rudolph
Fix regression introduced by: 3660c0fc658e4e20ef079f762dfc7ad05c83544c "northbridge/intel/sandybridge: Enable PEG clock-gating on demand" Issue observed: GNU/Linux kernel crashes in earlyinit on systems without PEG devices. The crash occurs on every boot in different functions. There's no problem on systems with PEG enabled. Test system: * Lenovo T530 * Intel Core i5-3320M CPU * Fedora GNU/Linux 4.1 * PEG disabled in devicetree Problem description: Tests shows that modifing PEG chicken bit or device enable bits after setting BIOS_RESET_CPL causes random crashes in GNU/Linux. Problem solution: Disable PEG devices before setting BIOS_RESET_CPL. Final testing results: No more random kernel crashes. Change-Id: I4a967c2d00d7d1e4426cf5abdd5f616c21557da7 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: http://review.coreboot.org/12112 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-11-18nb/intel/sandybridge/northbridge: Initialize uma_memory_base in all casesPatrick Rudolph
Issue observed: Coreboot stops at: "Not enough MTRRs available!" Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 * ATI Radeon HD4780 Problem description: In case the IGD does not claim VGA decode, the code path taken results in an integer overflow as uma_memory_base isn't initialized. The MTRR assignment will fail, because of invalid memory regions. Problem solution: Properly initialize uma_memory_base to prevent possible integer overflow. Final testing results: The system boots again with IGD not claiming VGA decode. Change-Id: I025be23b1defb6155469a3eee66569e49a695e7f Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: http://review.coreboot.org/11918 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-11-18northbridge/intel/sandybridge: Fix random raminit failuresPatrick Rudolph
Issue observed: Intel raminit works in about 50% of all test-cases on lenovo x220. Problem solution: Prefer a smaller valid value over the measured one for initial timB timings. Final testing result: Tests on x220 shows that the issue was resolved. The test system booted successfully ten times in a row. Tests on Gigabyte GA-B75M-D3H revealed no regressions. Test system: * Intel Pentium CPU G2130 * Gigabyte GA-B75M-D3H * DIMM: "Crucial 2GB 256Mx64 CT2566aBA160BJ" Change-Id: I1a115a45d5febf351d89721ece79eaf43f7ee8a0 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11248 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-11-17arm64: tegra132: tegra210: Remove old arm64/stage_entry.SJulius Werner
This patch removes the old arm64/stage_entry.S code that was too specific to the Tegra SoC boot flow, and replaces it with code that hides the peculiarities of switching to a different CPU/arch in ramstage in the Tegra SoC directories. BRANCH=None BUG=None TEST=Built Ryu and Smaug. !!!UNTESTED!!! Change-Id: Ib3a0448b30ac9c7132581464573efd5e86e03698 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/12078 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-17rules.h: Add ENV_ macros to detect current architectureJulius Werner
This patch expands the existing ENV_<stage> macros in <rules.h> with a set of ENV_<arch> macros which can be used to detect which architecture the current compilation unit is built for. These are more consistent than compiler-defined macros (like '#ifdef __arm__') and will make it easier to write small, architecture-dependent differences in common code (where we currently often use IS_ENABLED(CONFIG_ARCH_...), which is technically incorrect in a world where every stage can run on a different architecture, and merely kinda happened to work out for now). Also remove a vestigal <arch/rules.h> from ARM64 which was no longer used, and genericise ARM subarchitecture Makefiles a little to make things like __COREBOOT_ARM_ARCH__ available from all file types (including .ld). BUG=None TEST=Compiled Falco, Blaze, Jerry and Smaug. Change-Id: Id51aeb290b5c215c653e42a51919d0838e28621f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/12433 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-11-17northbridge/intel/fsp_sandybridge: remove blank lineMartin Roth
Remove a blank line introduced in commit 31f4d00c (northbridge/intel: Add i89xx header file) Change-Id: I27dadb27ad041f48520709ef499bde380c58265b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12387 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-11-17src/console: Link die.c in bootblock without BOOTBLOCK_CONSOLEAlexandru Gagniuc
Without BOOTBLOCK_CONSOLE any call to die() fails due to die() symbol not being defined at link time. die() is not is dependent on the console backend, and can function without it (the prink gets no-oped). Change-Id: I6cecafb576c3b1e901f3927c777f6282174fb259 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/12356 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-17fsp_baytrail: use external microcode .h filesMartin Roth
The microcode for Bay Trail that's in the blobs repo is for the M and D chip variants only. The fsp_baytrail directory is for Bay Trail I chip variants, and will not boot if the M/D microcode is used. The microcode for the I variant is supplied as part of the Bay Trail FSP package. Change-Id: I5493deb1626dc3cf037053e13e092f5a1143a13a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12334 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-16arm64: Implement generic stage transitions for non-Tegra SoCsJulius Werner
The existing arm64 architecture code has been developed for the Tegra132 and Tegra210 SoCs, which only start their ARM64 cores in ramstage. It interweaves the stage entry point with code that initializes a CPU (and should not be run again if that CPU already ran a previous stage). It also still contains some vestiges of SMP/secmon support (such as setting up stacks in the BSS instead of using the stage-peristent one from memlayout). This patch splits those functions apart and makes the code layout similar to how things work on ARM32. The default stage_entry() symbol is a no-op wrapper that just calls main() for the current stage, for the normal case where a stage ran on the same core as the last one. It can be overridden by SoC code to support special cases like Tegra. The CPU initialization code is split out into armv8/cpu.S (similar to what arm_init_caches() does for ARM32) and called by the default bootblock entry code. SoCs where a CPU starts up in a later stage can call the same code from a stage_entry() override instead. The Tegra132 and Tegra210 code is not touched by this patch to make it easier to review and validate. A follow-up patch will bring those SoCs in line with the model. BRANCH=None BUG=None TEST=Booted Oak with a single mmu_init()/mmu_enable(). Built Ryu and Smaug. Change-Id: I28302a6ace47e8ab7a736e089f64922cef1a2f93 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/12077 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-16northbridge/amd/mct_ddr3: Add registered and x4 DIMM support to Fam15hTimothy Pearson
The existing MCT support code did not perform any of the requisite configuration to support registered or x4 DIMMs. Add the needed configuration per the BKDG for Family 15h. Change-Id: I9ee0bb7346aa35f564fe535cdd337ec7f6148f2b Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12019 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-16amd/amdmct/mct_ddr3: Partially fix up registered DIMMs on Fam10hTimothy Pearson
Sufficient support has been added to allow booting with registered DIMMs on the KGPE-D16 in certain slots. ECC support needs additional work; the ECC data lanes appear to cause boot failures in some slots. Change-Id: Ieaf4cbf351908e5a89760be49a6667dc55dbc575 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12017 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-16Revert "Drop SuperIO nuvoton/nct6779d"Stefan Reinauer
This reverts commit 42444f6f53d47604d9a44c9e109b5717efaed74f. Change-Id: Ifaaaad715d94c3c9ff365745aa2e6ee546924f4f Reviewed-on: http://review.coreboot.org/12328 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-16intel/fsp_baytrail: Load APs microcode in baytrail_init_cpusYork Yang
Load microcode to APs when performing baytrail_init_cpus. The updated fsp1_0 driver calls TempRamInit API with a dummy microcode, so FSP will not handle the microcode load. Change-Id: I7b7c0f43da0d149048ae5a8fd547828f42de04fd Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: http://review.coreboot.org/12095 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-16intel/fsp_baytrail: Load BSP microcode in bootblockYork Yang
Load microcode to BSP in bootblock so later on the FSP TempRamInit call can be success. The updated fsp1_0 driver calls TempRamInit API with a dummy microcode, so FSP will not handle the microcode load. If BSP is not loaded a microcode before calling TempRamInit API, the call will fail with the error No Valid Microcode Was Found. Change-Id: I1fbe68e14e5a24d8f2da70603cd2f03675b9ca81 Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: http://review.coreboot.org/11896 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-16intel/fsp1_0: Use dummy microcode when calling FSP TempRamInitYork Yang
Pass in dummy microcode when calling FSP TempRamInit API. FSP will not do the microcode load and leave the work to coreboot. Ensure that BSP has been loaded a microcode before calling TempRamInit API, otherwise FSP will return error that No Valid Microcode Was Found. Change has been verified on fsp_baytrail and will be applied to rangeley. Change-Id: I8247c0503c8eb3d1c8eaa059632fb3a11c9daae9 Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: http://review.coreboot.org/11895 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-11-16intel/fsp_model_406dx: Load APs microcode in model_406dx_initDavid Guckian
Load microcode to APs when performing model_406dx_init. The updated fsp1_0 driver calls TempRamInit API with a dummy microcode, so FSP will not handle the microcode load. Change-Id: Ib75f860a34c84bf13c0c6c31ebed13e5787f365e Signed-off-by: David Guckian <david.guckian@intel.com> Reviewed-on: http://review.coreboot.org/12436 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-16intel/fsp_rangeley: Load BSP microcode in bootblockDavid Guckian
Load microcode to BSP in bootblock so later on the FSP TempRamInit call will return with success. The updated fsp1_0 driver calls TempRamInit API with dummy microcode, so FSP will not handle the microcode load. If BSP is not loaded with microcode before calling TempRamInit API, the call will fail with error No Valid Microcode Was Found. Change-Id: I9c55acaf3353a759bb0119f0a5402a704ffb2c4a Signed-off-by: David Guckian <david.guckian@intel.com> Reviewed-on: http://review.coreboot.org/12367 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: York Yang <york.yang@intel.com>
2015-11-16nb/amd/mct_ddr3: Fix RDIMM errors due to undefined number of slotsTimothy Pearson
The current code did not define the number of DIMM slots on the mainboard, which lead to incorrect configuration values and occassional training failure. Add preliminary support for DIMM slot count configuration. Change-Id: I488511d6262ffa8207c442d133314aed0f75acfb Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12016 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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