coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2018-10-15	nb/intel/x4x: Program read training results to all ranks	Arthur Heymans
2018-10-14	soc/amd/stoneyridge: Define PM USB Enable register	Marshall Dawson
2018-10-14	soc/amd/stoneyridge: Remove hudson EHCI debug controllers	Marshall Dawson
2018-10-14	soc/amd/stoneyridge: Remove errant parenthesis in southbridge.h	Marshall Dawson
2018-10-14	soc/amd/stoneyridge: Rearrange southbridge.h more	Marshall Dawson
2018-10-12	drivers/intel/fsp2_0: Hook up IntelFSP repo	Patrick Georgi
2018-10-12	libpayload: arm64: Conform to new coreboot lib_helpers.h and assume EL2	Julius Werner
2018-10-12	amd/stoneyridge: Fix PmControl register size in SMI handler	Marshall Dawson
2018-10-12	amd/stoneyridge: Rename CGPLL_CONFIG definitions	Marshall Dawson
2018-10-12	amd/stoneyridge: Rename GppClkCntrl fields	Marshall Dawson
2018-10-12	amd/stoneyridge: Rearrange southbridge.h	Marshall Dawson
2018-10-12	amd/stoneyridge: Remove dead GPIO definitions	Marshall Dawson
2018-10-12	amd/stoneyridge: Clarify XHCI_PM register definitions	Marshall Dawson
2018-10-12	amd/stoneyridge: Fix SPI_CMD_TRIGGER coding style	Marshall Dawson
2018-10-12	amd/stoneyridge: Convert hex definitions to lower case	Marshall Dawson
2018-10-12	amd/stoneyridge: Remove hudson register definitions	Marshall Dawson
2018-10-11	mb/google/poppy/var/nocturne: Provide override for ec eventinfo	Furquan Shaikh
2018-10-11	mb/google/poppy: Allow variants to provide event info at runtime	Furquan Shaikh
2018-10-11	ec/google/chromeec: Add support for querying ec board id in smm stage	Furquan Shaikh
2018-10-11	ec/google/chromeec: Get rid of __SMM__ guard for chromeec functions	Furquan Shaikh
2018-10-11	src: Move common IA-32 MSRs to <cpu/x86/msr.h>	Elyes HAOUAS
2018-10-11	src: Replace MSR addresses with macros	Elyes HAOUAS
2018-10-11	amd/stoneyridge: Indicate STAPM units in their name	Richard Spiegel
2018-10-11	mainboard/google/kahlee: Set PSPP setting to BalanceLow	Akshu Agrawal
2018-10-11	mb/google/kahlee: Set stapm parameters with time value fixed	Akshu Agrawal
2018-10-11	selfboot: remove bounce buffers	Ronald G. Minnich
2018-10-11	tegra124_lp0: make sure to build with compiler.h included	Patrick Georgi
2018-10-11	commonlib/storage: Make pci sdhci code compile in romstage	Bora Guvendik
2018-10-11	riscv: add physical memory protection (PMP) support	Xiang Wang
2018-10-11	soc/intel/common/block/gpio: check for NULL using if statement	Bora Guvendik
2018-10-11	mb/google/octopus: I2C clock tuning for meep	Wisley Chen
2018-10-11	mb/cavium/cn8100_sff_evb: Only expose two UARTs	Patrick Rudolph
2018-10-10	soc/intel/skylake: Set PCIEXPWAK_DIS if WAKE# pin is not enabled	Furquan Shaikh
2018-10-10	mb/google/octopus: Drop I2C bus 0 clock frequency for Phaser	peichao.wang
2018-10-10	lib: increase part number size in memory_info/dimm_info	Aaron Durbin
2018-10-10	soc/cavium: dynamic UART initialization for cavium cn8100	Jens Drenhaus
2018-10-10	mb/google/poppy/variants/nami: Add samsung_dimm_K4AAG165WB-MCRC SPD	Chris Zhou
2018-10-10	mb/google/kahlee/variants/*/devicetree.cb: Reset I2C slaves	Richard Spiegel
2018-10-10	soc/amd/stoneyridge/gpio.c: Create I2C slave reset code	Richard Spiegel
2018-10-10	mb/google/kahlee: Add delan variant	Martin Roth
2018-10-10	mb/google/fizz: Prepare sharing directory for variants	David Wu
2018-10-10	mediatek/mt8183: Init PLLs for DRAM	Tristan Shieh
2018-10-09	soc/intel/cannonlake: Add PCIE ASL entry	Subrata Banik
2018-10-09	soc/intel/cannonlake: Make correct IRQ mapping for CNL SA and PCH PCI devices	Subrata Banik
2018-10-09	soc/intel/common/acpi: Fix ACPI Namespace lookup failure, AE_ALREADY_EXISTS i...	Subrata Banik
2018-10-09	soc/intel/common/block/pcr: Add NULL pointer check in pcr_execute_sideband_msg()	Subrata Banik
2018-10-09	soc/intel/cannonlake: Disable Legacy PME for Root ports	Subrata Banik
2018-10-09	soc/intel/cannonlake: Ensure FSP don't override ITSS IPCx registers	Subrata Banik
2018-10-09	soc/intel/skylake: Ensure FSP don't override ITSS IPCx registers	Subrata Banik
2018-10-09	soc/intel/common/pch: Select Kconfig for ITSS polarity configuration	Subrata Banik