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2009-04-04fix configuration step of totalimpact briq and embeddedplanet ep405pc.Stefan Reinauer
(trivial). Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4062 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-03These are some cleanups and changes. These are build and boot tested on qemu.Ronald G. Minnich
Some changes for option roms: - don't make users pick the name. Names for option roms are in the v3-defined format of pci%04x,%04x.rom with the vendor and device id filling in the %04x. - users pass in vendor and device id. - users pass in a dest. If the dest is 0, the address of the ROM image in FLASH is returned. If the address is non-zero, then the decmpressor is called, and it will make sure the ROM image is copied to the destination (even in the uncompressed case). And some type and print cleanup. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4060 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-03Add u64 typedef to ppc (trivial)Patrick Georgi
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4059 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-03Fix up the incomplete commit in r4055.Carl-Daniel Hailfinger
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4058 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-03drop unused variables in generic smm handler. (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4057 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-03drop another shadow variable (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4056 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-03There are more than a dozen targets in the v2 tree which refer to ROMCCCarl-Daniel Hailfinger
in their Config.lb but never use it. There's no point in keeping dead code around. This patch removes ROMCC remainders from Config.lb and kills orphaned auto.c and failover.c in the affected mainboard directories. arima/hdama ibm/e325 ibm/e326 iwill/dk8s2 iwill/dk8x msi/ms9282 newisys/khepri sunw/ultra40 tyan/s2891 tyan/s2892 tyan/s2895 tyan/s4880 tyan/s4882 Abuild log is completely identical with and without the patch. With this patch, the last ROMCC remainders for K8 boards are gone. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4055 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-03I thought that romfs infrastructure is done now, but there were somePatrick Georgi
issues (see buildbot). The romfs image was always built, and sometimes broke (because of the different image layouts) for buildrom images. After the patch, these issues are avoided by not adding payloads to the romfs image (they wouldn't be read anyway). Both workarounds (in buildrom code for romfs and vice-versa) aren't very pretty, but that's what our buildsystem requires. As I had to create a "communication channel" (via the romfs-support files), I took the chance to also use it for compression information, so if you configure lzma support, you'll get lzma compressed payloads in romfs. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4054 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-03The attached patch tries new style compression first and runs oldPatrick Georgi
style compression if the command returned an error code (happens if you run an old lzma with the new arguments) Tested on new-style lzma only (as I lack a build environment with old lzma), but I tested that the old lzma returns with an error code. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-03Print a pointer as pointer, it's really trivial.Patrick Georgi
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-03Next step. Kill auto.c and failover.c and clean up Config.lb forCarl-Daniel Hailfinger
tyan/s2735 tyan/s2850 tyan/s2875 tyan/s2880 tyan/s2881 tyan/s2882 tyan/s2885 tyan/s2891 tyan/s2892 tyan/s2895 Abuild log is completely identical with and without the patch. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4050 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-03the attached patch is the last infrastructure change necessary forPatrick Georgi
romfs. Everything else to make a target romfs aware happens in the targets. What the patch does: 1. missing romfs.h include 2. special handling while creating coreboot.rom While the romfs code path in the makefile doesn't actually use the file, it's possible that the build of coreboot.rom fails in a romfs setup, because the individual buildrom image is too small to host both coreboot and payloads (as the payloads aren't supposed to be there). Thus, a special case to replace the payload with /dev/null in case of a romfs build. There would be cleaner ways, but they're not easily encoded in the Config.lb format. 3. config.g is changed to create rules for a romfs build Targets should still build (they do for me) Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4049 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-03There are more than a dozen targets in the v2 tree which refer to ROMCCCarl-Daniel Hailfinger
in their Config.lb but never use it. There's no point in keeping dead code around. Kill it. This patch removes ROMCC remainders from Config.lb for tyan/s2735 and tyan/s2850. Abuild build log with and without the patch is completely identical. More patches of the same type can be done, hopefully making ROMCC dependencies a bit more clear for v2. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4048 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-01Fix typo.Marc Jones
trivial. Signed-off-by: Marc Jones <marcj303@gmail.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4046 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-01Updated microcode for for AMD Fam10 DR-B2 and B3.Zheng Bao
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4045 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-01forgot this. Ronald G. Minnich
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4044 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-01(trivial) add filo call back for those few mainboards that still (need to) Stefan Reinauer
use the built-in filo. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4043 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-01Drop CONFIG_CHIP_NAME. Those config statements in Config.lb shouldStefan Reinauer
be used unconditionally, and the names don't hurt. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4042 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-01Forgot CONFIG_ROMFS for supermicro/h8dme.Patrick Georgi
Trivial fix, just add the defaults as with all other boards. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4041 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-01Add copyright notices to two files, src/boot/elfboot.cebiederm
and its derivative src/boot/selfboot.c. The mail in which Eric asserts authorship on elfboot.c is quoted below, selfboot.c was substantially edited by Ron. With that information in mind the change is trivial. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> From: ebiederm@xmission.com (Eric W. Biederman) Date: Wed, 01 Apr 2009 03:31:15 -0700 To: Patrick Georgi <patrick@georgi-clan.de> Patrick Georgi <patrick@georgi-clan.de> writes: > Hi, > > We found some file in the coreboot tree that we suspect is yours. > Unfortunately, > both copyright notice and license are missing. > Could you please take a look at it, and state whether it's yours, > and if so, > what license is to be attached? Yes. GPLv2 > The file in question is > http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot-v2/src/boot/elfboot.c > and its history goes back to > http://tracker.coreboot.org/trac/coreboot/log/trunk/LinuxBIOSv2/src/boot/elfboot.c?rev=2890 Eric git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4040 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-01This code adds support for coreboot images that use ROMFS. Ronald G. Minnich
It also removes the call to FILO from hardwaremain -- that has needed removal for a long time. abuild tested. Note that this code has been tested and works on both qemu and kontron. The changes to use it are coming next. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4039 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-31fix typoStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4038 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-31fix typoStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4037 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-31fix shadow variable in compute_ip_checksum.cStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4036 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-31Add the CONFIG_ROMS config variable. Ronald G. Minnich
Tested under abuild, causes no trouble. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4035 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-31This fixes a shadowed declaration in multiboot.c.Robert Millan
Signed-off-by: Robert Millan <rmh@aybabtu.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4034 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-31cosmetic fix for function definition.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4033 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-26During the suspend/resume programming I came to an issue that first 4KB ofRudolf Marek
memory must be clear with 0s because otherwise the resources of K8 will be totally messed up. res = probe_resource(dev, 0x100 + (reg | link)); This is called with dev = NULL and this is no good for probe_resource at all. The attached patch fixes the potential problems and of course the problem itself. On one particular place was missing test if the device really exists. This was copied to fam10 and perhaps the same issue is in v3 (DID NOT check). The rest of the patch is just very paranoid and do all checkings. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Myles Watson <mylesgw@gmail.com> --This line, and those below, will be igno red-- M src/devices/pci_ops.c M src/northbridge/amd/amdk8/northbridge.c M src/northbridge/amd/amdfam10/northbridge.c git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4030 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-25The latest ucode patches for Family 10h:Zeng Bao
9fh for RB/BL/DA Rev C; 96h for DR Rev B. Signed-off-by: Zeng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4028 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-24Every object file with a struct pci_driver ... __pci_driver needs to be markedStefan Reinauer
as "driver" instead of "object" in order to get the init code actually executed. This patch fixes up all northbridges that did not do this before. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4027 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-21To make use of HAVE_HIGH_TABLES following patch is needed. Also, it movesRudolf Marek
coreboot to 1MB and tries to cache whole range for XIP. The UMA part colide a bit with the HAVE_HIGH_TABLES region. I solved that by relocation of the region. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4025 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-21To make use of HAVE_HIGH_TABLES following patch is needed. Also, it movesRudolf Marek
coreboot to 1MB and tries to cache whole range for XIP. The UMA part colide a bit with the HAVE_HIGH_TABLES region. I solved that by relocation of the region. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4024 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-20Kevin O'Connor said:Myles Watson
The bug is in src/arch/i386/boot/boot.c. The inline assembly in jmp_to_elf_entry uses the "g" flag to pass in parameters. However, "g" allows gcc to use stack relative addressing of parameters. Easiest fix would be to change "g" to "ri" - put the parameter either in a register or as an immediate value. That's what this patch does. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4023 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-20Add Supermicro h8dm3 mainboard. This is mostly a copy from the h8dmr.Marc Jones
The one issues is the SPD address switch for the second CPU. That means that the memory must be an exact match on each CPU. Signed-off-by: Marc Jones <marcj303@gmail.com> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4022 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-20Fix CPUID typo. This caused fid to memory speed calculations to be off.Marc Jones
Signed-off-by: Marc Jones <marcj303@gmail.com> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4021 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-19fix the following warning on all boards that don't have PIRQ_ROUTE enabledStefan Reinauer
In file included from coreboot-v2-4017//src/arch/i386/boot/pirq_routing.c:2: coreboot-v2-4017/src/arch/i386/include/arch/pirq_routing.h:45:5: warning: "PIRQ_ROUTE" is not defined coreboot-v2-4017//src/arch/i386/boot/pirq_routing.c:103:6: warning: "PIRQ_ROUTE" is not defined Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4019 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-19fix totalimpact briq compilation. the target had a cpu specific and a mainboardStefan Reinauer
specific clock.c. Since no other target uses the same cpu, I commented out the CPU's clock.c. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4018 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-18add YABEL flag to options to decide wether access to devices other than the ↵Pattrick Hueper
one yabel is running for is possible Signed-off-by: Pattrick Hueper <phueper@hueper.net> Tested and Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4017 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-17Don't know if this is the correct fix, but it fixes compilation of the PPCStefan Reinauer
targets. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4014 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-17This patch adds "high coreboot table support" to coreboot version 2.Stefan Reinauer
Some bootloaders seem to overwrite memory starting at 0x600, thus destroying the coreboot table integrity, rendering the table useless. By moving the table to the high tables area (if it's activated), this problem is fixed. In order to move the table, a 40 bytes mini coreboot table with a single sub table is placed at 0x500/0x530 that points to the real coreboot table. This is comparable to the ACPI RSDT or the MP floating table. This patch also adds "table forward" support to flashrom and nvramtool. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4011 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-17- TOM2 is filled in by the dynamic ACPI code. Don't hardcode it in theCarl-Daniel Hailfinger
DSDT and use the dynamic TOM2 variable instead. - The DSDT needs to be revision 2 or above to handle 64 bit variables. This will require a recent (not older than 2007) iasl (ACPI compiler). - Fix an incorrect comment. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4010 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-16fix typo in pci_device.c (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4008 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-15Fix all build problems on PPC except the _SDA_BASE issues caused by theStefan Reinauer
code expecting too old binutils(?). Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4007 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-14add YABEL Debug Flags to OptionsPattrick Hueper
Signed-off-by: Pattrick Hueper <phueper@hueper.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4004 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-13This patch reverts SuperIO changes that I was too hasty with. Even though theMyles Watson
address of the RTC is 0x70, you need to write 0x400 to it. Now the dump from superiotool matches the factory except 0xf0 of the keyboard. When you boot with the factory BIOS that is 0x04, but with coreboot it is not set. It's trivial because it is reverts. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4002 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-13This one is an example on how to drop vgabios.c from the mainboard or chipsetStefan Reinauer
directories and use the global (v3) one in util/x86emu instead. It also fixes the breakage introduced by 4000 Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4001 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-13This, ladies and gentlement, is commit #4000.Stefan Reinauer
Use the (almost) same strict CFLAGS in v2 that we use on v3. And fix a few include files and missing prototypes. Also, fix up the Config-abuild.lb files to properly work for cross compiling. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4000 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-13ACPI implementation for i945, ICH7, Kontron 986LCD-MStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3999 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-12Fix HIGH_TABLES introduced error when compiling without MP tableMyles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-11i945 northbridge updateStefan Reinauer
- lots of PCIe updates - various bug fixes to early init - some fixes for typos and warnings - initial support for PCIe x16 - some minor fixes to memory init code - some subsystem vendor id patches, to be consistent with ICH7 Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3997 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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