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2019-07-10vendorcode/amd: Move 'static' to the beginning of declarationElyes HAOUAS
Change-Id: Ib9934f103262c57af076bd27d97c3166d8f2318b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-10nb/intel/nehalem: Tidy quickpath_reserved calculationJacob Garber
- Remove unnecessary braces - Move variable assignment out of function call - Do not find lowest bit set of 0, which is undefined - Use unsigned integer when bit shifting Change-Id: I8651f8cd04165d8d31c44f7919ad5e43499d3d4c Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1229562 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-10nb/intel/nehalem: Die if no memory ranks foundJacob Garber
Die if there are no memory ranks found to prevent a division by zero. Change-Id: I6146dd8420f3734d1a672a9f29a098f47fcb739c Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1229628 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-10soc/intel/block/cpu: remove unused USE_COREBOOT_NATIVE_MP_INITArthur Heymans
Only CONFIG_USE_INTEL_FSP_MP_INIT makes a difference whether native MP init is used or not. Also make USE_INTEL_FSP_MP_INIT mutually exclusive with USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI as this option requires coreboot to set up AP and publish PPI based on it. Change-Id: I65b80805d3cd7b66f8c9f878d3c741b98f24288d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33357 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-10vendorcode/eltan/security/lib: Implement SHA endian functionFrans Hendriks
digest from vb2_digest_bufer() does not contains the correct endian. Create cb_sha_endian() which can convert the calculated digest into big endian or little endian when required. BUG=N/A TEST=Created binary and verify logging on Facebok FBG-1701 Change-Id: If828bde54c79e836a5b05ff0447645d7e06e819a Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-07-10soc/intel/braswell/acpi/lpc.asl: Allocate used ROM size onlyFrans Hendriks
Fixed ROM area is allocated. Reduce the ROM size using CONFIG_COREBOOT_ROMSIZE. BUG=N/A TEST=Facebook FBG-1701 booting Embedded Linux Change-Id: I7a47bf2600f546271c5a65641d29f868ff2748bf Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-10soc/intel: Drop some HAVE_SMI_HANDLER guardsKyösti Mälkki
The necessary conditionals are evaluated within cpu/x86/Makefile.inc and there are no default targets added unconditionally to build. Change-Id: I694cccf6779551445b83659838749dff02aedece Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-07-10cpu/x86: Remove obsolete smm_init_completion()Kyösti Mälkki
This is not used together with PARALLEL_MP and SMM_TSEG. Platforms with SMM_ASEG continue to have their local implementation doing the same thing. Change-Id: I13a2f164804330c93240bff7f048e0a162b3ae25 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34154 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-10intel/i82801ix: Rename smm_lock() prototypeKyösti Mälkki
This southbridge code may be built with either ASEG or TSEG. Fix minor collision in namespaces. Change-Id: I04f90fb308c280621a3037fee4bece1e5655480e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-07-10soc/intel: Remove invalid smm_relocate stubsKyösti Mälkki
Remove the per-platform empty stubs, builds would just fail as there is no equivalent conditional for the smmrelocate.c file. Change-Id: Ie11f307b7bc5415bfdba6a2c66aed01b70d9f0e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-10cpu/amd: Remove empty smm_lock()Kyösti Mälkki
Change-Id: I599d1d7e28f3a6439b04ef9bd38f671e1a876e92 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-07-10device/oprom: Replace CONFIG() preprocessor statementsKyösti Mälkki
Change-Id: I7737b5f2a5c2598af68f2bca769232413f343a39 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mike Banon <mikebdp2@gmail.com>
2019-07-10device/oprom: Reduce indentationKyösti Mälkki
Change-Id: Iadae9221f7ea549e91cdc501155de058c51a982c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mike Banon <mikebdp2@gmail.com>
2019-07-09arch/x86: Flip HAVE_MONOTONIC_TIMER defaultKyösti Mälkki
Change-Id: Id56139a3d0840684b13179821a77bc8ae28e05ae Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-09arch/non-x86: Flip HAVE_MONOTONIC_TIMER defaultKyösti Mälkki
Also remove allwinner/a10 dummy monotonic_timer implementation. Change-Id: I9dfa9b92dc63375465e3bb87b73eeefad601c810 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-09emulation/qemu-power8: Select CPU_QEMU_POWER8Kyösti Mälkki
Change-Id: I5fa6486e96cd81767225a3e1015341c0c89053d1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-09cpu/x86: Flip SMM_TSEG defaultKyösti Mälkki
This is only a qualifier between TSEG and ASEG. Change-Id: I8051df92d9014e3574f6e7d5b6f1d6677fe77c82 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-09cpu/x86: Declare SMM_ASEGKyösti Mälkki
This is really an inverse of SMM_TSEG to flag platforms that should potentially move away from ASEG implementation. Change-Id: I3b9007c55c75a59a9e6acc0a0e701300f7d21f87 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-09cpu/intel: Drop SMM_TSEG conditionalKyösti Mälkki
SMM_TSEG is a qualifier between TSEG and ASEG memory region. ASEG is deprecated and not supported for these CPUs in coreboot codebase. Change-Id: I0602e04957a390473a2449e1c5ff951f9fdff73b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-09soc/amd/stoneyridge,picasso: Switch SMM lock conditionKyösti Mälkki
SMM_TSEG is a qualifier between TSEG and ASEG memory region. ASEG is deprecated and not supported for this platform in coreboot codebase. The SMM lock should be set based on whether SMM is installed or not, HAVE_SMI_HANDLER currently tells that. Change-Id: I9756f8a59ccfedd59d5b997b35313452dd0c4f46 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34127 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-09arch/x86: Replace some uses of SMM_TSEGKyösti Mälkki
No reason why the files could not be used with ASEG. Attempts to use malloc() from ASEG would still fail, though, due the lack of heap. Change-Id: Idf470ae84eb34c442e833925510b08d5314e7638 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34126 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-09arch/x86: Avoid HAVE_SMI_HANDLER conditional with smm-classKyösti Mälkki
Build of the entire smm-class is skipped if we have HAVE_SMI_HANDLER=n. Change-Id: I10b4300ddd18b1673c404b45fd9642488ab3186c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34125 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-09drivers/intel: Move FSP stage_cache implementation into common blockSubrata Banik
Change-Id: Iebb6d698c236a95162b3c7eb07987483a293b50a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-09soc/intel/icelake: Refer to soc/soc_chip.h rather than chip.hSubrata Banik
Change-Id: I9e3b5126173e7cec8f2809a38b92c82c9ed5327d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34085 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-08sb/intel/lynxpoint: Use common final SPI OPs setupArthur Heymans
Change-Id: I12e238b3a33c909103986822bd7398e1c3bac676 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-08sb/intel/ibexpeak: Use common final SPI OPs setupArthur Heymans
This also removes the relevant RCBA replays the mainboard dir. Change-Id: I75dd9d1bcd09d835f205a51c087d52ebb4e166f6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Thomas Heijligen <src@posteo.de>
2019-07-08sb/intel/i82801gx: Use common final SPI OPs setupArthur Heymans
Change-Id: I30f80c237bccf8dc350249fd12ca6c4559d23d4f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-08sb/intel/common: Add a common interface to set final OPs settingsArthur Heymans
This adds a common place to set the final opprefix, optype and opmenu, with a hook to override the opmenu. Change-Id: I162ae6bad7da3ea02b96854ee28e70594e210947 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-08cpu/x86/smm/smm_module_loader: Compare num_concurrent_stacks to size_tElyes HAOUAS
Spotted out using -Wconversion gcc warning option. Change-Id: I11e4792804f0f7b5a7ce504c46654c1bff775c32 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-08src/arch/x86/acpigen: Compare dev_states_count to size_tElyes HAOUAS
Spotted out using -Wconversion gcc warning option. Change-Id: Ib882cfa6d429fbfcab2b8132280182b427d510aa Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33803 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-08qemu-q35: die if started on wrong machinePatrick Rudolph
The QEMU machine "PC" doesn't support MCFG. Die after console init if the user selected the wrong qemu machine and print a message to use the correct machine type. Without this patch ramstage dies with non-helpful message: "get_pbus: dev is NULL!" Change-Id: I9d1b24176de971c5f827091bc5bc1bac8426f3f6 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-08intel/socket_mPGA604: Enable TSC_MONOTONIC_TIMERKyösti Mälkki
Change-Id: I3ca2b7752905209e8db6b1dc74b930445676792e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-08intel/nehalem: Move TSC_MONOTONIC_TIMERKyösti Mälkki
Change-Id: Ib7f2f7773d0eef5ac4e277b44ee9114aa6729527 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-08intel/fsp_broadwell_de: Remove redundant TSC_MONOTONIC_TIMERKyösti Mälkki
Change-Id: I240e9e767c9b38b3b06d3978fd20ddb37a96e470 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-07-08intel/fsp_baytrail: Move TSC_MONOTONIC_TIMERKyösti Mälkki
Change-Id: Ib61ea29724401146eb6f008374cdf599f418e81f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-07-08drivers/pc80: Move UDELAY_IO and UDELAY_TIMER2Kyösti Mälkki
No longer fallback to UDELAY_IO as default. Since these are not cpu properties or features, move the Kconfig location. Change-Id: I9809cdc285c7bf741aa391ddb5755390bbfc2909 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-08mb/google/hatch: Set GPP_D9 as enable pin for Goodix Touch Screen andFrank Wu
increase reset off delay time Goodix touchscreen cannot work in normal mode because PP3300_TOUCHSCREEN_DX dropped. Configure GPP_D9 as enable pin in the devicetree.cb to fix the power sequence. Increase reset_off_delay time from 1ms to 3ms to met the HW requirement. BUG=b:135287161 BRANCH=None TEST=local build and measure sequence with Goodix touch screen Change-Id: I33140869990aa4715c780b0fa322921e450530ef Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33808 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-07mb/google/hatch: Update GPIO settings for SD card and SPI1 Chip selectKrishna Prasad Bhat
This patch updates the following GPIO settings. 1. Set Native termination for GPP_G0 - G4 SD card pins. 2. Set GPP_B19 to NF1. BUG=b:123907904 TEST=Verified SD card functionality on hatch. Checked for SD detection, transferred files to and from SD card. Change-Id: I4549ac7377d7f58f51cda0eb96a62604fd31d2f2 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-07-07lib/romstage_stack.c: Remove fileKyösti Mälkki
After platforms have moved to POSTCAR_STAGE=y the only remaining user is binaryPI now. Make it simpler. Change-Id: Ia70c5c85e06c42f965fb7204b633db9b619e2e84 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-07mediatek/mt8183: update dcxo output buffer settingWeiyi Lu
DCXO consists of core that generates clock and output buffers that provide clock to other peripheral components. This patch mainly eliminates the extra power consumption of output buffers. We only enable the buffer for SOC and disable unused buffers for power-saving. Also disable useless buffer power mode to guarantee the lowest power state. BRANCH=none TEST=Boots correctly on Kukui. Change-Id: I2e5ce181ad327ccf852979da53baca4f249912fe Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32323 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: You-Cheng Syu <youcheng@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-07arch/mips: Make MIPS specific options depend on ARCH_MIPSArthur Heymans
Also don't define the default as this result in spurious lines in the .config. TEST: The generated config.h remain exactly the same for all boards. Change-Id: I7f35a5a9dcbc7b25b7806056e2b8e822fa94e428 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-07arch/x86: Use ssize_t to store lengthJacob Garber
size_t is the wrong type to store the return value of acpi_device_path_fill(), since any negative error values will be converted to a very large unsigned integer and potentially cause buffer overflow. Change-Id: Ia8ed62ecfac8eaa18a61545bd203b3c7a7cd9ca5 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1402095 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-07drivers/amd/agesa: Drop redundant stack allocationKyösti Mälkki
The removed call was there to support case LATE_CBMEM_INIT=y, HAVE_ACPI_RESUME=y. Same stack space is already allocated with postcar_frame_init() call. Change-Id: I03a44bc3252f553b1769d362b2f442d3e6ab73f4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Mike Banon <mikebdp2@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-07src/security/vboot: Add option to skip display init with vboot 2.0Sukerkar, Amol N
This config option, when set, will allow the platform to skip display initialization in normal (non-developer, non-recovery) mode. This allows platforms that do not implement firmware UI in normal mode to skip the display init in firmware. TEST=Set option CONFIG_VBOOT and clear CONFIG_VBOOT_MAY_SKIP_DISPLAY_INIT and the display should initialize in ramstage when platform boots. Set CONFIG_VBOOT and set CONFIG_VBOOT_MAY_SKIP_DISPLAY_INIT and the display initialization should be skipped in coreboot. Signed-off-by: Sukerkar, Amol N <amol.n.sukerkar@intel.com> Change-Id: Icadad6da34dcb817af02868e89a94ea62dbfa7b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-07device/pci: Declare pci_root_bus()Kyösti Mälkki
This is used a lot, cache the result so search of domain from devicetree is only done once. Improvement only applies when MAYBE_STATIC evaluates to static. Change-Id: If675abb632fe68acd59ba0bdfef854da3e0839a9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-07arch/x86: Clean up PIRQ_ROUTEKyösti Mälkki
This code is currently only used by via/epia-m850, it is also somewhat buggy. Change-Id: I140e15d584d3f60f7824bcb71ce63724c11e3f46 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34078 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-07mb/google/hatch/var/kindred: Add Raydium touchscreen supportDavid Wu
Add Raydium controller BUG=b:135728282 BRANCH=master TEST= 1. FW_NAME="kindred" emerge-hatch coreboot chromeos-bootimage 2. boot up on kindred DUT to check touchscreen device by evtest /dev/input/event3: Raydium Touchscreen 3. Raydium TS is working Change-Id: Id963300ab0dadcb78786c5a1328c2a4098a48a05 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33857 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-07mb/google/hatch/var/kindred: Update ELAN GPIO/IRQ and add Synaptics TouchpadDavid Wu
Update ELAN GPIO and IRQ setting and add Synaptics Touchpad BUG=b:132708463 BRANCH=None TEST=Verify ELAN/Synaptics touchpad is working fine. Change-Id: I883ce2e50ca5c6bd2b1ca76cbe24177055cc5d60 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-07mb/google/hatch/variants/kindred: Enable eMMC supportDavid Wu
Enable eMMC support for kindred. Cq-Depend: chromium:1666982 BUG=b:135464155 BRANCH=none TEST=Boot kindred onboard eMMC. Change-Id: I040af6da30313f8dd59e3ef910b290922e090cdc Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33618 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-07soc/intel/icelake: Remove redundant gpio.c from Makefile.incSubrata Banik
Change-Id: Ibddc2363e9bfea9ae41e4807435acb2e788dcb93 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 20:20:23 +0000