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2018-10-25soc/intel/cannonlake: Enable S4 sleep state supportpraveen hodagatta pranesh
Add ACPI entry in sleepstates.asl to support S4 (hibernate). TEST: boot to Windows on CFL RVP11 & RVP8, verified hibernate functionality. Change-Id: I751c774e6ec7fd89ac3af5a619033bd38a759281 Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/28846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-25soc/amd/common/pi: Correct top of DRAM reporting by AGESAMarshall Dawson
Accurately reflect the intention of the syslimit value returned from AmdInitPost(). Assume FFs for the non-present bits. BUG=b:118178425 TEST=Boot Grunt and verify reported value = TOM2-1. Change-Id: Ie8ea4fcbfd52c46ad441890f0decaf0f55816cfd Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-24mb/google/kahlee: Enable 2T mode for liarachris wang
Liara auto restart issue is caused by memory access error and consequent kernel panic. To solve this issue, revert the CL:1243666 (Disable NbP-state on Liara) and use 2T mode instead. BUG=b:116082728 TEST=verify the 2T mode is enabled/boot into ChromeOS and no auto restart/run memtester passed 10 cycle. Change-Id: I3a96276d88ffb70530d72b15c07b59a01cc6209a Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-24nb/intel/*: Use 2M TSEG instead of 8M on pre-arrandale hardwareArthur Heymans
8M was set in the assumption that at least 4M was needed for IED (Intel Enhanced Debug) , but this is not true. The SMRR MTRR's need to have TSEG aligned to its size which is easier when TSEG is only 2M. Also at most 6M of RAM more becomes available for use. Change-Id: I4b114c8dc13699b3c034f0a7060181d9d590737b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27873 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-24cpu/intel/smm: Don't make assumptions on TSEG_SIZEArthur Heymans
Do not assume: - TSEG is 8M - IED_REGION_SIZE is set (not needed on older platforms). Change-Id: I1aadc6f0459a8035864dcf02b0a07e00b284fe2a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27872 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-24mediatek/mt8183: Initialize DRAM with a sequence in constant arrayHuayang Duan
The DRAM init sequence is simply setting some values on register for all DRAM modules, no logic involved; so we can replace it by an array to configure easily. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui, and inits DRAM successfully with related patches. Change-Id: Iacd3ce909ba7a0bdf699c5bfcb2b97f383d7bb6f Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/28836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-10-24sb/amd: Use 'unsigned int' to bare use of 'unsigned'Elyes HAOUAS
Change-Id: I05f9ea97ea80ac7a8f34845c59bd66e424ba2991 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-10-24nb/intel/*: Account for cbmem_top alignmentArthur Heymans
Having cbmem floating between two ram regions is a bad idea and some payloads (e.g. tianocore) even bail out on this. To overcome this issue mark the region between tom and cbmem as uma. Change-Id: Ifab37b0003f09a680024d5b155ab0bb157920952 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-10-24nb/intel/i945: Fix domain resourcesArthur Heymans
Fixed resources have to be registered early during read_resources() phase, such that device allocator will avoid them. Change-Id: Iff5f1426015a908e988ff757055034c87085c0f5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27119 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-24intel/fsp: Fix license header for MeminfoHob.hLijian Zhao
Current header file included a proprietary license, fix that by using same license shared on public fsp release on fsp. BUG=https://ticket.coreboot.org/issues/177 TEST=N/A Change-Id: I129c8a465e702d3885d994f4fab352b34d46f177 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/29224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ian Kelling <ian@iankelling.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-10-24mb/google/octopus/variants/fleex: Update DPTF parametersJohn Su
1. Update PSV values for cpu and sensers. 2. Change PL1 min value from 3w to 4.5w. 3. Change TSR2 TRT source from charger to CPU. Refer to 112448519#comment31. BUG=b:112448519 TEST=Build coreboot for Octopus board Change-Id: I7c7df0f54374fdaa4cf57d5c255d841d7db38cfc Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-10-24mb/google/poppy/var/nocturne: Use CRFP as device name for FP deviceFurquan Shaikh
This change uses CRFP ACPI name for FP device since user space utilities expect this name for triggering different actions. BUG=b:112974410 BRANCH=nocturne Change-Id: I63309227c916b43917e529c223cf738fc3baa209 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29231 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-24mainboard/google/poppy/variants/rammus: Enable touchscreenkane_chen
On rammus, set GPIO GPP_C22 to 1 for touchscreen power on. And add touchscreen device "PNP0C50" to I2C0. According to touchscreen spec, device power on initialization takes 105 ms, so set "generic.enable_delay_ms" to 120. We found there is i2c error log pop up when we set delay time to be 110ms or 105ms. If we set delay time to be 120ms. System will not pop up i2c error log. BUG=b:115944726 BRANCH=master TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure touchscreen works. Change-Id: Ibce552d04991e85c99ae3a0a92455fc747d9fced Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-24vboot: fix CONFIG_RESUME_PATH_SAME_AS_BOOT S3 resume logicJoel Kitching
- should not check VBOOT_STARTS_IN_BOOTBLOCK to set context flag - implement vboot_platform_is_resuming on platforms missing it - add ACPI_INTEL_HARDWARE_SLEEP_VALUES to two intel southbridges [ originally https://review.coreboot.org/c/coreboot/+/28750 ] BUG=b:114018226 TEST=compile coreboot Change-Id: I1ef0bcdfd01746198f8140f49698b58065d820b9 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/29060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-24tpm2/tlcl_send_startup: should pass on TPM_E_INVALID_POSTINITJoel Kitching
Change TSS layer tlcl_send_startup() to expose TPM_RC_INITIALIZE, which gets mapped to TPM_E_INVALID_POSTINIT. The return value is exposed to TSPI layer tpm_setup(), and dealt with as follows: - Regular startup: TPM_E_INVALID_POSTINIT should count as failure. - S3 resume: TPM_E_INVALID_POSTINIT can be assumed to mean that TPM maintains power during S3, and is already initialized. Also, correct an error where |response| could be erroneously accessed when it is set to NULL. BUG=b:114018226 TEST=compile coreboot Change-Id: Ib0c3750386ae04279401c1dc318c5019d39f5ecf Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/29063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-24mb/google/octopus: Use DIMM_INFO_PART_NUMBER_SIZE for part_num_storeFurquan Shaikh
This change uses DIMM_INFO_PART_NUMBER_SIZE to decide the size of part_num_store that holds the number of DRAM part. It ensures that host advertises the supported size to read part number from the EC. BUG=b:115697578 Change-Id: I8439a301fc037b0acdc8b1226ad04d2f363838ef Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
2018-10-23mb/google/poppy: add the smi_events backZhuohao Lee
Before entering the OS, the AP relies on the smi handler to shutdown the system when the lid closes. Without the smi_events setting, the AP will not receive the smi handler. As a result, the AP won't shutdown and will always keep in S0. This problem is caused by the https://review.coreboot.org/c/coreboot/+/28983 and this patch adds the smi_events back to support the smi handler for the lid close. BRANCH=master BUG=b:115572596 TEST=test_that -b ${BOARD} ${IP} firmware_ECLidShutdown Change-Id: Id82311a8ccd109f9c26516f59a45bdf34da98529 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/29191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-10-23src: Remove unneeded whitespaceElyes HAOUAS
Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-10-23soc/amd/stoneyridge: Remove smbus.aslRichard Spiegel
The file smbus.asl has 0 bytes (no content). Now that it's no longer included, remove it. BUG=b:117814641 TEST=Build grunt and gardenia. Change-Id: I66389c721e272053d86357f71a6d1242ca767edd Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-23mb/kahlee mb/gardenia: Remove smbus.asl includeRichard Spiegel
The file soc/amd/stoneyridge/acpi/smbus.asl has 0 bytes (no content). Remove the include of this file. BUG=b:117814641 TEST=Build grunt and gardenia. Change-Id: I0c48167195a9708afc255490bb1996b6dfc7bdfb Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29178 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-23mb/google/octopus: Use a single GPIO for trackpad wake and IRQFurquan Shaikh
This change uses the newly added macros for configuring the same GPI pad(GPIO_135) for IRQ (normal interrupt operations) and wake (interrupt for waking from S3/S0ix) for the trackpad device. The other pad GPIO_142 is now configured as not connected. BUG=b:117553222 TEST=Verified that yorp and bobba wake from S3 and S0ix using trackpad. Change-Id: I2b704f1be493141629c647b79723b0025b0f7dd6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29189 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-23soc/intel/common/block/gpio: Allow GPI to be dual-routedFurquan Shaikh
This change adds new macros to GPIO common library helpers to allow a GPI pad to be dual routed using PAD_CFG_GPI_DUAL_ROUTE. It also adds a helper macro to configure a pad for IRQ and wake. Above macros are guarded using a newly added Kconfig option SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT that is selected only by SoCs that have been validated to allow dual route of GPIs. Currently, this config is selected only for APL/GLK/SKL/KBL that have been validated to work with dual-routing of GPIs for IRQ and wake. BUG=b:117553222 Change-Id: Iaa623d2d78a50f1504e3abe9a47a5a663693aead Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29188 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-23soc/intel/common/block/gpio: Configure Tx Disable in IO standby for GPIsFurquan Shaikh
This change updates various PAD_CFG_GPI* macros to configure Tx as Disabled in IO Standby state. This is done to ensure that the Tx setting is same in IO Standby state as it was in active state i.e. Tx disabled. BUG=b:17553222 Change-Id: If462aee3884cc61a519fb358b84867c695ace251 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-23acpi_device: Refine ACPI_IRQ_* macrosFurquan Shaikh
This change does the following: 1. Adds a helper macro ACPI_IRQ_CFG that can be used by all other ACPI_IRQ* macros to initialize acpi_irq structure. 2. Provides ACPI_IRQ_WAKE* versions to allow board to define an irq as wake capable. BUG=b:117553222 Change-Id: Ic53c6019527bbd270806897247f547178cd1ad3c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-23soc/intel/apollolake: Add reset code to postcar stagePatrick Georgi
Also add a test case for that, a config taken from chromiumos with some references to binaries dropped that aren't in our blobs repo (eg audio firmware). Change-Id: I411c0bacefd9345326f26db4909921dddba28237 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/29223 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-23{device,drivers}: Use 'unsigned int' to bare use of 'unsigned'Elyes HAOUAS
Change-Id: Iebb043a6fbc5803fbb7cad2f35b43917e10d09d4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28700 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-23src: Typo fix (cosmetic)Peter Lemenkov
Change-Id: I81985bd2836bdeb369587f170504a8a048ee496b Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29196 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-22mb/google/poppy/var/nocturne: Change IMX319 sensor link freqLijian Zhao
Change link frequency of IMX319 from 360Mhz to 482.4 Mhz to match the changes from kernel driver. IMX319 has two PLLs and it can be configured either single or dual. Previous driver implemente dual PLL mode, however image sensor vendor prefer single PLL mode and calculate the pixel rate became easier. So the kernel driver changed to use single pll, coreboot change will match that. Bug=b:116082248 Change-Id: Iac9a72253e0529bf2c0785fb701b7bc251bcbab5 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28736 Reviewed-by: Tomasz Figa <tfiga@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-22mb/lenovo/*/romstage: No need to specify board's model in commentsPeter Lemenkov
This is a cosmetic one. It just removes some board names from comments since these functions sometimes are very similar, so no need to add extra difference between them. Change-Id: I26b9296b402d98bcf048580da51da7bbb0c237e4 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-10-22mainboard/: Select MISSING_BOARD_RESET appropriatelyNico Huber
We didn't have a hard_reset() implementation for these boards. So select the board_reset() stub for them. Change-Id: I77651e3844632fb1a347008c96e53d23cc5a2646 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29170 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-22amdfam10: Convert to `board_reset()`Nico Huber
And here comes the mess... This just renames do_hard_reset() to do_board_reset() and keeps current behaviour. As these are never called from chipset or board code but only from common code, it's likely that their implementations are untested and not what we actually want. Also note, that sometimes implementations for rom- and ramstage differ considerably. Change-Id: Icdf55ed1a0e0294933f61749a37da2ced01da61c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29058 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-22sb/amd/*/hudson: Use CF9 resetNico Huber
Implement board_reset() as "system reset". Change-Id: I80801ba58b9d849ef5e14185510666bd312106c2 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29057 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-22sb/amd/cimx/sb[89]00: Use CF9 resetNico Huber
Implement board_reset() as "system reset". Change-Id: I2d277b0845b4e8977b68892c2e5e00d8918e063f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29056 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-22nb/via/vx900: Use CF9 resetNico Huber
Implement board_reset() as "system reset". Change-Id: I2b68a23cdf244884104d4ed54e19d3ab347c3a3e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29055 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-22intel: Use CF9 reset (part 2)Patrick Rudolph
Make use of the common CF9 reset in SOC_INTEL_COMMON_RESET. Also implement board_reset() as a "full reset" (aka. cold reset) as that is what was used here for hard_reset(). Drop soc_reset_prepare() thereby, as it was only used for APL. Also, move the global-reset logic. We leave some comments to remind us that a system_reset() should be enough, where a full_reset() is called now (to retain current behaviour) and looks suspicious. Note, as no global_reset() is implemented for Denverton-NS, we halt there now instead of issuing a non-global reset. This seems safer; a non-global reset might result in a reset loop. Change-Id: I5e7025c3c9ea6ded18e72037412b60a1df31bd53 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-22intel: Use CF9 reset (part 1)Patrick Rudolph
Add SOUTHBRIDGE_INTEL_COMMON_RESET for all Intel platforms that used to perform a "system reset" in their hard_reset() implementation. Replace all duplicate CF9 reset implementations for these platforms. Change-Id: I8e359b0c4d5a1060edd0940d24c2f78dfed8a590 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-22arch/x86: Implement common CF9 resetNico Huber
It's very common across many x86 silicon vendors, so place it in `arch/x86/`. Change-Id: I06c27afa31e5eecfdb7093c02f703bdaabf0594c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-22soc/amd: Implement common reset APINico Huber
Add an `amdblocks` internal API and rename soft_reset() => warm_reset() hard_reset() => cold_reset() as these terms are commonly used in the surrounding code. On Stoney Ridge, make board_reset() call cold_reset() to keep current behaviour of common code calling hard_reset(). But add a TODO if this is intended. Note: Stoney Ridge is using CF9 for the actual reset but the configuration for a cold reset doesn't use the usual full reset bit but some other mechanism. Change-Id: Id33eda676d79529db759b85fa8e28386846e6fa4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-22soc/samsung/exynos5250: Convert to `board_reset()`Nico Huber
Change-Id: I2f69d9f01ac5f7e28dd98e704f3280bf62b9ce58 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-22soc/mediatek: Convert to `board_reset()`Nico Huber
Note, MT8183 didn't select HAVE_HARD_RESET before. So it might still need an update. Change-Id: Ic850f2775ada5e6e543ffb92aaa033b9209596f5 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-22soc/imgtech/pistachio: Convert to `board_reset()`Nico Huber
Change-Id: If8fc29c46e2cbc69f94ea8b6dc414a93d82ffb28 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-22soc/rockchip/rk3399: Convert to `board_reset()`Nico Huber
Change-Id: Id07e1c7fbd35393ffafda53fc7a15ec0e157d075 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-22reset: Convert individual boards to `board_reset()`Nico Huber
Change-Id: I6182da172ae2f4107a9b5d8190e4b3b10ed2f0b9 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-22reset: Provide new single-function reset APINico Huber
board_reset() replaces the existing common reset API. There is no common distinction between reset types across platforms, hence, common code could never decide which one to call. Currently only hard_reset() is used by common code. We replace these calls and provide a fall-back to the current hard_reset() implemen- tation. The fall-back will be removed along with hard_reset() after the transition of all boards. Change-Id: I274a8cee9cb38226b5a0bdff6a847c74ef0b3128 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-19mb/google/octopus: Preserve MRC training data across firmware updateFurquan Shaikh
This change udpates FMAP to wrap MRC training data in RW_PRESERVE section so that we don't lose the data when performing full firmware updates on octopus. BUG=b:117882029 TEST=Verified that chromeos-firmwareupdate doing full firmware update preserves training data on octopus. Change-Id: I5adb9bfa926327057b003360150685a8b4778c8c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-19soc/lowrisc: Remove the remains of a LowRISC socPeter Lemenkov
Looks like we've got a race condition between commit ce8763fb with Change-Id I4e3e715106a1a94381a563dc4a56781c35883c2d ("mb/lowrisc: Remove the Nexys4DDR port") and commit 2e38dbe5 with Change-Id I5524732f6eb3841e43afd176644119b03b5e5e27 ("riscv: update mtime initialization"). Let's fix it. Change-Id: I03c5860b27d04b6e1d7868ba8ea7b52d1075aa6a Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29165 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-19mb/google/fizz: Provide nhlt variant APIDavid Wu
Move current NHLT configuration implementation to baseboard so that variants can leverage it or provide their own configuration. BUG=b:117066935 BRANCH=Fizz TEST=emerge-fizz coreboot Change-Id: I30d93babb6fc09e8642b3740f1f7638fa33f0ade Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-19mb/google/fizz: Provide cros_gpio variant APIDavid Wu
Add support for ChromeOS GPIO ACPI table information by providing weak implementation from the baseboard. BUG=b:117066935 BRANCH=Fizz TEST=emerge-fizz coreboot Change-Id: I2fa52c005cacdbcc322d107a3ac92d22df3f3697 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-19mb/google/fizz: Add variant API for gpioDavid Wu
Provide API for gpio table functionality. Default weak implementations are provided from the baseboard. BUG=b:117066935 BRANCH=Fizz TEST=emerge-fizz coreboot Change-Id: Iaafa8d6932bc0a37826175b15816f1b9a4f4c314 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-19mb/google/fizz: Provide baseboard and variant conceptsDavid Wu
In order to be able to share code across different fizz variants, provide the concept of baseboard and variants. New directory layout: variants/baseboard - code variants/baseboard/include/baseboard - headers variants/fizz - code variants/fizz/include/variant - headers New boards would then add themselves under their board name within "variants" directory. This is purely an organizational change. BUG=b:117066935 BRANCH=Fizz TEST=emerge-fizz coreboot CQ-DEPEND=CL:1273514 Change-Id: I28cc41681e7af88ddeba2e847dc0a4686606feb2 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 03:34:13 +0000