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2017-01-13fsp_baytrail: Enable graphic init per defaultWerner Zeh
Baytrail SoC has a bug where in some cases the DisplayPort can hang leading to a non-working display (it just stays black). To avoid this hang, a patch was introduced in 02/2016 (1c3b1112fa - fsp_baytrail: Fix a possible hanging DisplayPort) but per default not switched on so that each mainboard can decide if it wants to use this patch or not. Recently a new case of this bug was reported by Benoit Sansoni (benoit.sansoni@kontron.com) and he requested to enable this fix per default as it costs him a lot of time to find the cause and even the already available fix in coreboot. To avoid this effort for someone else in the future we can enable this fix per default as no negative side effects are known and it is now tested at Siemens and at Kontron on different mainboards with success. As the goal is to enable this code permanently the config switch is not longer needed and is removed. Change-Id: I15bd682218d0dc887945cc91ee3e5488945a6355 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/18109 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-13sb/nvidia/mcp55: Fix typo in nic.cMartin Roth
The comparison value was obviously wrong here. One too many 'f' characters. Found-by: Coverity Scan #1229588 & 1229604 Change-Id: Iedd4f956d846f1c8661390b346c7397346def86b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18100 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-13rockchip/rk3288: rtc-rk808: fix rtc time reading issueJeffy Chen
After we set the GET_TIME bit, the rtc time can't be read immediately. We should wait up to 31.25 us, about one cycle of 32khz. Otherwise reading RTC time will return a old time. BUG=chrome-os-partner:61078 BRANCH=veyron TEST=Build and Boot Original-Change-Id: I6ec07fc6c4d6d8b27b12031423b86b8ab15da6f6 Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/423272 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Change-Id: I9806b624d6e968e51d52aab8c052ae3fa77f247d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b4b708e29fbae0d8f5a2cece79711aa6b1887727 Original-Change-Id: I8c168c14437bb932a59ac0e91a01062df0cf11dc Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/427522 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18127 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-13gru: Tuning USB 2.0 PHY0 and PHY1 host-portWilliam wu
The commit 0ba3b2593b0c ("gru: Tuning USB 2.0 PHY to increase compatibility") bypass ODT to set the max driver strength for the Type-C otg-port, it works well on otg-port when connected with USB2.0 devices. Unfortunately, because the Type-C otg-port and host-port are consisted in one USB2 PHY, so bypass ODT will have an effect on both host-port and otg-port. I have tested the host-port eye-diagram, the result shows that if we bypass ODT, the host- port eye-diagram height will become to high, more than 500mv, this may cause USB 2.0 high-speed enumeration failure. This patch bypass ODT for host-port separately, and then we can reduce the host-port driver strength without affecting the otg-port driver strength. BRANCH=gru BUG=chrome-os-partner:60727 TEST=Boot system, run 'lsusb' command and check if the usb camera and usb bluetooth are on usb 2.0 hub or usb 1.1 hub. If they are on usb 1.1 hub, the issue happens. If not, try to run camera app and then close camera app, repeat until find that the usb camera is on the usb 1.1 hub. Change-Id: Ib693e2a6f2113c06692a7bfee22d85b67ee3b165 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5ea7660b7b05080b76fc5ca5af3fa18552a03491 Original-Change-Id: Ia1f12182929673c5726df9f77f0903469b5c957a Original-Signed-off-by: William wu <wulf@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/425739 Original-Commit-Ready: Douglas Anderson <dianders@chromium.org> Original-Tested-by: Douglas Anderson <dianders@chromium.org> Original-Tested-by: Inno Park <ih.yoo.park@samsung.com> Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/18126 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-13mb/lenovo/t400,x200,x201: Do not select DRIVERS_ICS_954309Arthur Heymans
This driver to configure the clock generator is not used. Change-Id: I156a42dfc336ff45acdcb6d8618bbd12671b66a7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18104 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-13soc/intel/skylake: Rename car_stage.S for fsp2_0Teo Boon Tiong
Cosmetic changes to rename car_stage.S to car_stage_fsp20.S, so that it is associated with FSP driver version that is being used. Tested on Kabylake Rvp11. Change-Id: I869df6eb746e3982e5912c272255eab6cb008838 Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com> Reviewed-on: https://review.coreboot.org/18083 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-13intel/wifi: Create ACPI objects for wifi SAR configurationRobbie Zhang
To support intel wifi SAR configuration, it is required coreboot to publish two ACPI objects (WRDS and EWRD) to supply SAR limit data sets. VPD entry "wifi_sar" is required to supply the raw SAR limit data. BUG=chrome-os-partner:60821 TEST=Enable USE_SAR, boot reef to OS, create the VPD entry, reboot, check the SSDT dump and verify WRDS and EWRD structures. Change-Id: I6be345735292d0ca46f2f7e7ea61924990d338a8 Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Reviewed-on: https://review.coreboot.org/17959 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-13google/pyro: Add ELAN touch screen supportKevin Chiu
Current fw does not create ACPI device for OS to recognize ELAN touchscreen. List the touch screen in the devicetree so that the correct ACPI device are created. BUG=chrome-os-partner:61803 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: I9015fa63ef3aba74b682da3608a05ee49c4947c5 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/18086 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-12soc/marvell/mvmap2315: Mark mvmap2315_reset() as noreturnMartin Roth
mvmap2315_reset() is called from locations where we're checking for NULL pointers. Because coverity can't tell from the code that the functions are not returning, it's showing errors of accessing pointers after we've determined that they're invalid. Mark it as noreturn, and add a loop in case the reset isn't on the next instruction. This probably isn't needed, but shouldn't hurt. Found-by: Coverity Scan #1362809 Change-Id: If93084629d5c2c8dc232558f2559b78b1ca5de7c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18103 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-12sb/intel/ibexpeak: Update debug code to match other chipsMartin Roth
Other chips dump tco_status here if it wasn't handled, which makes sense. tco_sts can't be zero here, because the call would have already returned if it were. Also, dump_tco_status wouldn't print anything if tco_sts were zero. This will still only print the debug information if DEBUG_SMI is enabled in Kconfig, so in general, this change won't have much of an effect on anything. Found-by: Coverity Scan #1229598 Change-Id: Id2c69a16817ba18dfa051f514138fbc04a2f7bee Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18101 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-123rdparty: update arm-trusted-firmware submoduleMartin Roth
Updated to arm-trusted-firmware TOT: 236c27d2 (Merge pull request #805 from Xilinx/zynqmp/addr_space_size) 183 commits between Sep 20, 2016 and January 10, 2017 - Also add associated change to src/soc/rockship/rk3399 Makefile.inc that is required to build the M0 Firmware. Change-Id: I49695f3287a742cd1fb603b890d124f60788f88f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18024 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-01-12sb/intel/fsp_rangeley: Fix NULL check in gpio.cMartin Roth
This should always have been an and, not an or. The only way this would happen is if no GPIOs were getting configured, so we shouldn't ever have a NULL here, but if we did, GPIOs would be randomly configured, which would have 'interesting' results. Found-by: Coverity Scan #1229633 & 1229632 Change-Id: If123372658383f84279738e1186425beba3208ca Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18095 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-12google/chromeos: disable platform hierarchy on resume for TPM2Aaron Durbin
On Chrome OS devices that use TPM2 parts the platform hierarchy is disabled by the boot loader, depthcharge. Since the bootloader isn't involved in resuming a suspended machine there's no equivalent action in coreboot to disable the platform hierarchy. Therefore, to ensure consistent state in resume the platform hierarchy in the TPM2 needs to be disabled as well. For systems that resume using the firmware the platform hierarchy is disabled when utilizing TPM2 devices. BUG=chrome-os-partner:61097 BRANCH=reef TEST=Suspend and resume. Confirmed 'stop trunksd; tpmc getvf; start trunksd' shows that phEnable is 0. Change-Id: I060252f338c8fd68389273224ee58caa99881de8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/18096 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-01-12amd/mct/ddr2: Remove orphaned Tab_TrefT_k variableTimothy Pearson
The orphaned Tab_TrefT_k causes a failure to build due to an unused variable warning on GCC 6. Remove this variable. Change-Id: Ida680a6a3bc2b135755dd582da8c6edb8956b6ff Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18094 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-12fsp 1.0 systems: Check for NULL when saving HobListPtrMartin Roth
Die if cbmem_add can't allocate memory for the hob pointer. This shouldn't ever happen, but it's a reasonable check. - fsp_broadwell_de already had a check, but it returned to someplace inside the FSP. Just die instead. Change-Id: Ieef8d6ab81aab0ec3d52b729e34566bb34ee0623 Found-by: Coverity Scan #1291162 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18092 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-01-11chromeos: fix build issues within sar.cRobbie Zhang
Build issues were somehow overlooked in commit ed840023a84915ece4bc63edffef979926107d55: 1. hexstrtobin is not defined (needs the lib.h); 2. coreboot default compiler doesn't like variable initialization within for loop. BUG=chrome-os-partner:60821 TEST=Build and boot lars and reef Change-Id: Ie52c1f93eee7d739b8aaf59604875f179dff60d0 Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Reviewed-on: https://review.coreboot.org/18076 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-11amd/mct/ddr3: Fix unintended sign extension warningTimothy Pearson
An unintended sign extension warning was thrown by Coverity. Explicitly state the length of the constant multiplier. Found-by: Coverity Scan #1347342 Change-Id: Icd42eec13be04fc5fd2ffc85320cbadafc852148 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18077 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2017-01-11amd/mct/ddr3: Avoid using uninitialized register address in ECC setupTimothy Pearson
Logic inside mct_EnableDimmEccEn_D uses an unintialized variable as a register address under certain conditions. Refactor mct_EnableDimmEccEn_D to use the explicit address of the register in all cases. Found-by: Coverity Scan #1347337 Change-Id: I6bc50d0524ea255aa97c7071ec4813f6a3e9c2b8 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18079 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-11skylake: Do not pass VBT to FSP if display init not requiredDuncan Laurie
The FSP 2.0 change broke the logic for determining whether or not to execute the GOP binary. Modify the FSP 2.0 code to do the right thing and check for display_init_required() before passing VBT into FSP and the GOP binary. BUG=chrome-os-partner:61726 TEST=disable developer mode and ensure FSP does not run GOP Change-Id: I7fc8055b6664e0cf231a8de34367406eb049dfe1 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18084 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-01-11nb/i945/raminit.c: Use Makefile.inc instead of '#include rcven.c'Arthur Heymans
Change-Id: Ib86600b687c7002646ca82d5fa52121b6eafcd60 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18087 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-11amd/mct/ddr3: Free malloced resources in failure branchesTimothy Pearson
Malloced resources were not freed in failure branches during S3 parameter save. Clean up Coverity warnings by freeing resources in failure branches. Found-by: Coverity Scan #1347344 Change-Id: I5f119874e52ef2090ca1579db170a49a2a6a0a2a Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18074 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-11amd/mct/ddr3: Rework memory speed to clock value conversion logicTimothy Pearson
The existing DRAM clock speed to configuration value logic contained an error resulting in a theoretical out of bounds read. While this would not be hit on real hardware, it was prudent to clean up the logic to avoid the associated Coverity warning. Found-by: Coverity Scan #1347353 Change-Id: Ic3de3074f51d52be112a2d6f2d68e35dc881dd2e Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18073 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-11amd/mct/ddr3: Correctly program maximum read latencyTimothy Pearson
The existing code inadvertently calculated the maximum read latency for nonexistent channel 2 instead of for channels 0 and 1 as intended. Fix the calls to the maximum read latency training function. Found-by: Coverity Scan #1347354 Change-Id: If34b204ac73cd20859102cc3b2f40bc99c2ce471 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18072 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2017-01-10SPD_CACHE: Drop debug statementKyösti Mälkki
Output from CBFS functions is enough. Change-Id: I94d4a20a24f88eeacbe4aeb2e03a15974d18b16c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17923 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-10SPI: Fix command-response behaviorKyösti Mälkki
Fix SPI flash ops regressions after commit: c2973d1 spi: Get rid of SPI_ATOMIC_SEQUENCING When spi_flash_cmd() is called with argument response==NULL, only send out command without reading back the response. Change-Id: I28a94f208b4a1983d45d69d46db41391e267891d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18082 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-01-10amd/mct/ddr3: Allow critical delay delta to go negativeTimothy Pearson
The critical delay delta was incorrectly specified as an unsigned short. Use a signed short instead. Found-by: Coverity Scan #1347355 Change-Id: I37d769afb8c8af85a0375ae459e9d4ab0adcca74 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18071 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2017-01-10amd/mct/ddr3: Correctly configure CsMux45Timothy Pearson
The existing logic to set up CsMux45 used an incorrect mask and comparison value due to a copy + paste editing error. Use the correct mask and comparison value for the last two values. Found-by: Coverity Scan #1347385 Change-Id: Ic08a52977df90b9952e434e71cd12dbc6d7e1443 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18070 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-10amd/mct/ddr3: Wait for northbridge P-state transitionsTimothy Pearson
The existing code waiting for northbridge P-state transitions contained a logical error preventing correct operation. Fix the logical error and force coreboot to wait for the P-state transitions per the BKDG. Found-by: Coverity Scan #1347388 Change-Id: I35f498c836db1439734abe684354c18c8e160368 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18069 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2017-01-10cpu/intel/model_6fx: Add Conroe-L to cpu_device_id listArthur Heymans
Tested with Intel® Celeron® Processor 420. Change-Id: I63d308477a22a9e55ceed1b6b36e63a3044c2354 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18057 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-10nb/intel/945gc: Hardcode the integrated graphic frequenciesArthur Heymans
The code to set the igd frequencies is written with the mobile version of the 945 chipset in mind and seems to cause cause strange igd related problems on the desktop versions. Some possible problems are: * on 800MHz fsb CPUs the igd sometimes has artifacts on the screen; * on 800MHz fsb CPU memtest results vary a lot; * since a commit 45e11aa0a5 "Add/Combine Broadwell Chromebooks using variant board scheme" that does not affect this northbridge, the display shows garbage as soon as Linux (4.8) modesets the display. A fix is to hardcode the core display and render clocks to their maximum, potentially also improving graphical performance. Vendor bios on all boards in coreboot with this northbridge have the same value in this PCI config address. TESTED on P5GC-MX (display works fine again in Linux) and user reports of it making GA-945GCM-S2L run more stable. Change-Id: I8b046edbc952631d9b79023e3d385160ff682c24 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17981 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-10amd/mct/ddr3: Fix incorrect DQ mask calculationTimothy Pearson
On AMD DDR3 platforms, the upper DQMask was incorrectly calculated, leading to undefined behaviour and possible DRAM training faults. Use the correct calculation for the upper DQMask. Found-by: Coverity Scan #1347394 #1347393 Change-Id: If3190eb7c30f1f00d6fd8b751bc1761c9d119782 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18068 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-10mb/lenovo/t400: Increase MAX_CPUS to 4Arthur Heymans
The Lenovo T400 has a CPU socket that can fit quad cores. Change-Id: I585775ac9510cc7d2c2d731531f536c1a56b81e8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18059 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-10amd/mct/ddr2|ddr3: Refactor persistent members of DCTStatStrucTimothy Pearson
Several members of DCTStatStruc are designed to persist across resets of all other members. Move the persistent members into a substructure in order to simplify the reset logic and avoid compiler warnings / UB. Change-Id: I1139b7b3b167d33d99619338d42fcd26e2581a5d Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18058 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-10amd/hudson/agesa: Fix position of hudson_fwmRicardo Ribalda Delgado
AMDFWTOOL calculates the location of the amdfw based on the CONFIG_ROM_SIZE. If HUDSON_FWM_POSITION does not match that location the resulting rom does not boot. This patch forces the position of HUDSON_FWM_POSITION to be the position calculated by amdfwrom. Tested on a Bettong derivative with a 16MiB flash. Change-Id: I3ce69f77174327c18ff97e551c0665c9f633991e Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Reviewed-on: https://review.coreboot.org/17934 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-01-10amd/hudson/pi: Fix position of hudson_fwmRicardo Ribalda Delgado
AMDFWTOOL calculates the location of the amdfw based on the CONFIG_ROM_SIZE. If HUDSON_FWM_POSITION does not match that location the resulting rom does not boot. This patch forces the position of HUDSON_FWM_POSITION to be the position calculated by amdfwrom. Tested on a Bettong derivative with a 16MiB flash. Change-Id: Id2ee96ee076293d48ade84fd6e976ca994dcf491 Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Reviewed-on: https://review.coreboot.org/17925 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-01-10intel/i82801dx: Support 2MiB FWH partKyösti Mälkki
Default setting of southbridge assigned 1MiB of memory for FWH ID 0, while 2MiB is commercially available. Only remap IDs when large ROM is requested in case some board uses multiple FWH parts. Change-Id: I500425f42f755f911d84c6f94a9f3ab5a1ca0b51 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17918 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-01-09chromeos: Implement locating and decoding wifi sar data from VPDRobbie Zhang
A VPD entry "wifi_sar" needs to be created which contains a heximal encoded string in length of 40 bytes. get_wifi_sar_limits() function retrieves and decodes the data from the VPD entry, which would later be consumed by platform code. BUG=chrome-os-partner:60821 TEST=Build and boot lars and reef Change-Id: I923b58a63dc1f8a7fdd685cf1c618b2fdf4e7061 Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Reviewed-on: https://review.coreboot.org/17958 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-09amd/pi: Make BottomIo position configurableRicardo Ribalda Delgado
Some PCI peripherals, such as FPGA accelerators, require a great amount of memory mapped IO. This patch allows the user to select at build time the bottom IO to leave enough space for such devices. We cannot calculate this value at runtime because it has to be set before the PCI devices are enumerated. Change-Id: Ic590e8aa8b91ff89877cbff6afd10614d33dcf8d Credit-to: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Reviewed-on: https://review.coreboot.org/17980 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-01-06Kconfig: Remind users to delete .config when switching boardsMartin Roth
Because Kconfig default values *ONLY* get set when they are first configured, if you switch mainboards with an existing .config, the values will not be set as expected for the new board. This seems to confuse most users, so put a warning in a visible location to let them know. Change-Id: Ie6a9c2d139ecd841d654943f14c119ebafd632f2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17939 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-01-06mb/asus/p5gc-mx: Use common/gpio.hArthur Heymans
Should have been included in 62902ca45d "sb/ich7: Use common/gpio.h to set up GPIOs", which was not rebased on addition of this board. Change-Id: If4547ee43ce6a7a6e4af67e9364613e48f989401 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18047 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2017-01-06nb/intel/*/northbridge.c: Remove #include <device/hypertransport.h>Arthur Heymans
Nothing from that header is used or even declared since CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not selected on Intel hardware. Change-Id: I9101eb6ffa6664a2ab45bc0b247279c916266537 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18044 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2017-01-06sb/ich7: Use common/gpio.h to set up GPIOsArthur Heymans
This is more consistent with newer Intel targets. This a static struct so it is initialized to 0 by default. To make it more readable: * only setting to GPIO mode is made explicit; * only pins in GPIO mode are either set to input or output since this is ignored in native mode; * only output pins are set high or low, since this is read-only on input; * blink is only operational on output pins, non-blink is not set explicitly; * invert is only operational on input pins, non-invert is not set explicitly. Change-Id: I05f9c52dee78b7120b225982c040e3dcc8ee3e4e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17639 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-06arch/x86: fix cmos post logging in non romcc bootblockAaron Durbin
cmos_post_init() is called in src/arch/x86/bootblock_simple.c, and that function is reponsible for bootstrapping the cmos post register contents. Without this function being called none of the cmos post functionality works correctly. Therefore, add a call to lib/bootblock.c which the C_ENVIRONMENT_BOOTBLOCK SoCs use. BUG=chrome-os-partner:61546 Change-Id: I2e3519f2f3f2c28e5cba26b5811f1eb0c2a90572 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/18043 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-01-05src/amd: Add common definition of AMD ACPI MMIO addressTimothy Pearson
The bare ACPI MMIO address 0xFED80000 was used in multiple AMD mainboard files as well as the SB800 native code. Reduce duplication by using a centrally defined value for all AMD ACPI MMIO access. Change-Id: I39a30c0d0733096dbd5892c9e18855aa5bb5a4a7 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18032 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-05mb/ga-m57sli-s4: Fix early uart outputArthur Heymans
The console output is garbled until it is fixed in ramstage by devicetree which sets the uart clock predivider correctly. Change-Id: I6d6ec0febfec98a8d4a71e1476036c804cf5f08d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17969 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-01-04google/auron: Fix omitted ACPI KB backlight for variantsMatt DeVillier
Restores KB backlight functionality for auron variants gandof, lulu, and samus. TEST: boot Lulu and observe KB backlight functional Change-Id: Iaa852f9327ff1690111db610b4cc5266cd7925b4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17960 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-04vboot: Remove rmu.bin from FW_MAIN_A and FW_MAIN_BLee Leahy
Add rmu.bin to the list of files that exist only in the read-only section (COREBOOT) of the SPI flash. TEST=Build and run on Galileo Gen2. Change-Id: I30cbd3fb2ef1848807e4de4c479dc7a561c1faba Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18031 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-04amdfam10: Perform major include ".c" cleanupDamien Zammit
Previously, all romstages for this northbridge family would compile via 1 single C file with everything included into the romstage.c file (!) This patch separates the build into separate .o modules and links them accordingly. Currently compiles and links all fam10 roms without breaking other roms. Both DDR2 and DDR3 have been completed TESTED on REACTS: passes all boot tests for 2 boards ASUS KGPE-D16 ASUS KFSN4-DRE Some extra changes were required to make it compile otherwise there were unused functions in included "c" files. This is because I needed to exchange CIMX for the native southbridge routines. See in particular: advansus/a785e-i asus/m5a88-v avalue/eax-785e A followup patch may be required to fix the above boards. See FIXME, XXX tags Change-Id: Id0f9849578fd0f8b1eab83aed910902c27354426 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/17625 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
2017-01-04intel/i945 boards: Add romstage time stampsPaul Menzel
Currently, some Intel 945 boards miss some or all of the time stamps *1:start of rom stage*, *2:before ram initialization*, and *3:after ram initialization*, so add them. Use the same formatting as used for the board Lenovo X60, which already has code for all the time stamps. Change-Id: Ie25747d02fadd74b7d7b7cab234a7a88b2cc0c42 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/17993 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-01-04soc/intel/quark: Add monotonic timer supportLee Leahy
Add the Kconfig value HAVE_MONOTONIC_TIMER and the routine to read the TSC for the monotonic timer. Simplify the routine to get the TSC frequency. TEST=Build and run on Galileo Gen2 Change-Id: I806fb864b01e39277bf2d6276254b0543930c2f6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18002 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-26 02:29:33 +0000