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2016-05-18rockchip: rk3399: configure emmc clkLin Huang
Select aclk_emmc and clk_emmc source from GPLL, and both to 198MHz, that is GPLL(594MHz) divided by 3. BRANCH=none BUG=chrome-os-partner:51537 TEST=boot kevin rev1 to chromeos prompt from both emmc and sdcard TEST=LoadKernel faster, more than twice as I measured manually. Change-Id: I2580c43b8c79049c3fe16bbf60bfa1a8e0559948 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 5fd37b66dcce77354e1cafab0d6e806d832c08d2 Original-Change-Id: Id22815b302af3204e0e5537af99c1577b09b0877 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/339152 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14855 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-18ec/google/chromeec/acpi: Add MKBP supportGwendal Grignou
Allow EC to send an interrupt using ACPI SMI when a MKBP event is available. This will be used by the sensor stack. Update all ACPI branch except those without sensors with: for i in $(find . -name ec.h -exec grep -l MAINBOARD_EC_SCI_EVENTS {} \+ | cut -d '/' -f 2 | grep -v -e cyan -e lars); do echo $i cd $i git diff ../lars/ec.h | patch -p 5 cd - done BUG=b:27849483 BRANCH=none TEST=Compile on Samus. Tested in Cyan branch. Change-Id: I4766d1d56c3b075bb2990b6d6f59b28c91415776 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: d3b9f76a26397ff619f630c5e3d043a7be1a5890 Original-Change-Id: I56c46ee17baee109b9b778982ab35542084cbd69 Original-Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/342364 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14854 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
2016-05-18rk3399: set proper configuration of SDMMC interfaceVadim Bendebury
For proper interface operation the drive strength on all pins is set to 8 mA and all pull ups/pull downs disabled, this matches the current kernel configuration. BRANCH=none BUG=chrome-os-partner:53257 TEST=it is possible to boot Chrome OS on Gru from various micro SD cards which were failing to boot before. Change-Id: Ie43e52a52cd0513d48d0ecc8ac02fbb100baf9a4 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 6bb0549ed728ac3c5faab6cbe16e2487400e67ed Original-Change-Id: I5180537d3ceb74a9a2f7b3982ca94d3e2daf0369 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/344491 Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14853 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-18rk3399: add GPIO register definitions for SDMMC0Vadim Bendebury
The code needs to be able to set drive strength for the pins used for SDMMC0 interface. This patch adds the definitions for the two registers, as per page 378 of the RK3399 TRM Part 1. Instead of calculation of the reserved range size just use known offsets of the registers included in the structure. BRANCH=none BUG=chrome-os-partner:53257 TEST=with the upcoming driver change it is possible to boot chrome OS on Gru from various micro SD cards which were failing before. Change-Id: I63bf37432ec7f3bdf7e9c6a79d51c31de122dae9 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: c6d6dc5e5e6cc81c173603d4eb21ae803a47815d Original-Change-Id: Ibe7584e77b446435ab1264dcf8fc8bfe0c50438e Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/344490 Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14852 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-18gru: set correct gpio for SD card detectVadim Bendebury
The only outlier at this time is Kevin rev 0, treat it specially, the rest of the targets use the same GPIO. BRANCH=none BUG=none TEST=gru still boots off SD card just fine Change-Id: Ic603093a990d27166b16175db3303f155b4775aa Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 5788c5add1d1f803e7b22fb53215b6003ac04d03 Original-Change-Id: Ic5183f08dd1119f9588f243bd9e9c080d84687f9 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/344151 Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14851 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-18Gru: support 4GB sdram on gruLin Huang
now we use 4GB sdram on gru board, enable it. BRANCH=none BUG=chrome-os-partner:51537 TEST=boot from kevin board Change-Id: Icc483a8ba91c5deea85e6e4009a8a132851b1853 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: efa94aee02bedf51d73c91059b06afcbb1320282 Original-Change-Id: I26f77ff4ad9b2aa35ab5ff50f23984796f4f06bc Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/342585 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14850 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-18rockchip: rk3399: improve sdram driverLin Huang
improve rk3399 sdram drvier, so we can support DDR3, and check the cs training result, so we make sdram work more stable. BRANCH=none BUG=chrome-os-partner:51537 TEST=boot from kevin, do memtester in kernel and pass Change-Id: I508bf26fb8163bab2d725a91ead929df585e04a7 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 4d83a87c459167145b7260f9af5c0380caddc056 Original-Change-Id: Id385f1343804a829b6589f89f4cfbb6565d41417 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/342664 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14849 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-18rockchip: rk3399: add tsadc driverShunqian Zheng
This patch configures clock for tsadc and then makes it in automatic mode to generate TSHUT when CPU temperature is higer than 120 degree Celsius. BRANCH=none BUG=chrome-os-partner:52382,chrome-os-partner:51537 TEST=Set a lower tshut threshold(45C), run coreboot and check that coreboot reboot again and again. Change-Id: I0b070a059d2941f12d31fc3002e78ea083e70b13 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 05107bd6a3430e31db216c247ff0213e12373390 Original-Change-Id: Iffe54d3b09080d0f1ff31e8b3020d69510f07c95 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/342797 Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/14848 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-18rockchip: revert the common tsadc headerShunqian Zheng
The tsadc of rk3288 and rk3399 are similar but not enough to share the same common driver, and we also decide to add a polarity setting for mainboards on rk3399 tsadc header. So we'd better split the tsadc header for each SoC. BRANCH=none BUG=chrome-os-partner:51537 TEST=build veyron_jerry Change-Id: I41f08965e6d7ce16da1754d4d2512c826cf8aff5 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: b36ee54c4146623bcacd83fe7d55a4fc78bae792 Original-Change-Id: I629599f9e30d863cabf764e1372c38f0f39d5480 Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/342796 Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14847 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-18rockchip: rk3399: add routines to set vop clocksShunqian Zheng
Let vop aclk sources from CPLL, and vop dclk from NPLL. The dclk freq is decided by the edid mode pixel_clock which may require high accuracy like 252750KHz. The pll_para_config() can calculate the dividers for PLL to output desired clock. BRANCH=none BUG=chrome-os-partner:51537 TEST=check display with the other patches Change-Id: I12cf27d3d1177a8b1c4cfbd7c0be10204e3d3142 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 0f019b055fffebe9ea3928aae1e25b0ad4feef81 Original-Change-Id: Icef58f87041905961772b69c6b8170d5a866a531 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/342335 Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@google.com> Reviewed-on: https://review.coreboot.org/14846 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-05-18AGESA vendorcode: Build a common amdlibKyösti Mälkki
Having CFLAGS with -Os disables -falign-function, for unlucky builds this may delay entry to ramstage by 600ms. Build the low-level IO functions aligned with -O2 instead. Change-Id: Ice6781666a0834f1e8e60a0c93048ac8472f27d9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14414 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-18AGESA vendorcode: Move compiler class definitionKyösti Mälkki
Change-Id: Ia4cef7d584e43f1911db2f81d8b86ed406b75aad Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14786 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-18soc/intel/apollolake: Enable ACPI PM1 timer emulationAndrey Petrov
Enable emulation for ACPI PM1 timer. This is needed by FSP-M MemoryInit. Change-Id: I7a441f5f1673e6430697615ae7251da948e77548 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14821 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-18soc/intel/apollolake: Remove hardcode for TCO watchdog timerAndrey Petrov
Change-Id: Ie528b0ee3d447dcb819ccb7c0f832885da0f4257 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14820 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-18soc/intel/apollolake: Work around FSP-M CAR layoutAndrey Petrov
As of now FSP-M can not be relocated and it can not be instructed to use a specific resource for temporary memory. As result coreboot is forced to use CAR layout dictated by default FSP-M configuration. Change CAR size to 1MiB, link romstage at such CAR address so it doesn't overlap with FSP-M's default heap/stack. Change-Id: I56f78f043099dc835e294dbc081d7506bfad280d Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14804 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-18soc/intel/apollolake: Do not use StackBase FSP-M parameterAndrey Petrov
Currently, StackBase field doesn't work and changing it from default value leads to crash. Change-Id: Id3f3ea9a834d0c04a8381938535109d6a729cca2 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14803 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-18drivers/intel/fsp2_0: Add recipes for FSP blobs in CBFSAndrey Petrov
Add recipes that insert FSP blobs into CBFS and get rid of CBFS names hardcoding. Change-Id: I350abeffc4d23e45e339464d036716ecdb2ba83a Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14818 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-05-18soc/intel/apollolake: Take advantage of common opregion codeAndrey Petrov
Change-Id: I2d16336513bcd5a0544a6b68b609e40dd7c141fb Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14807 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-18soc/intel/common: Add IGD OpRegion supportAndrey Petrov
Add helper function that fills OpRegion structure based on VBT file content and some reasonable defaults. Change-Id: I9aa8862878cc016a9a684c844ceab390734f3e84 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14806 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-18soc/intel/common: Add utility to load VBT fileAndrey Petrov
Change-Id: I8d3d47ca2fc1fc4c10e61c04b941b6378b9c0f80 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14815 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-18mainboard/intel/galileo: Add I2C chip initializationLee Leahy
Add I2C chip initialization for the Galileo boards. TEST=Build and run on Galileo Gen2 Change-Id: Ib5284d5cd7a67de2f3f98940837ceb2aa69af468 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14829 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-18soc/intel/quark: Add I2C supportLee Leahy
Add the I2C driver. TEST=Build and run on Galileo Gen2 Change-Id: I53fdac93667a8ffb2c2c8f394334de2dece63d66 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14828 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17soc/intel/quark: Fix spelling errorLee Leahy
Change Memroy to Memory in comment. TEST=None Change-Id: Ic57fcf962be6a302dcd7b52b9256a182577e734b Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14881 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17soc/intel/quark: Perform GPIO initializationLee Leahy
Set the base address and enable the GPIO and legacy GPIO controllers. Call the mainboard routine to initialize the GPIO controllers. TEST=Build and run on Galileo Gen2 Change-Id: I06aed5903d6655d2a0948fb544cf9e0db68faa26 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14827 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17mainboard/intel/galileo: Add GPIO initializationLee Leahy
Add Kconfig to configure coreboot for a specific Galileo board. Configure the GPIOs for the specific Galileo board. TEST=Build and run on Galileo Gen2 Change-Id: I992460d506b5543915c27f6a531da4b1a53d6505 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14826 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17acpigen: Fix ?: operator confusionJonathan Neuschäfer
strlen(string) was on the "negative" side of the selection operator, the side where string is NULL. Change-Id: Ic421a5406ef788c504e30089daeba61a195457ae Reported-by: Coverity Scan (CID 1355263) Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/14867 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
2016-05-17intel/sch: Merge northbridge and southbridge in src/socStefan Reinauer
Change-Id: I6ea9b9d2353c0d767c837e6d629b45f23b306f6e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14599 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2016-05-17soc/intel/quark: Add GPIO register accessLee Leahy
Add register access routines for the GPIO and legacy GPIO controllers. TEST=Build and run on Galileo Gen2 Change-Id: I0c023428f4784de9e025279480554b8ed134afca Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14825 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17soc/intel/quark: Add LPC symbolsLee Leahy
Add LPC_DEV and LPC_FUNC symbols TEST=Build and run on Galileo Gen2 Change-Id: I8485e2671af439f766228d4eaf9677c2ff8ff3f6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14880 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17soc/intel/quark: Reformat include/soc/pci_devs.hLee Leahy
Replace # define with #define Align the right hand column to prepare for further expansion TEST=Build and run on Galileo Gen2 Change-Id: Ie4d9fb56d52d7291be5523d31c1d3aa51f94dcd6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14879 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17drivers/intel/fsp1_1: Simplify union referencesLee Leahy
Simplify the union references to enable Coverity to properly process the routine. Found-by: Coverify CID 1349854 TEST=Build and run on Galileo Gen2 Change-Id: I667b9bc5fcde7f68cb9b4c8fa85601998e5c81ff Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14870 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17drivers/intel/fsp1_1: Replace for/break with returnsLee Leahy
Coverity does not like the use of for/break, switch to using returns instead. Found-by: Coverity CID 1349855 TEST=Build and run on Galileo Gen2 Change-Id: I4e5767b09faefa275dd32d3b76dda063f7c22f6f Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14869 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17soc/intel/quark: Add Ioh.h from EDK-IILee Leahy
Add Ioh.h from EDK-II to enable easy comparisons between EDK-II and coreboot implementations. TEST=Build and run on Galileo Gen2 Change-Id: I9320101a4a2c16ed18f682f3d04623c54afb52fd Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14824 Tested-by: build bot (Jenkins) Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2016-05-17drivers/intel/fsp2_0: Fix array indexing errorLee Leahy
Don't allow an array index of 2 to be processed by the code referencing the array. Found-by: Coverity CID 1353337 TEST=None Change-Id: I586ca14416a6e40971f8f6f4066fbdb4908ca688 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14868 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-05-17mainboard/google/reef: add first pass of full pad configurationAaron Durbin
This is an initial stab of configuring the reef pads. Change-Id: I8d8060745af6fbada268c6c6f3492b985ddf9eb8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14831 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@google.com> Tested-by: build bot (Jenkins)
2016-05-16vboot: Call verification_should_run directly in the if statementPaul Kocialkowski
Using a dedicated variable is slightly less readable and makes the code less consistent, given that other test functions are called directly in the if statements. Change-Id: If52b2a4268acb1e2187574d15cc73a0c1d5fe9bb Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/14817 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-05-16acpigen: Add functions to generate _STA() and _PRW()Duncan Laurie
Add helper functions for generating some common objects: acpigen_write_STA(status) will generate a status method that will indicate the device status as provided: Method (_STA) { Return (status) } Full status byte configuration is possible and macros are provided for the common status bytes used for generated code: ACPI_STATUS_DEVICE_ALL_OFF = 0x0 ACPI_STATUS_DEVICE_ALL_ON = 0xF acpigen_write_PRW() will generate a Power Resoruce for Wake that describes the GPE that will wake a particular device: Name (_PRW, Package (2) { wake, level } Change-Id: I10277f0f3820d272d3975abf34b9a8de577782e5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14795 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-16acpigen: Add an abstracted integer output methodDuncan Laurie
In order to produce smaller AML and not rely on the caller to size the output type appropriately add a helper function that will output an appropriately sized integer. To complete this also add helper functions for outputting the single OpCode for Zero and One and Ones. And finally add "name" variants of the helpers that will output a complete sequence like "Name (_UID, Zero)". Change-Id: I7ee4bc0a6347d15b8d49df357845a8bc2e517407 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14794 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-16acpigen: Add helper functions for stringsDuncan Laurie
Add helper function to emit a string into the SSDT AML bytestream with a NULL terminator. Also add a helper function to emit the string OpCode followed by the string itself. acpigen_emit_string(string) /* Raw string output */ acpigen_write_string(string) /* OpCode followed by raw string */ Change-Id: I4a3a8728066e0c41d7ad6429fad983e6ae6962fe Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14793 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-05-16acpigen: Add helpers for word/dword outputDuncan Laurie
Add helpers for writing word and dword values in acpigen and use them throughout the file to clean things up: acpigen_emit_word - write raw word acpigen_emit_dword - write raw dword acpigen_write_word - write word opcode and value Change-Id: Ia758d4dd25d0ae5b31be7d51b33866dddd96a473 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14792 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-16sconfig: Add a new generic device typeDuncan Laurie
Add support for a basic generic device in the devicetree to bind to a device that does not have a specific bus, but may need to be described in tables for the operating system. For instance some chips may have various GPIO connections that need described but do not fall under any other device. In order to support this export the basic 'scan_static_bus()' that can be used in a device_operations->scan_bus() method to scan for the generic devices. It has been possible to get a semi-generic device by using a fake PNP device, but that isn't really appropriate for many devices. Also Re-generate the shipped files for sconfig. Use flex 2.6.0 to avoid everything being rewritten. Clean up the local paths that leak into the generated configs. Change-Id: If45a5b18825bdb2cf1e4ba4297ee426cbd1678e3 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14789 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-05-16sconfig: Add 10bit addressing mode to i2c device typeDuncan Laurie
Use the second token for an i2c device entry in devicetree.cb to indicate if it should use 10-bit addressing or 7-bit. The default if not provided is to use 7-bit addressing, but it can be changed to 10-bit addressing with the ".1" suffix. For example: chip drivers/i2c/generic device i2c 3a.1 on end end Change-Id: I1d81a7e154fbc040def4d99ad07966fac242a472 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14788 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-13mainboard/google: add reef reference boardAaron Durbin
This adds the initial scaffolding for the reef reference board. One big thing missing is the GPIO configuration. Change-Id: I8e2d275df296bb397bb33dbd0c66fc87c82ff10f Signed-off-by: Aaron Durbni <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14798 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-13soc/intel/apollolake: provide common LPDDR4 memory initAaron Durbin
Instead of having the mainboards duplicate logic surrounding LPDDR4 initialization provide helpers to do the heavy lifting. It also handles the quirks of the FSP configuration which allows the mainboard porting to focus on the schematic/design. Change-Id: I686eb3097c33399a3b94af89237f7fe1b2d34c2f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14790 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-13vendorcode/intel/fsp1_0: Don't break GCC strict aliasingStefan Reinauer
Change-Id: I6b345670db7df652b8b712b721dfe2905373e0d5 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14630 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-by: York Yang <york.yang@intel.com>
2016-05-13HobLib: Don't break GCC strict aliasingStefan Reinauer
Change-Id: I1bd33e423b0fcb69597e001b61c6ea916f5fe44a Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14622 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-05-13AMD fam14: Blacklist Intel Centrino n6235 from PCIe ASPMKyösti Mälkki
PCI device ID of this mini-PCI-e WLAN card is 8086:088e. With this card inserted on pcengines/apu1 mini-PCI-e slot J17, system halts late in ramstage, in agesawrapper AMD_INIT_MID. Offending operation is enabling PCIe ASPM L0s and L1 for the card. That is, writing PCIe capability block Link Control [1:0] = 11b in the card's configuration space. AGESA already has a blacklist for the purpose of masking such unstable ASPM implementations. Change-Id: I9623699c4ee68e5cdc244b87faf92303b01c4823 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/8496 Tested-by: build bot (Jenkins) Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-13soc/intel/apollolake: implement common gpio APIAaron Durbin
In order for apollolake mainboards to utilize the common GPIO API it actually needs to be implemented. Change-Id: I41de8d5d9f3c39e7e796eae73b01cb29e9c01347 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14797 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-13ec/google/chromeec: don't guard function declarationsAaron Durbin
In order to allow using the same C source to be compiled for multiple stages (with #if/#endif guards) one needs the necessary function delcarations. Therefore, remove the guards. Change-Id: Iea94d456451c5d3db8b8b339e81163b3b3fed3ed Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14796 Reviewed-by: Duncan Laurie <dlaurie@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-12soc/intel/apollolake: use common FADT infrastructureAaron Durbin
Instead of having the mainboards duplicate the same boilerplate code utilize the common FADT infrastructure to reduce duplication. Change-Id: If824619fd619433974e588050a933d2c19b97ec8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14779 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 10:56:10 +0000