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2017-11-15soc/intel/common: Use HOST_CSR to get circular Buffer DepthSubrata Banik
As per CSME BWG section 3.4.4. The Circular Buffer Depth can find by checking B0:D22:F0 MMIO_HOST_CSR register. TEST=Build and boot eve/soraka/reef/cnl-rvp Change-Id: I1d3c09077e040b5c32b3c8be867a07f392ea4e1c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-15soc/intel/common: Add HECI message retry countSubrata Banik
Send/Receive HECI message with 5 retry count in order to avoid HECI message failure. TEST=Build and boot eve/soraka/reef/cnl-rvp Change-Id: I76662f8080fe312caa77c83d1660faeee0bdbe7e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22443 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-15soc/intel: Enable ACPI DBG2 table generationDuncan Laurie
Enable the ACPI DBG2 table generation for Intel boards. This is a Microsoft defined ACPI extension that allows an OS to know what the debug port is on a system when it is not enabled by the firmware, so it does not show up in the coreboot tables and cannot be easily found by a payload. broadwell: Use byte access device, set up only when enabled since it relies on the port being put in byte access mode and using this serial port for debug was not standard in this generation. skylake: Enable for the configured debug port. Skylake uses intelblocks for UART but not ACPI. common: Enable for the configured debug port. This affects apollolake and cannonlake. Tested by compiling for apollolake/broadwell, tested by reading the DBG2 ACPI table on kabylake board and using IASL to dump: [000h 0000 4] Signature : "DBG2" [004h 0004 4] Table Length : 00000061 [008h 0008 1] Revision : 00 [009h 0009 1] Checksum : 3B [00Ah 0010 6] Oem ID : "CORE " [010h 0016 8] Oem Table ID : "COREBOOT" [018h 0024 4] Oem Revision : 00000000 [01Ch 0028 4] Asl Compiler ID : "CORE" [020h 0032 4] Asl Compiler Revision : 00000000 [024h 0036 4] Info Offset : 0000002C [028h 0040 4] Info Count : 00000001 [02Ch 0044 1] Revision : 00 [02Dh 0045 2] Length : 0035 [02Fh 0047 1] Register Count : 01 [030h 0048 2] Namepath Length : 000F [032h 0050 2] Namepath Offset : 0026 [034h 0052 2] OEM Data Length : 0000 [036h 0054 2] OEM Data Offset : 0000 [038h 0056 2] Port Type : 8000 [03Ah 0058 2] Port Subtype : 0000 [03Ch 0060 2] Reserved : 0000 [03Eh 0062 2] Base Address Offset : 0016 [040h 0064 2] Address Size Offset : 0022 [042h 0066 12] Base Address Register : [Generic Address Structure] [042h 0066 1] Space ID : 00 [SystemMemory] [043h 0067 1] Bit Width : 00 [044h 0068 1] Bit Offset : 00 [045h 0069 1] Encoded Access Width : 03 [DWord Access:32] [046h 0070 8] Address : 00000000FE034000 [04Eh 0078 4] Address Size : 00001000 [052h 0082 15] Namepath : "\_SB.PCI0.UAR2" Change-Id: If34a3d2252896e0b0f762136760ab981afc12a2f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/22453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-15arch/x86/acpi: Add support for writing ACPI DBG2 tableDuncan Laurie
Add a function to create an ACPI DBG2 table, which is a Microsoft ACPI extension for providing a description of the available debug interface on a board. A convenience function is provided for creating a DBG2 table with a 16550 UART based on a PCI device. This is tested by generating a device and verifying it with iasl: [000h 0000 4] Signature : "DBG2" [004h 0004 4] Table Length : 00000061 [008h 0008 1] Revision : 00 [009h 0009 1] Checksum : 3B [00Ah 0010 6] Oem ID : "CORE " [010h 0016 8] Oem Table ID : "COREBOOT" [018h 0024 4] Oem Revision : 00000000 [01Ch 0028 4] Asl Compiler ID : "CORE" [020h 0032 4] Asl Compiler Revision : 00000000 [024h 0036 4] Info Offset : 0000002C [028h 0040 4] Info Count : 00000001 [02Ch 0044 1] Revision : 00 [02Dh 0045 2] Length : 0035 [02Fh 0047 1] Register Count : 01 [030h 0048 2] Namepath Length : 000F [032h 0050 2] Namepath Offset : 0026 [034h 0052 2] OEM Data Length : 0000 [036h 0054 2] OEM Data Offset : 0000 [038h 0056 2] Port Type : 8000 [03Ah 0058 2] Port Subtype : 0000 [03Ch 0060 2] Reserved : 0000 [03Eh 0062 2] Base Address Offset : 0016 [040h 0064 2] Address Size Offset : 0022 [042h 0066 12] Base Address Register : [Generic Address Structure] [042h 0066 1] Space ID : 00 [SystemMemory] [043h 0067 1] Bit Width : 00 [044h 0068 1] Bit Offset : 00 [045h 0069 1] Encoded Access Width : 03 [DWord Access:32] [046h 0070 8] Address : 00000000FE034000 [04Eh 0078 4] Address Size : 00001000 [052h 0082 15] Namepath : "\_SB.PCI0.UAR2" Raw Table Data: Length 97 (0x61) 0000: 44 42 47 32 61 00 00 00 00 3B 43 4F 52 45 20 20 // DBG2a....;CORE 0010: 43 4F 52 45 42 4F 4F 54 00 00 00 00 43 4F 52 45 // COREBOOT....CORE 0020: 00 00 00 00 2C 00 00 00 01 00 00 00 00 35 00 01 // ....,........5.. 0030: 0F 00 26 00 00 00 00 00 00 80 00 00 00 00 16 00 // ..&............. 0040: 22 00 00 00 00 03 00 40 03 FE 00 00 00 00 00 10 // "......@........ 0050: 00 00 5C 5F 53 42 2E 50 43 49 30 2E 55 41 52 32 // ..\_SB.PCI0.UAR2 0060: 00 // . Change-Id: I55aa3f24776b2f8aa38d7da117f422d8b8ec5479 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/22452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-15soc/intel/cannonlake: Fix and clean up xhci ACPI codeVaibhav Shankar
During S3 cycling, system entered S3 only once and falied to enter S3 the second time. The system gets stuck at this point and we have to do a cold reboot to restore the system. Since XHCI IP is able to power gate during kernel freeze/suspend, this patch removes unnecessary device gating from ASL. This helps in continuous cycling of S3. BUG=b:69115421 TEST=run powerd_dbus_suspend multiple times and check if the system enters and resumes from S3. Change-Id: Id459631ea2d32feea4b8f658fd34fa25945f909e Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/22389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-15device: further untangle device_t from struct deviceAaron Durbin
This further allows compilation units to be re-used without having to add macro guards because of declarations not being around in the __SIMPLE_DEVICE__ case. These declarations are for functions that operate on struct device. struct device is a known type so just expose the functions using the correct type. Also, DEVTREE_CONST is empty while in ramstage so there's no reason to separate the declarations. Lastly, fix up device_util.c to use the proper types. It's only compiled in ramstage and it only operates on struct device. Change-Id: I306e0ad220cdab738cb727dda4a93bdec77c5521 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14mb/google/eve: Add DSP calibration clock name/rate for RT5514Cheng-Yi Chiang
Add a property for DSP calibration clock name and rate such that RT5514 codec driver can control ssp1_mclk for DSP clock calibration. BUG=b:67763576 TEST=boot on eve check RT5514 codec driver can get this device property. Change-Id: Icf9695ef67efb2bb073e39b2ece02d57f0460a0c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org> Original-Change-Id: Ie204dda81a099f23beb20be71380a8494a9bee31 Original-Reviewed-on: https://chromium-review.googlesource.com/756261 Original-Reviewed-by: Dylan Reid <dgreid@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/22451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14mb/google/eve: Set DSP SPI clock to 12MHzDuncan Laurie
To enable faster download of hotword data set the SPI clock to the Realtek 5514 DSP chip to 12MHz instead of the default 1MHz. BUG=b:67763576, b:66161281 TEST=cras_test_client --listen /tmp/rec.raw, trigger hotword, and check the samples using hexdump or cras_test_client --playback_f /tmp/rec.raw Change-Id: I92710eae25613a8202c63888b86a269803c40fe6 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org> Original-Change-Id: I7e50d755a90d739b6dec155228351c3974b2f3b9 Original-Reviewed-on: https://chromium-review.googlesource.com/686675 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Chinyue Chen <chinyue@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Original-Tested-by: Chinyue Chen <chinyue@chromium.org> Original-Commit-Queue: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/22450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14mb/google/eve: Enable VMXDuncan Laurie
This feature was enabled at the kernel level, but that is triggering an issue where FSP expects it to be disabled so it forces a cold reboot on every warm reboot. Since we want this enabled anyway just set it this way in the BIOS so it matches what the kernel expects. BUG=b:68666100 TEST=pass firmware_FWtries on Eve with R63 OS image Change-Id: I294e34d25406365d591da06ce4c931b710cfbbaa Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Change-Id: I964d3d30392d130e808f37a661f2c89ec926cf58 Original-Signed-off-by: Duncan Laurie <dlaurie@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/749733 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14mb/google/eve: Tune I2C4 hold timesDuncan Laurie
Tune PCH I2C4 hold times to ensure the frequency is always <400KHz. BUG=b:67029862 TEST=boot on eve and measure I2C4 at Tp262 to be 385KHz Change-Id: Ie93c5c40bc74069b285f6c3ee311f1bd7cefcaf1 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Change-Id: Iceabc806a17b9e6a144a4f6288c6cca790d03950 Original-Signed-off-by: Duncan Laurie <dlaurie@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/739841 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14mb/google/eve: Enable AER and LTRFurquan Shaikh
AER and LTR must be enabled individually on ports that need it, in this case it should be enabled for WiFi and NVMe. BUG=b:65457528 TEST=Wifi team verified that the performance is better with these changes. Change-Id: I0d688fe07a1f3117c1ca617c2ce78e0d024a3510 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Change-Id: Ib059517fa782ccc18ba5ef1f76058a1898b7bf7a Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/671211 Original-Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Original-Commit-Queue: Duncan Laurie <dlaurie@google.com> Original-Tested-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/22447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14mb/google/eve: Use rt5663 driver and set propertiesDuncan Laurie
Use the rt5663 driver and provide values for the offsets which are needed for providing manual values to compensate the DC offset for L and R channels between headphone and headset. BUG=b:62712227 TEST=build and boot on eve and ensure rt5663 is functional. Change-Id: I88113616e4b7c79cff840168b7c54ae754dfa75f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Change-Id: Ica4090636c1ff29f0298114e62c9cc6fe167a425 Original-Signed-off-by: Duncan Laurie <dlaurie@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/611606 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Hsinyu Chao <hychao@chromium.org> Reviewed-on: https://review.coreboot.org/22446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14mb/google/eve: Remove ACPI control of touchscreen powerDuncan Laurie
Change the touchscreen power control back to coreboot instead of under the ACPI _ON/_OFF methods, and switch the TOUCHSCREEN_STOP_L pin back to an output. This reverts previous changes to touchscreen GPIOs that were made to get back to a known good/working state. Having ACPI control these pins was resulting in a small percentage of touchscreen not being discovered at boot. This platform is not intending to use S0ix so the ACPI control is not needed. BUG=b:63718744 TEST=manual testing on Eve devices. Change-Id: I3fd64a435a053da1558ef736fe7baceee3c8f3a0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Change-Id: Ia1e2ae7ca2a8b668c60fbda2aa50373e580646b2 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/572692 Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Original-Commit-Queue: Duncan Laurie <dlaurie@google.com> Original-Tested-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/22445 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14mb/amd/gardenia: Remove direct AGESA header includesMartin Roth
All AGESA headers should be included only through agesawrapper.h BUG=b:66818758 TEST=Build gardenia Change-Id: I3c9ae7a435fadabf577f1f65ad4a6aa6234e9a29 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-14soc/amd/stoneyridge: Remove direct AGESA header includesMartin Roth
All AGESA headers should be included only through agesawrapper.h BUG=b:66818758 TEST=Build gardenia; Build & boot kahlee Change-Id: Iadc516e11148048ed9bf43c7a46827793245027a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-14soc/amd/common: Remove direct AGESA header includesMartin Roth
All AGESA headers should be included only through agesawrapper.h BUG=b:66818758 TEST=Build gardenia; Build & boot kahlee Change-Id: I94140235f46a627dda99540af8619aeca3f4f157 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-14mb/google/kahlee: Remove direct AGESA header includesMartin Roth
All Stoney AGESA headers should be included only through agesawrapper.h BUG=b:66818758 TEST=Build and boot tested Change-Id: I642f5caf8a37ae4042c32fec3a92e0995193cb7a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-14AMD Stoney Ridge: Add agesa_headers.hMartin Roth
- Create header files for the stoneyridge PI that pulls in AGESA pi headers and encloses them in #pragma pack push/pop to keep the '#pragma pack(1)' in Porting.h from leaking. - Add that header to agesawrapper.h, replacing AGESA.h and Porting.h Following patches will update the coreboot code to use only agesawrapper.h to pull in the AGESA headers. BUG=b:66818758 TEST=Build tested Change-Id: Ib7d76811c1270ec7ef71266d84f3960919b792d4 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-14ec/lenovo/h8/acpi/ec: Add registersPatrick Rudolph
Add register HPPI and GSTS. Add method WLSW that is used by thinkpad_acpi kernel module. Seperate method by an empty newline. Change-Id: I5a125047fad0e08cd9256bc53c3f5a7db7e56e7d Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-11-14amd/common/spi: Update flash driver usageMarshall Dawson
Fix how the SPI driver is accessed in spi_SaveS3info. This code has been unused to date. Change-Id: Ie2b97c13079fd049f6e02f3ff8fa630ed880343f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-14soc/amd/stoneyridge: Load SMU fimware using PSPMarshall Dawson
Add the ability to locate the SMRAM-based SMU firmware early and call the PSP library to load it prior to DRAM initialization. This is currently placed in bootblock to ensure the blob is loaded before any reset occurs. Add similar functionality in ramstage for SMU FW2 to the hook already in place for running AmdInitEnv. Rename the hook to make more sense. This patch was tested using a pre-released PSP bootloader on a google/kahlee system. Leave the option unused until the bootloader is ready. BUG=b:66339938 Change-Id: Iedf768e54a7c3b3e7cf07e266a6906923c0fad42 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-14amd/stoneyridge: Add generic IMC sleep and wakeupMarshall Dawson
Hudson code, the basis for soc//stoneyridge southbridge, has typically contained direct calls to vendorcode/amd//ImcLib.c. In an effort to keep #include files clean in other stoneyridge files, put the new calls into imc.c. Change-Id: I830d5431635ac4acaf3c3c974cb452847dc147cd Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-11-14amd/stoneyridge: Replace BIT(n) in southbridgeMarshall Dawson
Use more descriptive #define values for the ACPI features and register decoding. Change-Id: Iaaf9f9bd5761001bc4bfe6b64a6c72b1f04844bd Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22427 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-14amd/stoneyridge: Define bits for AcpiConfigMarshall Dawson
Add defintions for PMx74. Change-Id: Id9483be9032abe6fbd5a6ec2af6bb8869a4ab766 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22426 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-13mb/google/kahlee: Add getter function for GPIO arrayMartin Roth
Instead of getting the address of the GPIO function with an extern, add a getter function and make the GPIO arrays static. TEST=Build Grunt; Build & boot Kahlee BUG=b:69164070 Change-Id: I3defcb66696459b915d7d4f43234d5c08ab7d417 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-13mb/google/kahlee: Remove mainboard.hMartin Roth
mainboard.h only had a single function definition. Move it into baseboard/variants.h and get rid of the file. TEST=Build grunt/kahlee BUG=b:69164070 Change-Id: I6b7d50d5c949733d77c42b4daf56ed1f97ed6954 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-13mainboard/google/kahlee: Add Grunt variant frameworkMartin Roth
Update common files and add files for grunt to the variant directory. BUG=b:68293392 TEST=Build only Change-Id: I7b80e470058872d6613e66e64c8dd1494942e9b9 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-13mainboard/google/kahlee: Add baseboard frameworkMartin Roth
BUG=b:68293392 TEST=Build only Change-Id: Ie4d039b4da10a992fc9dd2b0221fd4a1644aae6a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-13soc/intel/common: Add error print in common i2cLijian Zhao
Print error message when using common i2c without default clock defined. TEST=Do not define default clock in Kconfig, compile will stop for assertion. Change-Id: I803f97698b3928e6b64df0010e71a6ded1400f87 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-11-13soc/intel/cannonlake: Define default LPSS clockLijian Zhao
Default LPSS clock need to be defined for SOC. TEST=Turn on COMMON_I2C_DEBUG, add I2C clock entry and check I2C programing properly during coreboot. Change-Id: I2c6b9bb23950b09f6f05e3ef762ccb1a260efc5f Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-13soc/amd/stoneyridge: Add CPU PPKG ASLMarc Jones
Add PPKG Method for processor passive thermal control list. BUG=b:67999819 Change-Id: I5d84832af06f64c923485926e4e0c73c65a2b0b2 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22399 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-13soc/amd/stoneyridge: Add GNVS variables for thermal controlMarc Jones
BUG=b:67999819 Change-Id: I78db830c14092f5e918657e62bf38ab7124b1646 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-13amd/gardenia: Add globalnvs.aslMarc Jones
Stoney Ridge ASL uses global NVS for sharing data between ACPI and SMM. Change-Id: I8f497870844da1f56ff5c3b126d5613be36a9bfb Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-13soc/amd/stoneyridge: Fix DRAM clear checkMarshall Dawson
Explicitly add #include files to romstage.c to ensure sizes of the devicetree structures are correct. The AMD support headers have an open #pragma pack(1) which causes structure sizes to change based on include ordering in different compilation units. More concretely, this fixes a bug where dev->chip_info is incorrectly detected as 0. Also shorten a printk string to bring the source line within 80 columns. Change-Id: I1ed51cdbb8df387a453de6cb944b90538dac4431 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-13google/chell: add missing SPD hex filesMatt DeVillier
Several SPD hex files for chell were missing from upstream coreboot (as compared to the Chromium tree/branch), which resulted in the incorrect type and amount of RAM being reported on chell boards with > 4GB RAM. Add these missing files and their Makefile entries. TEST: boot google/chell m7/16GB config and observe correct RAM type and amount reported via dmidecode and cbmem console log. Change-Id: I37d708c96e754b438e40fc413420aa64bf234c29 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22402 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-11intel/fsp: Update cannonlake FSP headerLijian Zhao
Update cannonlake FSP header to revision 7.x.11.43. Following changes had been made: 1.Remove Minimum control ration from FSPM UPD. 2.Add Intersil VR command option in FSPS UPD. 3.Add minimum and maxiam ring ratio override. TEST=None Change-Id: I63c990e5766370a82dc1c044bcf744612229a605 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-11vendorcode/amd/pi/00670f00: Set ModuleIdentifier to be 8 bytesMartin Roth
ModuleIdentifier must be 8 bytes. Every other location else that uses this value explicityly defines it as 8 bytes. If it's initialized here to less than 8 bytes, it gets passed to those other locations with garbage at the end and fails to load the AGESA binary. TEST=Build & boot Kahlee BUG=B:69165234 Change-Id: I11fc90748f49782e2b16ee5326aee17cfe92d0bc Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-11soc/intel/apollolake: Make use of Intel SPI common blockSubrata Banik
TEST=Build and boot reef Change-Id: I1bb22ef1737b9e35892294ec0d66df39c546d72e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-11soc/intel/apollolake: Add support for SPI deviceSubrata Banik
Provide a translation table to convert SPI device structure into SPI bus number and vice versa. Change-Id: I4c8b23c7d6f289927cd7545f3875ee4352603afa Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-11soc/intel/cannonlake: Make use of Intel SPI common blockSubrata Banik
TEST=Build and boot RVP Change-Id: I5ff9867f08e43016a797b1b3719053df0c382174 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-11soc/intel/skylake: Make use of Intel SPI common blockSubrata Banik
TEST=Build and boot soraka/eve Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I10de3ff75a3b063c4c46471e380bbbe2630c35f3 Reviewed-on: https://review.coreboot.org/22361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-11soc/intel/{cannonlake,skylake}: Add _soc_ prefix in spi soc routineSubrata Banik
This ensures that function callback into the SoC code. Change-Id: Idc16d315ba25d17a2ab537fcdf0c2b51c8802a67 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-11soc/intel/common/block: Add Intel common SPI supportSubrata Banik
SOC need to select specific macros need to compile common SPI code. Change-Id: I82f7d1852d12ca37f386b64a613a676753da959c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-10google/kahlee: Use devicetree register values for UMAMarshall Dawson
Set the UMA memory size to 128 MiB. This value was empirically tested by AMD as the lowest value one could use. BUG=b:64927639 TEST=default, and 64, 128, 256, 384MB non-legacy configurations. Change-Id: I2bc808d8b402c3eb16a1a5962f3fa9d6b224cf52 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/21335 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-10soc/amd/stoneyridge: Add UMA settings to devicetreeAaron Durbin
Add three settings for the UMA configuration to correspond with definitions in AGESA.h. * UMA off, Auto, or size specified * Size (if specified above) * Legacy vs. non-legacy (if Auto) BUG=b:64927639 Change-Id: I38b6603f365fdc1f1f615794365476f749e58be7 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-10amd/stoneyridge: Implement vboot_platform_is_resumingMarshall Dawson
Change-Id: I23882ad8cd93fbc25acd8a07eca6a78b6bafc191 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-10amd/stoneyridge: Add function to find Pm1EvtBlk baseMarshall Dawson
The AcpiPm1EvtBlk base I/O address is configured in PMx60. Add a helper function to read this. The register is not lockable so it shouldn't be assumed to be at its original address. Change-Id: I91ebfb454c2d2ae561e658d903f33bfb34e1ad6f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-10amd/stoneyridge: Remove dead southbridge definitionsMarshall Dawson
The revision level is not checked. This was probably left over from trying to determine hudson variants. Remove the unused SMI command port values. This was missed in: e9b862e amd/stoneyridge: Use generic SMM command port values Change-Id: I91d8051372f4e238d390dd445d0bf06d06683a66 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-10amd/stoneyridge: Add more ACPI register definitionsMarshall Dawson
Change-Id: I62a840499deed895cf474f1bfce1f399c970e589 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-10amd/stoneyridge: Use the new generic acpi_sleep_from_pm1Marshall Dawson
Unhardcode the acpi_get_sleep_type() function and rely on the new function in arch/acpi.h. Change-Id: Icd49c44fae43effb9f082db354abd327cad9f1ad Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 13:46:15 +0000