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2012-11-09Add Gigadevice SPI rom supportMartin Roth
Add support for GigaDevice SPI ROMS. The GD25Q64B device has been tested, the other rom devices added to the file have not. Change-Id: If35676ca6b90329f15667ebb32efa0d1a159ae91 Signed-off-by: Martin Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/1747 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-09ELOG: Add EC events to elog headerDuncan Laurie
These events were initially for Chrome EC but they can be applied to any EC. Change-Id: I0eba9dbe8bde506e7f9ce18c7793399d40e6ab3b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1746 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-09SPI: re-init SMM SPI driver after lockdownDuncan Laurie
If the driver is initialized before the lockdown then it will fail to work after the lockdown bit is set. Change-Id: Idc05d33d8d726bf29cb3c9b1b4604522bd64170a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1745 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-09Change flashmap base to reflect new FMAP in U-bootDuncan Laurie
The RO_FMAP base moved from 0x5f0000 to 0x610000. Also update Kconfig default and add a descripton so the default can be changed by boards. Change-Id: I0caad0ce6e6f19750dbbf042a5a489b558f62b96 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1705 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-09mc146818rtc: Remove the hyphen to build on NetBSD and DarwinZheng Bao
http://netbsd.gw.com/cgi-bin/man-cgi?date++NetBSD-current The NetBSD manual tells us the date in NetBSD doesn't take any flags to enable or disable padding in the format. By default, date pads numeric fields with zeroes. This will convert the number to octal one. So add "0x" to convert it to BCD directly. Change-Id: Icd44312acf01b8232f1da1fbaa70630d09007b40 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1804 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-11-09mc146818rtc: Update the Day of Week in CMOS in the right way.Zheng Bao
The range of weekday in CMOS is 01-07, while the Sunday is 1, and Saturday is 7. The comand date in coreutils defines %u day of week (1..7); 1 is Monday %w day of week (0..6); 0 is Sunday There are 1 day offset for each week day. So we use "%w" and plus 1 before we update the weekday in CMOS. Change-Id: I3fab4e95f04924ff0ba10a7012b57da1d3f0d1a5 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1802 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-11-08mainboard/roda/rk886ex: Disable CHECK_SLFRCS_ON_RESUMENico Huber
This makes resume from S3 work again. The check is new and fails on other boards, too. Change-Id: I0ada569e4ba649b9ac82768b0888e16104c621e8 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1809 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-08Log unexpected post code from the previous bootDuncan Laurie
Read out the post code from the previous boot and log it if the code is not one of the expected values. Test: 1) interrupt the boot of the system, this is easiest with warm reset button when servo is attached 2) check the event log with mosys 65 | 2012-09-09 12:32:11 | Last post code in previous boot | 0x9d Change-Id: Id418f4c0cf005a3e97b8c63de67cb9a09bc57384 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1744 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-08Add support for storing POST codes in CMOSDuncan Laurie
This will use 3 bytes of CMOS to keep track of the POST code for the current boot while also leaving a record of the previous boot. The active bank is switched early in the bootblock. Test: 1) clear cmos 2) reboot 3) use "mosys nvram dump" to verify that the first byte contains 0x80 and the second byte contains 0xF8 4) powerd_suspend and then resume 5) use "mosys nvram dump" to verify that the first byte contains 0x81 and the second byte contains 0xFD Change-Id: I1ee6bb2dac053018f3042ab5a0b26c435dbfd151 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1743 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-08x86 memcpy: Copy 4 bytes at onceStefan Reinauer
This is a slight improvement over the rep movsb loop Change-Id: Id71d9bfe5330b154a5c62fac85ce3955ae89b057 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1742 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-08RTC: Don't clear pending interrupt in resume pathDuncan Laurie
The linux kernel relies on the RTC reporting pending interrupts if the RTC alarm was used to wake the system. If we clear these flags here then the rtc-cmos driver in the kernel will think that no interrupts are pending and will not re-start the timerqueue to handle the alarm timerqueue node. This flag doesn't exist in SMM but the rtc code is compiled there. Since rtc_init() is not called by SMM it is guarded with an ifdef. I performed several thousand suspend/resume cycles without seeing an issue where hwclock was unable to read from /dev/rtc. There still is a potential kernel issue where the timerqueue can stall but this makes that much less likely to happen on resume. Change-Id: I5a343da4ce5c4c8ec4783b4e503869ccfa5077f0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1741 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-08smi: make tseg_relocate check pointer offsetDuncan Laurie
In case tseg_relocate() is called again on a pointer we should not relocate it again. Change-Id: Ida1f9c20dc94b448c773b14d8864afe585369119 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1740 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-08elog: add extended management engine eventDuncan Laurie
We are seeing ME disabled and ME error events on some devices and this extended info can help with debug. Also fix a potential issue where if the log does manage to get completely full it will never try to shrink it because the only call to shrink the log happens after a successful event write. Add a check at elog init time to shrink the log size. Change-Id: Ib81dc231f6a004b341900374e6c07962cc292031 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1739 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-08spi: fix erase in SMM while SPIBAR is lockedDuncan Laurie
The handling of write enable was not entirely correct, the opcode needs to be skipped when the controller is locked down. Addresses were not getting set properly for erase commands which seemed to mostly work when the previous command had set an address. Tested by adding events to the event log at runtime on a freslhy flashed device (with locked down SPI controller) until the log log shrink happens to ensure it does not hang: hexdump -C elog.event.kernel_clean 00000000 01 00 00 00 ad de 00 00 00 00 for x in $(seq 1 232); do cat elog.event.kernel_clean > /sys/firmware/gsmi/append_to_eventlog done mosys eventlog list | tail -6 154 | 2012-09-01 13:54:43 | Kernel Event | Clean Shutdown 155 | 2012-09-01 13:54:43 | Kernel Event | Clean Shutdown 156 | 2012-09-01 13:54:43 | Kernel Event | Clean Shutdown 157 | 2012-09-01 13:54:43 | Kernel Event | Clean Shutdown 158 | 2012-09-01 13:54:43 | Log area cleared | 1030 159 | 2012-09-01 13:54:43 | Kernel Event | Clean Shutdown Change-Id: I3a50dae54422a9ff37daefce3632f8bcbe4eb89f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1717 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-08Make option rom init more verboseStefan Reinauer
When bringing up VGA by running the option rom it's sometimes useful to get more information about the mode that gets set, or the reason why the mode could not be set or a picture could not be displayed. Also prefix the output from VBE mode setting with VBE: Copying VGA ROM Image from fff0fd78 to 0xc0000, 0x10000 bytes Real mode stub @00000600: 867 bytes Calling Option ROM... int15_handler: INT15 function 5fac! ... Option ROM returned. VBE: Getting information about VESA mode 4161 VBE: resolution: 1280x1024@16 VBE: framebuffer: d0000000 VBE: Setting VESA mode 4161 VGA Option ROM has been loaded Change-Id: I2be11f095dc62ed3c99e0d4272ad9d6521608a44 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1714 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-08ELOG: Find flash base in FMAP if possibleDuncan Laurie
Now that we have FMAP support in coreboot use it to find the offset in flash for ELOG to use. If coreboot has elog configured with a smaller size then use that over the FMAP size. This is because I set aside a 16KB region in the FMAP but we only use 4KB of it to keep the impact to boot/resume speed to a minimum. FMAP: Found "FMAP" version 1.0 at ffe10000. FMAP: base = 0 size = 800000 #areas = 32 FMAP: area RW_ELOG found FMAP: offset: 3f0000 FMAP: size: 16384 bytes FMAP: No valid base address, using 0xff800000 ELOG: base=0x003f0000 base_ptr=0xffbf0000 ELOG: MEM @0x00190ad8 FLASH @0xffbf0000 ELOG: areas are 4096 bytes, full threshold 3072, shrink size 1024 Change-Id: I3d826812c0f259d61f41b42797c58dd179f9f1c8 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1706 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-07ELOG: Don't disable SPI controller lockdownDuncan Laurie
Now that WREN prefix is handled properly ELOG is able to write when the SPI controller is locked down. To test, ensure that runtime SPI write via ELOG is successful by checking the event log for a kernel shutdown reason code: 5 | 2012-08-27 11:09:48 | Kernel Event | Clean Shutdown 6 | 2012-08-27 11:09:50 | System boot | 26 7 | 2012-08-27 11:09:50 | System Reset Change-Id: If6d0dced7cb0f5ca7038b3d758f31b856826d30b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1712 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-11-07SPI: opmenu special case for WREN as atomic prefixDuncan Laurie
The code that attempts to use the opmenu needs to have a special case for write enable now that it is handled as an atomic prefix and not as a standalone opcode. To test, ensure that runtime SPI write via ELOG is successful by checking the event log for a kernel shutdown reason code: 5 | 2012-08-27 11:09:48 | Kernel Event | Clean Shutdown 6 | 2012-08-27 11:09:50 | System boot | 26 7 | 2012-08-27 11:09:50 | System Reset Change-Id: I527638ef3e2a5ab100192c5be6e6b3b40916295a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1710 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-11-07RTC: Write build date in BCD when clearing RTC CMOSDuncan Laurie
Check the RTC on boot after RTC battery failure and ensure that the reported build date matches what is reported: > grep ^rtc /proc/driver/rtc rtc_time : 01:00:21 rtc_date : 2012-08-16 Change-Id: If23f436796754c68ae6244ef7633ff4fa0a93603 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1709 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-11-07SMI: Change order of SMI_EN and PM1_EN initDuncan Laurie
This appears to fix an infrequent resume hang on Ivybridge. Tested on 2 devices with 15k suspend/resume cycles each Change-Id: I53618bc7966824413f1720a2be3cbd2550e29473 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1704 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-11-07EC: Prepare to read and log last post code from previous bootDuncan Laurie
(elog portion, support in EC code pending) - Use a new EC command to read the last post code from the previous boot - If the post code is not well-known final boot or resume code then log it Change-Id: Id6249e9a182243eb87c777edd56f48de72125e77 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1703 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-11-07SandyBridge/IvyBridge: Use flash map to find MRC cacheStefan Reinauer
Until now, the MRC cache position and size was hard coded in Kconfig. However, on ChromeOS devices, it should be determined by reading the FMAP. This patch provides a minimalistic FMAP parser (libflashmap was too complex and OS centered) to allow reading the in-ROM flash map and look for sections. This will also be needed on some partner devices where coreboot will have to find the VPD in order to set up the device's mac address correctly. The MRC cache implementation demonstrates how to use the FMAP parser. Change-Id: I34964b72587443a6ca4f27407d778af8728565f8 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1701 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-11-07Add missing newline in error messageStefan Reinauer
This is purely cosmetic. All error messages in the Sandybridge raminit code printed a newline at the end. Change-Id: I880d291928291d487039850a2a3d53a1101124ba Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1699 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-11-07rtc: add explicit dependency on build.hVincent Palatin
build.h is generated at build time, with highly parallel builds, we might try to compile the rtc driver too early. Change-Id: I9a2681484d58b67ed3061669fbdf52ac5ad14dab Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: http://review.coreboot.org/1698 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-11-07rtc: erase CMOS memory after power failureVincent Palatin
When a power failure happens on the RTC rail, the CMOS memory (including the RTC registers) is filled with garbage. So, we erase the full first bank (112 bytes) and we reset the RTC date to the build date. To test, disconnect the CMOS battery to produce an RTC power failure, then boot the machine and observe the RTC date is the build date using "cat /sys/class/rtc/rtc0/date" Change-Id: I684bb3ad5079f96825555d4ed84dc0f7914e9884 Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: http://review.coreboot.org/1697 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-11-07AMD G34 CPU: change lapic_id in northbridge.c to accommodate G34 CPUSiyuan Wang
Each G34 socket has two node. Previous lapic algorithm is written for the CPU which has one node per socket. I test the code on h8qgi with 4 family 15 CPUs(8 cores per CPU). The topology is: socket 0 --> Node 0, Node 1 socket 2 --> Node 2, Node 3 socket 1 --> Node 4, Node 5 socket 3 --> Node 6, Node 7 Each node has 4 cores. I change the code according to this topology. Change-Id: I45f242e0dfc61bd9b18afc952d7a0ad6a0fc3855 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/1659 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-07CMOS: Move MRC seed offset into upper bankDuncan Laurie
This will allow the lower bank to be cleared without impacting the ability to suspend/resume. Change-Id: Iaec3c9e7e40c334053c814eaddd1f614df245a73 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1696 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-11-07rtc: force mc146818 register D to a correct valueVincent Palatin
On Panther Point PCH (and maybe cougar point), when some of the register D reserved bits are set, the RTC starts misbehaving (e.g. incrementing the year byte every second). There are probably undocumented features implemented behind those bits. Let's reset register D to a known state to ensure we get the expected RTC behavior. Change-Id: I7e2c2a2c6130a974bccb3d760b41eaa579a58b67 Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: http://review.coreboot.org/1695 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-11-07Fix CONFIG_ use in i8254.cStefan Reinauer
We always define CONFIG_ variables, even if they're not set. Hence, remove the check whether CONFIG_UDELAY_TIMER2 is defined Change-Id: Iefdf2389941f2cc63ae4f13ac6b213da4c96b201 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1694 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-11-07Add POST code for "All devices initialized"Stefan Reinauer
Right now we only had a post code for "All devices enabled" which was emitted at the wrong time (after the device initialize stage rather than the device enable stage) Change-Id: Iee82bff020de844c7095703f8d6521953003032c Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1693 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-11-07Move global variable check to MakefileStefan Reinauer
Our linker script for romstage checks for global variables and makes the build fail if there are any (on non-AMD systems). This is great, but having the build fail without any indication which variables are global is not very useful. Moving the check to the Makefile allows us to let the linking stage succeed and reveil which variable names end up in the data and bss sections of the binary. To test, add "int foo;" as the first line in src/mainboard/samsung/lumpy/romstage.c and build coreboot for Lumpy. See the build break the following way: LINK cbfs/fallback/romstage_null.debug Forbidden global variables in romstage: 00006a84 B foo Change-Id: I3c8780888f46a6577ffd36bcea317997b4f84f6f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1692 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-07Leave power control registers unlockedSameer Nanda
To allow easy experimentation with thermals, leave power control registers unlocked. Change-Id: Ia53065f3f220c2faed58e7d53e60c3f169ae58ec Signed-off-by: Sameer Nanda <snanda@chromium.org> Reviewed-on: http://review.coreboot.org/1688 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-07Fix whitespace issue with help message in Kconfig fileDave Frodin
Every line of text after a 'help' label in a Kconfig file must have the same whitespace preceding it, otherwise it's no longer considered help text. Change-Id: I97093bee72b295b315d78d4c26d7186bf1017fda Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/1687 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-11-07AMD rd890 late.c: Don't enable PCIe ports after PCIe init.Siyuan Wang
PCIE devices are detected and initialized by the AMD PCIe init functions, which is in cimx rd890. The parameters are read from devicetree.cb before PCIe init. Now, all bridges and devices are trained on the device 0.0 enable. After PCIe init, the PCIe ports with devices are on and the PCIe ports without devices are off. so resources may be allocated correctly during the rest of the PCI scan. But if the devicetree was being used to enable/disable devices after initialization, the problems would arise. Take a look at the serial log: do_pci_scan_bridge for PCI: 00:02.0 PCI: pci_scan_bus for bus 01 PCI: pci_scan_bus returning with max=001 do_pci_scan_bridge returns max 1 do_pci_scan_bridge for PCI: 00:03.0 PCI: pci_scan_bus for bus 02 PCI: pci_scan_bus returning with max=002 do_pci_scan_bridge returns max 2 do_pci_scan_bridge for PCI: 00:04.0 PCI: pci_scan_bus for bus 03 PCI: pci_scan_bus returning with max=003 do_pci_scan_bridge returns max 3 PCI bridge 02.0, 03.0 and 04.0 are not inserted devices, but these bridges are still scanned. This is not correct. Change-Id: I87dac5f062c6926081970ed0c5f26a7e3f447395 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/1640 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-07AMD agesa family15: PCI domain should scan bus from 0x18.0Siyuan Wang
There are four mainboards using agesa family15 code: Supermicro h8scm and h8qgi, Tyan s8226 and AMD dinar. All of these boards' PCI domain starts from 0x18.0. Take h8scm as an example, PCI devices from 0.0 to 0x14.5 is under 0x18.0. Now, the PCI domain's scan bus function stats from 0.0. This would result to the PCI devices be scanned twice. Because when the function run to device 18.0, it would scan from 0.0 again. This issue would result to 2 problems: 1) PCI device may be assigned two different PCI address. If this happenned on VGA device, coreboot maybe not load vga bios correctly. 2) coreboot initializes rd890's IO APIC twice. So this patch scans from 0x18.0 and could resolve the problems above. Change-Id: I90fbdf695413fd24c7a5e3e9b426dc7ca6e128b1 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/1639 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-06acpi: Add support for DMAR tables (Intel IOMMU support)Patrick Georgi
Adds lowlevel handling of DMAR tables for use by mainboards' ACPI code. Not much automagic (yet). Change-Id: Ia86e950dfcc5b9994202ec0e2f6d9a2912c74ad8 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1654 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-06Drop redundant CHIP_NAME in mainboard.cKyösti Mälkki
Compose the name from Kconfig strings instead. As the field is for debug print use only, a minor change in the output should do no harm. The strings no longer include word "Mainboard". Change-Id: Ifd24f408271eb5a5d1a08a317512ef00cb537ee2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1635 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-06smsc/lpc47n227: Make early_serial usablePatrick Georgi
This is the smallest possible change to make early_serial.c compile when included from romstage.c. early_serial could be reworked to be built as separate unit (romstage-y), but that should be done for all SuperIOs, not some individual outlier. Change-Id: I90ee66b43c9677b86b1b5d6fcc8febfbe58d80dd Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1686 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-06cpu/intel/model_1067x: Add proper c-state/p-state/thermal supportNico Huber
Change-Id: I853454e8f5617fb7af5dddd7288bdeeacc7b1b8e Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1663 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-06intel/socket_BGA956: enable speedstep, CAR, MMX, SSEPatrick Georgi
All of these capabilities exist on all CPUs supported on this socket. Change-Id: I54f34e48e34bb6ab5b9954ab7ece8c2c3a1a8e67 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1664 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-06Add name field for deviceKyösti Mälkki
The constant field "name" in chip_operations is common to multiple different devices within a chip and cannot reflect the actual device as found on the platform. The intention is that a driver sets dev->name as part of the device enumeration sequence with the detected hardware type and revision. The field is for debug print use only. Change-Id: Ib7bf90ba3c618ad0cb715d80d6a937ceaae0adcf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1634 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-05Overhaul speedstep codeNico Huber
This adds proper support for turbo and super-low-frequency modes. Calculation of the p-states has been rewritten and moved into an extra file speedstep.c so it can be used for non-acpi stuff like EMTTM table generation. It has been tested with a Core2Duo T9400 (Penryn) and a Core Duo T2300 (Yonah) processor. Change-Id: I5f7104fc921ba67d85794254f11d486b6688ecec Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1658 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-05Fix some indentation flaws and break very long linesNico Huber
Change-Id: I3efef6bc8f519382ffdd92eb10b4bcd1a4361ba9 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1657 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-02remove enable_cache() of 3 mainboardsSiyuan Wang
Because enable cache is added at the end of disable_cache_as_ram, ( http://review.coreboot.org/#/c/1662/2/src/cpu/amd/agesa/cache_as_ram.inc ) enable_cache() should be removed. The 3 mainboards are: amd parmer, amd thatcher and tyan s8226 Change-Id: If870ca07d2e97b9e860a2e2315f551251c7a4ed2 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/1669 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2012-11-02Persimmon: disable the unconnected Full-Speed USB portDave Frodin
Change-Id: Ia3824059a38412896ed2be0c8714018b2291c9f8 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/1660 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-02AMD agesa: add enable cache at the end of disable_cache_as_ramSiyuan Wang
add this code according to src/include/cpu/x86/cache.h ,line 92, functin enable_cache() Change-Id: Ida96a98397eeed98dd61ca979e8c5a33bf00f9e5 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/1662 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-02Correct FSB reading in speedstep ACPINico Huber
We parsed the MSR the wrong way, and didn't support some valid values. Change-Id: Ia42e3de05dd76b6830aaa310ec82031d36def3a0 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1656 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-02Fix some issues with new "reference" toolchainStefan Reinauer
Unfortunately the reference tool chain was updated without ever even testing it on an abuild run. This broke a number of ports. This change gets coreboot at least compiling again for all supported systems. Change-Id: I92c7cbc834de6d792fdab86b75df339e2874c52e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1670 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-11-01Merge cpu/intel/acpi.h into cpu/intel/speedstep.hNico Huber
We had only some MSR definitions in there, which are used in speedstep related code. I think speedstep.h is the better and less confusing place for these. Change-Id: I1eddea72c1e2d3b2f651468b08b3c6f88b713149 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1655 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-10-30Add support for socket LGA775Stefan Tauner
Change-Id: Ia7ef3a4cbc3638a9c9a48b297e392e4e655b6e6b Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: http://review.coreboot.org/1581 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 21:37:19 +0000