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2017-08-10SMBIOS: Correct length calculation for empty string tableKonstantin Aladyshev
If all strings in SMBIOS table are empty, smbios_string_table_len function should return 2, cause every table must end with "\0\0". Also replace "eos" field type in smbios structures from char to u8. Change-Id: Ia3178b0030aa71e1ff11a3fd3d102942f0027eb1 Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com> Reviewed-on: https://review.coreboot.org/20840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-08-10nb/amd_fam10/mct_ddr3: Use common function to compute crc16 checksumArthur Heymans
Change-Id: I730a8a150134cc1ef8fb3872728bb0586ac7b210 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19732 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2017-08-10google/kahlee: Set eMMC slotMarc Jones
Set AGESA SD/eMMc variable to non-removable eMMc. BUG=b:63891719 BRANCH=none TEST=Boot eMMC on Kahlee. Change-Id: I76ed9cec36a9688ebe75db2077f1ece4ab750c16 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20911 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-09intel/common/block/smm: Update smihandler to handle gpiBrandon Breitenstein
Updating the common smihandler to handler gpi events which originally were going to be left to each soc to handle. After some more analysis the gpi handler can also be commonized. Change-Id: I6273fe846587137938bbcffa3a92736b91982574 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/20917 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-09drivers/i2c: Add driver for rt5663 codecDuncan Laurie
This commit adds a new driver for the RT5663 codec to use instead of the generic i2c driver. Since the kernel needs additional driver-specific device properties we need a BIOS driver that can provide those properties. The kernel driver devicetree properties for this codec are at: linux/Documentation/devicetree/bindings/sound/rt5663.txt This was tested by booting and verifying the generated SSDT contains the expected device properties in _DSD. Scope (\_SB.PCI0.I2C4) { Device (RT53) { Name (_HID, "10EC5663") Name (_UID, Zero) Name (_DDN, "Realtek RT5663 Codec") Method (_STA, 0, NotSerialized) { Return (0x0F) } Name (_CRS, ResourceTemplate () { I2cSerialBus (0x0013, ControllerInitiated, 0x00061A80, AddressingMode7Bit, "\\_SB.PCI0.I2C4", 0x00, ResourceConsumer) GpioInt (Edge, ActiveBoth, Exclusive, PullDefault, 0x0000, "\\_SB.PCI0.GPIO", 0x00, ResourceConsumer) { 0x0051 } }) Name (_DSD, Package (0x02) { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") Package (0x05) { Package (0x02) { "irq-gpios", Package (0x04) { \_SB.PCI0.I2C4.RT53, Zero, Zero, Zero } }, Package (0x02) { "realtek,dc_offset_l_manual", 0x00FFD160 }, Package (0x02) { "realtek,dc_offset_r_manual", 0x00FFD1C0 }, Package (0x02) { "realtek,dc_offset_l_manual_mic", 0x00FF8A10 }, Package (0x02) { "realtek,dc_offset_r_manual_mic", 0x00FF8AB0 } } }) } } Change-Id: I3425fcbe13c9a5987fc91086d283a86db55c0819 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/20904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-08-09soc/intel/common: smi handler fix comilation errorAaron Durbin
The device_t type is used in smihandler.h, but the header is not including a header which provides that type. Fix that by #includeing <device/device.h> Change-Id: I89af949b088bf569d330f2ea74b1b8ae97e1ed52 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20933 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-09soc/intel/cannonlake: Add ramstage SystemAgent supportLijian Zhao
Revere memory resource within SA, also perform necessary routine for initialization during ramstage. Change-Id: Ibaa7334b0d94fedc87e707a136c9537e2e6f57cb Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20914 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-09mb/lenovo/x1_carbon_gen1: add missing '+' in spd/MakefileAlexander Couzens
Each line of spd config overwriting the slot 0 instead of appending it. Change-Id: I0124aa34f1d4fcb30810fb7eef03d4828a7ac430 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Tested-on: lenovo x1 carbon gen 1 with elpida 8GB Fixes: e9787ff61f81 ("mb/lenovo/x1_carbon_gen1: Add 4GiB SPD index 2") Reviewed-on: https://review.coreboot.org/20918 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-08-09common/block/smm: Update SMM common code for io trap handlingBrandon Breitenstein
Add smm common code for io trap handling. This feature is mainly used by big core intel platforms. Commonizing io trap handling will make bring up of big core platforms more seamless. Change-Id: I83bcf22107291ea181b347fac40d57d7ea138de1 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/20848 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-09device/pci: untangle struct device and device_tAaron Durbin
This patch uses struct device explicitly for the ramstage functions as that's the actual type it's working on. Additionally, the declarations for types and functions are fully exposed so that compliation units don't have to guard certain functions from use because it's being compiled for multiple stages. Change-Id: I8db23ed400a59073e1e66522d020a5928f71f3a6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-08-08mb/lenovo/x1_carbon_gen1: Add 4GiB SPD index 2Nico Huber
Change-Id: I218fd48c8e29563ef089d60ebde7bc36ac8ab189 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-08-08soc/intel: Remove ACPI notification for fan speed changeSumeet Pawnikar
In _FSL ACPI notification 0x83 was incorrectly being sent to DPTF. When there should be no notification on fan speed change. Change-Id: I66efa7a7feb911a458829a54dbd0afefabd42394 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/20875 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-08add __must_check to */compiler.hCaveh Jalali
the __must_check function attribute is pretty much straight from the linux kernel - used to encourage callers to consume function return values. Change-Id: I1812d957b745d6bebe2a8d34a9c4862316aa8530 Signed-off-by: Caveh Jalali <caveh@google.com> Reviewed-on: https://review.coreboot.org/20881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-08soc/intel/apollolake: Use common PMC for apollolakeShaunak Saha
With this patch apollolake uses the common PMC util code.No regression observed on a APL platform. Change-Id: I322a25a8b608d7fe98bec626c6696e723357a9d2 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/19375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-08soc/intel/common: Use common PMC for SMMShaunak Saha
Change-Id: I067b99415e882a24970140280d3b223eb1301e2d Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/20307 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Aaron Durbin <adurbin@chromium.org>
2017-08-08soc/intel/common/block: Add Intel PMC supportShaunak Saha
PMC util code is very similar accross different intel SOC's. This patch is an effort to move those code in common place so that it can be shared accross different intel platforms instead of duplicating for each platform. This patch adds pmclib.c file which contains the pmc utility functions common accross SOC's. The config for common PMC is SOC_INTEL_COMMON_BLOCK_PMC which can be defined in SOC's Kconfig file in order to use the common PMC util code. Change-Id: Ic3d96fc23a98c30e8ea0969a7be09d217eeaa889 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/19349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-08soc/intel/skylake: Log wakes caused by PME on internal bus and PCIE RPNaresh G Solanki
Internal PME is detected when bit PME_B0_STS is set. Following devices causes internal PME. - Integrated LAN - HD Audio/Audio DSP - SATA - XHCI ('USB3') - ME Maskable Host Wake In SPT, PCIEXPWAK_STS bit isn't getting set due to known bug. So scan all PCIe RP for PME status bit & update event log accordingly. BUG=b:36992859 TEST=Build for Soraka, Verify resume due to PME on root port is logged in elog. Change-Id: I879a7c332e62ab598942b29d31bad84619b35ea7 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/20532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-08rx6110sa: Make sure that VLF bit will be clearedWerner Zeh
Ensure that the VLF bit will be cleared after a power loss event even if the stopwatch has expired before the code to clear the bit is reached. Change-Id: Ib2cfdabf4cd4df834395d6a102c6ae70568e71db Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/20893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2017-08-08mb/lenovo/l520/Kconfig: Remove hybrid graphics driver supportPatrick Rudolph
The schematics isn't available for the board, but other L*00 series boards seem to use a different, compared to T*00 series, GPIO layout. As it has never been tested, remove the broken driver. Change-Id: I4bfa02fdbc5da5b556010c2f300faaf6dc845b80 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-08mb/intel/d510mo: Configure clockgenArthur Heymans
Configuring the clockgen like vendor bios fixes the issue where the display wobbles from left to right on the analog VGA output. Note: This seems to be common issue/requirement on Intel devices from that generation (also happens on dg43gt). TESTED on Intel D510MO. Change-Id: I08449f0b8b90a1781e6dec91140bf219ea07aaf9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19595 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-08-07soc/intel/braswell: Fix SPI write after FLOCKDN is setHannah Williams
The SPI controller initialization in finalize_chipset was failing because FSP was setting FLOCKDN before finalize_chipset was called. Hence move finalize_chipset to get called from BS_POST_DEVICE so that it is called before FSP notify function-Ready To Boot state. TEST: run flashrom with -VVV and observe supported opcodes and SPI flash chip are reported correctly, and write/erase operations succeeed. Original-Change-Id: I3c0297f3f2258cf77cf00db367f11ff4d1d9dc77 Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I690fb4bf9e78bb58811c704179ba8b8f25ce95cc Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/20891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-07soc/intel/cannonlake: Add memory map supportLijian Zhao
Calculate the top of ram from output of Fsp reserved memory range. Change-Id: I0dcc8f737c5811c9010cc4a20ea0126ab3f90f14 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-07nb/intel/*/gma.c: Use macros for GMBUS numbersArthur Heymans
Change-Id: I885b6bd9f5be6b4e3696a530016123a3e81c4b10 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-08-07usbdebug: Force EHCI to D0 stateKyösti Mälkki
When resuming from ACPI S3 suspend, EHCI controller may be in D3 power-management state. Bring it to D0 early so it is functional for console. NOTE: D3hot->D0 transition was observed to reset previous programming of PCI_COMMAND register. Change-Id: Id177ce61926beb057fe67ba42a306d8e565d2657 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-08-07usbdebug: Refactor early enableKyösti Mälkki
Always sanity check for EHCI class device and move PCI function power enablement up. Change-Id: I1eebe813fbb420738af2d572178213fc660f392a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-07usbdebug: Consolidate EHCI_BAR setupKyösti Mälkki
There is assumption of static EHCI_BAR_INDEX, try to clean it up by bringing BAR programming at one spot. Change-Id: Ie16090536ac5470c24720a54813015250ae2d0dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-08-07usbdebug: Remove redundant setupKyösti Mälkki
Taking ownership is handled with DBGP_OWNER within usbdebug driver code. Change-Id: Ia5da10d385cda1b4968f812967ea8a54d7e3c974 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Guckian <david.guckian@intel.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-08-07sb/intel/i82801jx: Add romstage smbus and i2c block operationsArthur Heymans
Change-Id: I76bf1ed392d3d18059792106fc482d2259a3f084 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-08-06sb/intel/i82801gx: Implement smbus block r/w functionsArthur Heymans
Uses common hardware access functions to make smbus block read and write available in romstage. Those are needed to reconfigure the clockgen on smbus offset 0x69, which is sometimes needed for things like CPU C-states or analog display out to work properly. Change-Id: I0a06178d2474ce65972de157cb437b42f3354da0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Damien Zammit <damien@zamaudio.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-08-06sb/intel/*: Use common SMBus functionsArthur Heymans
All Intel southbridges implement the same SMBus functions. This patch replaces all these similar and mostly identical implementations with a common file. This also makes i2c block read available to all those southbridges. If the northbridge has to read a lot of SPD bytes sequentially, using this function can reduce the time being spent to read SPD five-fold. Change-Id: I93bb186e04e8c32dff04fc1abe4b5ecbc4c9c962 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-08-06sio/smsc/kbc1100: Fix some style issuesArthur Heymans
This fixes indentation and whitespaces before opening parentheses. Change-Id: I8940f712c0161419ee0c383b7bc9eb581967366e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2017-08-06rockchip: gpio: Correct rk3399 pmu gpio pull settingLin Huang
Starting with RK3399, PMUGPIO pull registers use the same write mask format as normal GRF registers, so they need to use RK_CLRSETBITS() rather than clrsetbits_le32(). BRANCH=None BUG=None TEST=boot from scarlet Change-Id: Ibe391273d58ab35df993e149187d67497fcf2acc Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/20871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-08-06rockchip: gpio: add gpio_pull argument in gpio_input_irq() functionLin Huang
some gpio irq need to set input pull initialization status to guarantee to get the right irq trigger. let's add this argument in gpio_input_irq() function BRANCH=None BUG=None TEST=boot from bob Change-Id: I9b8e6497f07146dafdb447a6ea10d039a2a2fa33 Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/20866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-08-04soc/intel/common: Add lpss.c to ramstageFurquan Shaikh
BUG=b:64030366 Change-Id: I7e05d65ebb3b6499451242521ffc61fc4c952830 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-04drivers/uart: Use baudrate of 115200 by defaultFurquan Shaikh
If TTYS0_BAUD is not configured, then by default use baudrate of 115200. BUG=b:64030366 Change-Id: Ida4c7ae77aba5dfd4ec331e22a54ce43a91bde00 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-04AGESA f15 f15tn f16kb: Add extra checks for incorrect SPD dataKonstantin Aladyshev
Make DMI data calculation fail-safe to incorrect SPD data. Change-Id: Ica92850cc77e1f7cbf3e7e44717de42a03b93bbe Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com> Reviewed-on: https://review.coreboot.org/20839 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-04mainboard/google/poppy: Decrease link-frequencies for OV13858 and OV5670V Sowmya
Decrease the link-frequencies as recommended by Omnivision for OV13858 and OV5670 camera sensors. BUG=b:38326541 BRANCH=none TEST=Build and boot soraka. Dump and verify that the generated DSDT table has the required entries. Verified that sensor probe is successful. Change-Id: I78fb2d3527f66b5147123a9c8fc4cb95650f86b6 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/20787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
2017-08-04mainboard/google/soraka: Configure GPP_B8 in bootblockFurquan Shaikh
GPP_B8 acts as input to the inverter whose output controls PERST# signal to wifi module. Out of reset, GPP_B8 is configured as input by default. Since there is no external pull-down on it, this line is floating and results in PERST# being asserted until ramstage where the GPIO was originally configured. Because of this the wifi chip is not ready during the PCIe initialization step. Move the configuration of GPP_B8 to bootblock so that wifi device is taken out of reset as early as possible. BUG=b:64181150,b:62726961 TEST=Verified with warm reboot and suspend-resume stress test that wifi is still functional. Change-Id: I68e1bd67499262a17daade72e9a9fd32934a184d Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-04mainboard/google/soraka: Add gpio.c to bootblockFurquan Shaikh
Add gpio.c to bootblock so that the variant early_gpio_table can be used for configuration in bootblock. BUG=b:64181150,b:62726961 Change-Id: I77181334257f2fd19982ecafc1f58afe912f4280 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-04southbridge/pi/hudson: Fix GPIO bank1 control definitionMarshall Dawson
Change-Id: I3ef3ea3ea22faa0152d99923da2e57517ab3d0be Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-04soc/intel/common: Add Cannonlake pci ids for commonLijian Zhao
Add Cannonlake pci device ids for all the merged intel common code. As of now only have CNL-U and CNL-Y pci ids. Change-Id: Iee5087cdeba53919d83ff665d0c417075279294c Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-08-04google/kahlee: Add ChromeOS SMBIOS Board IDMarc Jones
Kahlee uses 3 GPIO(144, 140, 135) pins to identify the board revision. Change-Id: Ia9693db6d6506af7ff40db0b3ce4cc6c1469f6ef Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-04soc/amd/stoneyridge: Use generic gpio libraryMarc Jones
Use the genric GPIO library. Add the required functions. Also, update the Kahlee mainboard dependency to match. Change-Id: I2ea562b052401efff3101f736788ca77d21e6de6 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20543 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-04lib/cbmem: provide optional cbmem top initialization hookAaron Durbin
Provide a hook to allow an optional one-time cbmem_top() initialization. The new function, cbmem_top_init(), is called on the first expected initialization of cbmem based on the Kconfig options LATE_CBMEM_INIT and EARLY_CBMEM_INIT. Change-Id: I89edd2d11f226217c8e2aaca829b4f375a2cff28 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-08-03lib/cbmem: use globals for non CAR global migration platformsAaron Durbin
For CAR platforms which don't migrate globals real globals can be directly used. This alleviates the need to peform partial recovery on every cbmem access which in turn acts like all non-CAR platforms or any stages which execute entirely out of RAM. Change-Id: I31c08dd6473324424d5d42fe6b56d42fe635929e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-08-03soc/intel/apollolake: Skip disabled IGD deviceSubrata Banik
If IGD PCI device is disabled: 1. BAR for the device will be 0. 2. There is no need to allocate framebuffer for this device. Some early SOCs don't have GFX model fuse by default hence we need to add a check to ensure PCI device is enable. This code to avoid die inside coreboot for missing resources. Change-Id: Ied677e8c77fa7b166b016da458caad0e4702b5d8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-03soc/intel/skylake: Skip disabled IGD deviceSubrata Banik
If IGD PCI device is disabled: 1. BAR for the device will be 0. 2. There is no need to allocate framebuffer for this device. Some early SOCs don't have GFX model fuse by default hence we need to add a check to ensure PCI device is enable. This code to avoid die inside coreboot for missing resources. Change-Id: Ic31d3e57ba730f6b569bf2cc3bdc54cb369b8caf Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-03soc/intel/cannonlake: Sort Kconfig for CannonlakeLijian Zhao
Look and feel update, sort the sequence in Kconfig. Change-Id: I41d99979d9c7d081086aac8bfef27186b37a6e70 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-03soc/intel/braswell/Kconfig: select RELOCATABLE_RAMSTAGEMatt DeVillier
Without RELOCATABLE_RAMSTAGE selected, S3 resume will hang under Linux and Windows. All other Intel SoCs have this selected by default, so this change simply corrects an omission on Braswell. TEST: boot Linux on google/cyan with and without RELOCATABLE_RAMSTAGE selected; observe that S3 resume fails without and succeeds with. Change-Id: I9071d9b4e3e3a156281d95fae059947c4c26f744 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/20819 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-03google/kahlee: Add Realtek audio codec ASLIvy Jian
Add the RT5650 codec ASL for proper Linux driver loading. Devices visible to OS: /sys/bus/acpi/devices/AMDI1002:00 /sys/bus/acpi/devices/I2SC1002:00 Change-Id: I60b256f68372c9d17d67c9cb2accaca616a0b9a5 Signed-off-by: Ivy Jian <ivy_jian@compal.com> Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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