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2008-01-18Please bear with me - another rename checkin. This qualifies as trivial, noStefan Reinauer
code is changed. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-13Various small fixes to make the Tyan S1846 match the format ofUwe Hermann
the other supported 440BX boards. Fix up totally b0rked static device tree in Config.lb. Drop useless and duplicated failover.c, use global one. Make CPU init actually work (result: massive speed-up). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2960 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-03Switch the Tyan S1846 to a fallback-only boot per default to allowUwe Hermann
bigger payloads (trivial). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2710 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-27Various 440BX and Tyan S1846 related minor changes and fixes (trivial):Uwe Hermann
- Only check the RAM from 0 - 640 KB and 768 KB - 1 MB now. That's available on all boards, regardless of what DIMMs you use. Tested on the Tyan S1846, works fine. - Properly set the PAM registers to allow the region from 768 KB - 1 MB to be used as normal RAM (required for the above). - Document all of this properly. Add/improve other documentation, too. - Simplify and document code in northbridge.c. - Cosmetics and coding style. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2701 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-03Correct the RAM checking code to _not_ check the range from 640 KB - 1 MB,Uwe Hermann
as that is not RAM but used for other stuff. First try at PCI init added to src/mainboard/tyan/s1846/Config.lb. Use a real payload (FILO) per default now. Note: this cannot boot a payload, yet, but it gets a lot further now. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2623 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-25Revert the image size increasing for abuild. It breaks more boards thanUwe Hermann
it fixes. It seems many of the other boards run out of space for the payload. Thus, this patch only increases the image size for the three boards - tyan/s2912 - nvidia/l1_2pvv - gigabyte/m57sli by adding a custom Config-abuild.lb file for each of them. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2618 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-03Add initial framework for the Tyan S1846.Uwe Hermann
It's not fully working, among other things because the Intel 440BX northbridge isn't working, yet. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2580 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-27This is another fixup round for Yinghai Lu's great patch.Stefan Reinauer
It does the ROM_STREAM -> PAYLOAD rename that afaik was done after Yinghai sent his work to legal, so it is required to get that code building. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2561 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-17Initial support for the following new mainboards:Yinghai Lu
* Nvidia l1_2pvv * Gigabyte m57sli * Supermicro h8dmr * Tyan s2912 -- with HTX The boards will currently _not_ compile, two further patches from Yinghai Lu are still missing. Please be patient :) Signed-off-by: Yinghai Lu <yinghai.lu@amd.com> Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2554 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-04get_bus_cong using sysconf insteadYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2442 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-06Uwe Hermann:Stefan Reinauer
Here's a patch which makes all "option ROM_SIZE" lines use x*y format which is a lot easier to read and modify, without having to use your brain or a calculator ;-) Tested with abuild, no errors. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2398 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-03new cache_as_ram support Yinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-01-27adding preliminary, and almost certainly wrong, rumba support. Ronald G. Minnich
This is just a skeleton, basically, and will most likely not even compile yet. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2164 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-12-021201_ht_bus0_dev0_fidvid_mb.diff - part 3Stefan Reinauer
issue 41 - fix up motherboard compilation target configuration files. Who wants to do some major cleanup here some time? The fixed/relative paths in payloads are nasty. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2122 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-08eric patchYinghai Lu
1. x86_setup_mtrr take address bit. 2. generic ht, pcix, pcie beidge... 3. scan bus and reset_bus 4. ht read ctrl to decide if the ht chain is ready 5. Intel e7520 and e7525 support 6. new ich5r support 7. intel sb 6300 support. yhlu patch 1. split x86_setup_mtrrs to fixed and var 2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource 3. in_conherent.c K8_SCAN_PCI_BUS git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-51arch import user (historical)
Creator: Yinghai Lu <yhlu@tyan.com> cache_as_ram for AMD and some intel git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-34arch import user (historical)
Creator: Yinghai Lu <yhlu@tyan.com> AMD D0/E0 Opteron new mem mapping support, AMD E Opteron mem hole support,AMD K8 Four Ranks DIMM support git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1950 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-30arch import user (historical)
Creator: Yinghai Lu <yhlu@tyan.com> Nvidia Ck804 support git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1946 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-02-09VERSION and rom_image_sizeYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1914 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-13onboard pci romYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1859 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-12-16btext fixYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1822 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-02Tyan update for ROM_IMAGE_SIZE > 64KYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1730 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-22s2735 half updateYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1705 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-20Tyan update to work with new CPU ConfigYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1693 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-07-01Intel E7501 P64H2 ICH5R supportYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1616 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-05-13add comment and new config fileRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1558 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-04-28Changes for btext and etherboot and filo merge supportYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1540 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-04-24commit Yinghai's patches to targets/ (from: fb2_tyan_0420.change.diff)fb2_tyan_0420.change.diff)
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1527 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-25add target configuration files for Tyan s4882, update tyan s2880 and s2885Stefan Reinauer
config. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1475 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-12fixes for tyanRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1392 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-12-02newRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1303 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-12-02from Yh LuRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1302 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-15for tyan. recover from Eric B's error additions to via code :-)Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1220 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-01vga supportRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1169 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-25new from tyanRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1135 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-17add filename to buildrom commandStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1116 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-01- Updates to config.g so that it works more reliably and has initial supportEric Biederman
for paths - Renamed some configuration variables SMP -> CONFIG_SMP MAX_CPUS -> CONFIG_MAX_CPUS MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS - Removed some dead configuration variables MAX_CPUS -> CONFIG_MAX_CPUS MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS SMP -> CONFIG_SMP FINAL_MAINBOARD_FIXUP SIO_BASE SIO_SYSTEM_CLK_INPUT NO_KEYBOARD USE_NORMAL_IMAGE SERIAL_CONSOLE USE_ELF_BOOT ENABLE_FIXED_AND_VARIABLE_MTRRS START_CPU_SEG DISABLE_WATCHDOG ENABLE_IOMMU AMD8111_DEV - Removed some assembly files that are no longer needed killed src/southbridge/amd/amd8111/smbus.inc killed src/southbrideg/amd/amd8111/cmos_boot_failover.inc killed src/ram/ramtest.inc - Updates to config.g so that it works more reliably and has initial support for paths - Renamed some configuration variables SMP -> CONFIG_SMP MAX_CPUS -> CONFIG_MAX_CPUS MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS - Removed some dead configuration variables MAX_CPUS -> CONFIG_MAX_CPUS MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS SMP -> CONFIG_SMP FINAL_MAINBOARD_FIXUP SIO_BASE SIO_SYSTEM_CLK_INPUT NO_KEYBOARD USE_NORMAL_IMAGE SERIAL_CONSOLE USE_ELF_BOOT ENABLE_FIXED_AND_VARIABLE_MTRRS START_CPU_SEG DISABLE_WATCHDOG ENABLE_IOMMU AMD8111_DEV - Removed some assembly files that are no longer needed killed src/southbridge/amd/amd8111/smbus.inc killed src/southbrideg/amd/amd8111/cmos_boot_failover.inc killed src/ram/ramtest.inc killed src/sdram/generic_dump_spd.inc killed src/sdram/generic_dump_spd.inc - Updated the arima/hdama to build with the new configuration system - Updated config.g to list all of the variables with make echo git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-08-29more targetsRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1092 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-08-29new targetsRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1091 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-08-27support for new mobos and fixesRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1087 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-08-04patches from Yh Lu. Tested and working on HDAMARonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1068 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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