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2006-09-24clean up epia targetsStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2433 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-20Lots of lx fixes. CLeanup mainly. THings now buildRonald G. Minnich
Signed-off-by: Ronald G. Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2430 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-19add targetRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2427 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-19resize OLPC flashRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2424 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-19Fix the name for buildrom scriptRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2423 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-19add an OLPC target for qemuRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2422 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-15run preprocessor on hand-crafted config files in abuild, tooStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2418 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-14additions and mods for lzma. Carl-Daniel Hailfinger
Signed-off-by: Carl-Daniel Hailfinger Signed-off-by: Ronald G. Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2413 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-13changes for the lx and artecgroup moboIndrek Kruusa
Signed-off-by: Indrek Kruusa Approved-by: Ronald G. Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2412 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-13Fix the irq_tables ronald g. minnich
signed-off-by: ronald g. minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2403 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-13mods for qemu, these buildronald g. minnich
signed-off-by: ronald g. minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2402 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-06Uwe Hermann:Stefan Reinauer
Here's a patch which makes all "option ROM_SIZE" lines use x*y format which is a lot easier to read and modify, without having to use your brain or a calculator ;-) Tested with abuild, no errors. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2398 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-18delete unused device. Ronald G. Minnich
set rom to 512k git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-11- revert Config.1M.lb back to PLCC size and add new SPI config fileRichard Smith
SPI config file is 1M-128k to allow for EC code git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2374 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-11build 1024-128k binary as per requests.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2372 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-09mods for the ultra40 bringup. This now builds.Ronald G. Minnich
amd gx2 north -- don't set anything in the north, it conflicts with vsa settings. So we have our own pci_set_resources that is essentially a no-op -- just calls the kids. olpc rev_a config -- DISABLE the compressed rom stream. This SHOULD NOT have been set -- it is untested and caused real trouble. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2369 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-07initial work on sunw ultra40. It's wrong :-)Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2366 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-03Changelog:Indrek Kruusa
* src/cpu/amd/model_lx/model_lx_init.c L2 cache initialization removed (moved to northbridge.c) * src/include/cpu/amd/lxdef.h more checked values * src/northbridge/amd/lx/northbridge.c L2 cache initialization added cpubug() commented out * src/northbridge/amd/lx/raminit.c empty function sdram_set_registers() is in use, don't remove * src/mainboard/artecgroup/dbe61/Config.lb irqmap changes * src/mainboard/artecgroup/dbe61/irq_tables.c tentative changes to irq table (currently not in use) * src/mainboard/artecgroup/dbe61/mainboard.c irq assigned manually to NIC * src/mainboard/artecgroup/dbe61/Options.lb gcc 4.0 is OK * targets/artecgroup/dbe61/Config.lb 64K for VSA is OK at moment Signed-off-by: Indrek Kruusa <indrek.kruusa@artecdesign.ee> Signed-off-by: Andrei Birjukov <andrei.birjukov@artecdesign.ee> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2360 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-03slightly changed C.D. Hailfinger's precompressed rom stream patchStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2359 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-07-29- Add support _framework_ for the Asus p2b. Richard Smith
- New superIO winbond/w83977tf - Add single memory controller SBbus debug routine into a file private to the i440bx This adds support the start of support for an Asus p2b mainboard. Current limitations are the same as for the Bitworks IMS board. Reads from the SMbus don't work. Moving dump_spd_registers() into its own private copy solves the problem of having to go hack on the version that included in src/sdram to only do one memory controller. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2351 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-07-28This patch adds support for the AMD LX cpu. Ron Minnich
There is one global change to pci_ids.h. The rest are changes for LX. I ran abuild and it is ok. Not all artec design changes are included as some of them would adversely affect other mainboards. Indrek will need to test. Signed-off-by: Ron Minnich Signed-off-by: Indrek Kruusa, indrek.kruusa@artecdesign.ee, artec design. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2350 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-07-24add framework for i440bx chipsetRichard Smith
add support for NSC pc87351 SuperIO add Bitworks/IMS manboard config This is a very basic framework for the i440bx chipset and the Bitworks IMS board that uses it. Most things are structure only. Known issues: - SMbus reads to the RAM SPD come back all zero. - dump_spd_registers() is commented out since it breaks with the default setting of generic_dump_spd.c where it wants 2 memory controllers. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2347 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-06-11add a 1M target for big romsRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2317 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-06-10changes from AMD for making OLPC video work.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2316 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-06-08further development of OLPC. Set vsm size to 35k. add PCI IRQ for USB. Ronald G. Minnich
Set linuxbios size to 28k. Drop debug level to 8. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2315 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-25add DK8HTX support. Ronald G. Minnich
VSAs now required to be nrv2 compressed git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2312 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-18cleanup some of the compressed rom stream ugliness -- more to do!Ronald G. Minnich
olpc and rumba can now boot linux out of flash. vsa was resized to 64K. olpc and rumba now used compressed payload -- thanks stefan! git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2307 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-09Fix an error in the config files.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2302 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-06For a kernel-only OLPC.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2300 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-04mods for early printing on OLPCRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2297 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-02Fall back to pre-broken settings and setup for GX2. Ronald G. Minnich
We lost a few things, but this is still worth it. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2287 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-27we don't need msr_initRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2281 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-25no fallback versionRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2279 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-18added the olpc target and supportRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2255 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-03new cache_as_ram support Yinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-01- Adds support for the Advantech eval board. Configuration was producedRichard Smith
on a SOM-DB2301 baseboard with a SOM-2354 cpu module. - Also does a slight tweak to the ram test code to make it more obvious when it fails. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2231 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-03-21add vsm supportRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2223 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-03-19small cleanup attempt in sc520 code. there needs to be some major springStefan Reinauer
cleaning git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2214 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-03-18small ts5300 update, fix endian problem in dummmcr.Stefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2213 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-03-01a few new items and mods for ollieRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2189 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-02-16serverworks HT1000/HT2000, bcm5785/5780 supportYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2176 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-02-11fix mistake in nameRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2173 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-02-11lippert frontrunnerRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2172 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-01-28This is the change so that we can readable ldscript.ldRonald G. Minnich
amd/rumba now builds. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2169 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-01-27adding preliminary, and almost certainly wrong, rumba support. Ronald G. Minnich
This is just a skeleton, basically, and will most likely not even compile yet. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2164 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-01-19add a tinylinux config fileRonald G. Minnich
Make the error in buildrom a lot more informative -- how big are the things that did not fit? it now tells you. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2162 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-01-17First, a FATAL error, that blows up your BIOS, should NEVER FAIL to Ronald G. Minnich
provide more information. The printk_debug in that failure case is now a printk_error. The msm stuff is for debugging. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2159 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-12-04get ts5300 compiling, it's mostly a copy of msm586segStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2130 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-12-03small update, one comment adjusted, fix epia-m abuild.Stefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2124 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-12-021201_ht_bus0_dev0_fidvid_mb.diff - part 3Stefan Reinauer
issue 41 - fix up motherboard compilation target configuration files. Who wants to do some major cleanup here some time? The fixed/relative paths in payloads are nasty. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2122 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-04 23:25:15 +0000