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2009-10-22The LAN chip-set on the Technexion TIM-5690 is enabled by hardware andLibra Li
does not need any handling in software. Signed-off-by: Libra Li <libra.li@technexion.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4822 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-21Add CONFIG_VGA_ROM_RUN to HP e-Vectra P2706T to make VGA init work.Uwe Hermann
Also add pci_rom entries (commented) to targets/hp/e_vectra_p2706t/Config.lb for the same reason. They have to be uncommented to be used. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4821 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-20Add initial support for the HP e-Vectra P2706T.Uwe Hermann
Boot-tested by Paweł Stawicki <stawel@gmail.com>. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Paweł Stawicki <stawel@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4820 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16Add CONFIG_VGA_ROM_RUN to dbm690t and pistachio, otherwise theZheng Bao
VGA ROM can not run. After make, run > ./cbfs/cbfstool ./coreboot.rom add ../vga_bios.rom pci1002,791f.rom optionrom to make the final image with vga bios. The macro vga_rom_address is out-of-date when CBFS starts play its role. it also should be eliminated from rs690/chip.h as below. But it will cause building error on other board, which I cant make test on. ## Index: src/southbridge/amd/rs690/chip.h ## =================================================================== ## --- src/southbridge/amd/rs690/chip.h (revision 4782) ## +++ src/southbridge/amd/rs690/chip.h (working copy) ## @@ -23,7 +23,6 @@ ## /* Member variables are defined in Config.lb. */ ## struct southbridge_amd_rs690_config ## { ## - u32 vga_rom_address; /* The location that the VGA rom has been appened. */ ## u8 gpp_configuration; /* The configuration of General Purpose Port, A/B/C/D/E. */ ## u8 port_enable; /* Which port is enabled? GFX(2,3), GPP(4,5,6,7) */ ## u8 gfx_dev2_dev3; /* for GFX Core initialization REFCLK_SEL */ ## Don't apply above patch about rs690/chip.h before every board has been fixed. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4783 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-14Add forgotten target files for technexion/tim5690.Libra Li
Signed-off-by: Libra Li <libra.li@technexion.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4774 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-13Add support for the MSI MS-6156 board.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4767 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-13Fix kontron/kt690 build.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4766 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-13This patch adds (initial) support for the Kontron KT690 mainboard. Stefan Reinauer
It's an embedded AMD 690/SB600 mainboard with a Mobile Sempron CPU. Issues with this port: - hangs early during "Starting Windows" with Windows 7, after loading all the drivers - sound is untested and probably not working - powernow seems to be not working Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4764 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-08Simplify targets/amd/serengeti_cheetah/Config.lb. There were too manyMyles Watson
variables being set incorrectly. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4747 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07Major CONFIG_IRQ_TABLE_COUNT fixing and cleanups. Some of these boardsUwe Hermann
and PIRQ tables were actually wrong, I cannot imagine they ever worked properly. - Use CONFIG_IRQ_TABLE_COUNT in all irq_tables.c files instead of hard-coded numbers. - Make all CONFIG_IRQ_TABLE_COUNT values in irq_tables.c match Options.lb. - Make all CONFIG_IRQ_TABLE_COUNT values match the actual number of entries in the irq_tables.c file. - Set all CONFIG_IRQ_SLOT_COUNT values in src/.../Options.lb for those boards where they were set to 0 (in order to be overridden in the respective targets/.../Config.lb). This is mainly done to aid Patrick's scripts for kconfig conversion. - Fix a number of comments in irq_tables.c files. - Drop CONFIG_IRQ_SLOT_COUNT usage from boards that don't have irq_tables.c: - tyan/s1846 - asus/a8v-e_se - asus/m2v-mx_se Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4739 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-04This does away with CONFIG_ROM_PAYLOAD_START and CONFIG_PAYLOAD_SIZE.Patrick Georgi
Both were only really used in pre-cbfs, as the payload's size isn't relevant for the build process anymore. Various calculations in {no,}failovercalculation.lb are adapted accordingly. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-03Remove:Patrick Georgi
- CONFIG_CBFS - anything that's conditional on CONFIG_CBFS == 0 - files that were only included for CONFIG_CBFS == 0 In particular: - elfboot - stream boot code - mini-filo and filesystems (depends on stream boot code) After this commit, there is no way to build an image that is not using CBFS anymore. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4712 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-02Remove the Embedded Planet board.Ronald G. Minnich
Signed-off-by: Ronald G. Minnich <rminich@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4710 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-02Remove left-over targets/motorola/*, fix Dell PowerEdge 1850 name.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4709 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-02Drop remainders of the removed Totalimpact board. Fix typos.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4707 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-30Add supermicro h8dmr fam10 target. This is largely a mashup of the tyan s2912Ward Vandewege
fam10 and h8dmr k8 targets. Many, many thanks to Marc, Myles, Patrick and Stepan for all their help with this, and to Arne for doing the s2912 fam10 port. Build and boot tested. Abuild tested. There are a number of outstanding issues and caveats - see src/mainboard/supermicro/h8dmr_fam10/README. Signed-off-by: Ward Vandewege <ward@gnu.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4693 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-22failoverR.diff: Revert my failover change since Kconfig only supports fallback.Myles Watson
kconfig_s2892.dif: Add support for Tyan s2891, s2892, and s2895 to Kconfig. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4656 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-15This is an otherwise dead platform. I'm just committing the basics that Ronald G. Minnich
let it build. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4636 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-28This patch adds VGA and PS/2 Keyboard/mouse support to the already existing ↵Arnaud Maye
intel truxton (ep80579) dev board. This patch tries to improve the pcie portA configuration. The Matrox G550e PCIe gfx card shipped along with the dev board is supported. Signed-off-by: Arnaud Maye <arnaud.maye@4dsp.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4615 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-28Fix broken compilation. As CBFS is now enabled by default,Arnaud Maye
CONFIG_FALLBACK_SIZE should be equal to CONFIG_ROM_IMAGE_SIZE and not CONFIG_ROM_SIZE Signed-off-by: Arnaud Maye <arnaud.maye@4dsp.com> Acked-by: Cristi Magherusan <cristi.magherusan@net.utcluj.ro> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4605 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-27Change some more image names to "fallback" (not "image").Uwe Hermann
Also, if there's only one image, it should be named "fallback", not "normal". Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4600 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-27Rename "image" image to "fallback", so CBFS can find it.Patrick Georgi
Thanks to Carl-Daniel for finding this. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4592 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-27amd/pistachio: fallback image must be called fallback.Carl-Daniel Hailfinger
Thanks to Stefan for providing the original fix for amd/dbm690t Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4590 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-27fallback image must be called fallback.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4589 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-19Config-abuild.lb doesn't need to override ROM_IMAGE_SIZE.Patrick Georgi
Trivial change Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4555 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-12Kconfig!Patrick Georgi
Works on Kontron, qemu, and serengeti. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> tested on abuild only. Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-11Enable CBFS everywhere. All boards compiled for me (abuild tested),Patrick Georgi
and we will fix issues as they appear. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-07Add pci_rawops.h from the mailing list and fix the via/epia-m700 build.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4406 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-05Add support for the Mitac 6513WU mainboard, a Compaq OEM board using theMichael Gold
i810 chipset. Not all hardware has been tested, but my test PC boots Linux (via FILO) without any problems. Also: Add support for the SMSC LPC47U33X to the generic 'smscsuperio' driver. Signed-off-by: Michael Gold <mgold@ncf.ca> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4401 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-05Enable onboard VGA on the MS-6178 (i810 chipset) board (trivial).Uwe Hermann
Tested on hardware with the patch from r4398 and works fine as soon as Linux boots (no VGA in FILO for some reason, will investigate). In order to make the 'i810.vga' VGA blob from the vendor BIOS work you have to make the check for PCI device ID mismatches non-fatal (for now) in the src/devices/pci_rom.c file like this: Index: src/devices/pci_rom.c =================================================================== --- src/devices/pci_rom.c (Revision 4393) +++ src/devices/pci_rom.c (Arbeitskopie) @@ -87,7 +87,7 @@ if (dev->vendor != rom_data->vendor || dev->device != rom_data->device) { printk_err("Device or Vendor ID mismatch Vendor %04x, Device %04x\n", rom_data->vendor, rom_data->device); - return NULL; + // return NULL; } printk_spew("PCI ROM Image, Class Code %04x%02x, Code Type %02x\n", The reason is that the VGA blob thinks the proper VGA device ID is 0x7123 whereas it really is 0x7121 on hardware. There are multiple ways to work around this (there have been many discussions in the past), we'll see which method will be used in future... Note: This has been tested against r4393 only for now to make sure there are no problems because of the recent resource allocator changes, see http://www.coreboot.org/pipermail/coreboot/2009-July/050486.html. Tests with trunk will follow. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4399 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-02Convert Supermicro H8DMR to CBFS. Also clean up some whitespace inWard Vandewege
targets/supermicro/h8dmr/Config.lb and Config-abuild.lb. Importantly, this also sets default CONFIG_AP_CODE_IN_CAR=0 in src/mainboard/supermicro/h8dmr/Options.lb which is required to make this box boot since the changes that went in in r4315. At Myles' suggestion, this patch also sets default CONFIG_USE_FAILOVER_IMAGE=0 default CONFIG_USE_FALLBACK_IMAGE=0 default CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE in src/mainboard/supermicro/h8dmr/Options.lb to simplify targets/supermicro/h8dmr/Config.lb a bit further. Build tested with abuild, boot tested on physical hardware. Signed-off-by: Ward Vandewege <ward@gnu.org> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4393 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-01Add support for the Intel Eagle Heights development board.Thomas Jourdan
Signed-off-by: Thomas Jourdan <thomas.jourdan@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4392 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-01Fix abuild for via/epia-n. Trivial.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4390 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-01Ron,Jon Harrison
Attached is the third revision of the CN400/EPIA-N(L) patch for CB V2. Patch should work against r4381 (or later ?) This version now boots all of the way through to attempting to launch a payload (I'm trying FILO right now), where it falls over with exception 6 (invalid opcode) The coreboot_table issue seems to have been automagically resolved by the latest core files. It may still be that the reason for the payload not starting is down to some issue with the tables initialising, I'll look closer at that. Signed-off-by: Jon Harrison <bothlyn@blueyonder.co.uk> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4386 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-30the tool chain settings should not be in renamed (as they will never live inStefan Reinauer
Kconfig) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4384 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-30whoops. missed those two..Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4383 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-30This patch unifies the use of config options in v2 to all start with CONFIG_Stefan Reinauer
It's basically done with the following script and some manual fixup: VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC` for VAR in $VARS; do find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \; done Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-27Add a target/ directory for the VIA EPIA-M700 board, so we can build it.Uwe Hermann
Note that this board is nowhere near usable, further patches will follow and hopefully get this into buildable and usable shape. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4376 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-24Add support for the Soyo SY-6BA+ III board.Uwe Hermann
Tested on hardware by Andrew Morgan <ziltro@ziltro.com>, boots Linux fine. Detailed status at: http://www.coreboot.org/Soyo_SY-6BA_Plus_III Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Andrew Morgan <ziltro@ziltro.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4369 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-19Convert the MSI MS-6178 board to CBFS.Uwe Hermann
Also, enable HIGH_TABLES support for this board. The HIGH_TABLES failed with: No matching ram area found for range: [0x00000000000f0000, 0x0000000000100000) Ram areas [0x0000000000000000, 0x0000000000001000) Reserved [0x0000000000001000, 0x00000000000a0000) RAM [0x0000000000100000, 0x000000000fff0000) RAM [0x000000000fff0000, 0x0000000010000000) Reserved SELFBOOT RETURNED! Boot failed. The fix was to change northbridge.c as follows: - ram_resource(dev, idx++, 1024, tolmk - 1024); + ram_resource(dev, idx++, 768, tolmk - 768); This is build-tested and tested on hardware by me. It boots fine, for instace with SeaBIOS and the standard GRUB1 from my disk. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4365 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-16These changes implement car in qemu. The implementation is in several Ronald G. minnich
ways superior to v3, while lacking its completeness. But, one nice thing: no more included .S or .c files. It's all separate compilation. That should allow our Makefiles to work much better. Note that the current non-CAR implementation is the default and continues to work (tested FILO boot to Linux on both CAR and non-CAR). Index: src/mainboard/emulation/qemu-x86/Config.lb Change this to be sensitive to USE_DCACHE_RAM. All settings etc. that depend on this variable are grouped in one if, and the other parts (romcc etc.) are in the else. This change is a model of how we should be able to do other motherboards. Index: src/mainboard/emulation/qemu-x86/Options.lb add needed options. Index: src/mainboard/emulation/qemu-x86/failover.c remove code inclusion from this not-yet-used file. Index: src/mainboard/emulation/qemu-x86/rom.c This is the entry point for the rom-based code. Called stage1.c in v3. Index: src/lib/Config.lb change initobject to a .o from a .c; this fixed a build problem. Index: src/pc80/serial.c make uart_init non-static. Index: src/pc80/Config.lb add initobject Index: src/arch/i386/init/entry.S Entry point. Unify a bunch of files that were fiddly lttle includes. From v3. Index: src/arch/i386/init/ldscript.ld new file. The goal is to hang all init changes for CAR here, to minimize other changes to any other ldscript. Besides, putting this in init makes sense; entry and car are manage init. Index: src/arch/i386/init/car.S generic i386 car code from v3. Index: src/arch/i386/init/ldscript_fallback_cbfs.lb Fix what looks like a bug: this was not including the init.text section. Index: targets/emulation/qemu-x86/Config.lb push up the console loglevel. qemu is for debugging so we might as well get all the debugging we can. Index: targets/emulation/qemu-x86/Config-car.lb For CAR bullds. Signed-off-by: Ronald G. minnich <rminnich@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4357 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-08Add (commented) line for VGA blob adding (CBFS version) to simplify things ↵Uwe Hermann
for users a bit. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4352 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-06Change the CBFS build process to use coreboot.romPatrick Georgi
instead of coreboot.strip. That fixes the normal image because the calculations for its offset in the ROM match reality again. This requires changes in CBFS configurations to minimize the bootblock size. These are also done for CBFS boards. Other than this a couple of minor fixes are in this patch: - make asus/m2v-mx_se build with abuild with a crosscompiler - move CONFIG_CBFS for hp/dl145_g3 to Options.lb as it's done everywhere else - change the default config of abuild to not provide ROM_IMAGE_SIZE values for the images in a CBFS configuration - change abuild's crosscompile autodetection to not try to use "i386-elf-i386-elf-gcc" (which is bogus) Except for the latter two abuild changes (both in util/abuild/abuild), they're available as patch set on the mailing list in a mail from 2009-06-05 titled [PATCH]es to get normal image to work again with CBFS The changes in util/abuild/abuild are trivial and abuild tested. As discussed on the list, targets/hp/dl145_g3/Config-abuild.lb is deleted, now that Config.lb works again. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4344 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-29rename the option CONFIG_PCI_OPTION_ROM_RUN_VM86 to ↵Joseph Smith
CONFIG_PCI_OPTION_ROM_RUN_REALMODE. Signed-off-by: Joseph Smith <joe@settoplinux.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4325 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-29enable/disable IDE 0/1 (Primary/Secondary) interfaces on the i82801xx ↵Joseph Smith
southbridge. Signed-off-by: Joseph Smith <joe@settoplinux.org> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4324 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-27Move coreboot_ram and coreboot_apc to CBFS. This allows to Patrick Georgi
reduce the size of the bootblock (done for kontron/986lcd-m) Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4315 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-21Defaulting to the board's default size is the correct thing to do.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4294 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-19Trivial update of Config-lab.lb so that it works again.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4292 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-15There were a few updates lately that generates ROM size > 512K. I am ↵Vincent Lim
changing the default ROM size to 1M to accommodate this and future changes. I tested on SimNow family10h_1p.bsd and it POSTs OK. Signed-off-by: Vincent Lim <vincent.lim@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4289 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-12This is the final patch that got everything working for me with the HP dl145g3.Samuel Verstraete
I would like to remind you that this firmware enables the hardware virtualization on the AMD cpu's on the machine. That feature was explicitly disabled by the factory BIOS. Due to an error in the VGAROM no other rom loader (YABEL or X*^BIOS) than SeaBIOS manages to load the VGA rom. The VGA ROM tries to read config space of a device that is actually not present. Because SeaBIOS does not support AHCI SATA it can not start the bootable drive of the machine so i had to add filo to seabios to manage booting: ./cbfstool coreboot.rom add-payload filo.elf img/FILO Signed-off-by: Samuel Verstraete <samuel.verstraete@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4277 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1