coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2018-10-04	util/autoport: Use romstage.c instead of early_southbridge.c	Angel Pons
2018-04-16	autoport: add missing PCI IDs	Dan Elkouby
2018-01-30	autoport: Don't do writes to FD in romstage	Arthur Heymans
2018-01-20	autoport: Don't include default_irq_route.asl	Arthur Heymans
2018-01-07	autoport: Add Intel PCIe Root Port and Bridges	Jean Lucas
2017-11-01	autoport: move spi_uvscc and spi_lvscc to devicetree.cb	Iru Cai
2017-10-06	autoport: Add GPL boilerplate header to not empty .c files	Arthur Heymans
2017-10-06	autoport/bd82x6x.go: Improve gpio.c generation	Arthur Heymans
2017-07-31	util/autoport: Remove copy-pasting of PMIR register	Nico Huber
2017-05-01	mb/*/mainboard.c: Get rid of SPI AFC register	Patrick Rudolph
2016-12-07	autoport: Fix romstage generator	Kyösti Mälkki
2016-02-18	util/autoport: Use common gpio.c for bd82x6x	Stefan Reinauer
2016-02-12	Merge sandy/ivybridge romstage flow for MRC and non-MRC.	Vladimir Serbinenko
2016-02-09	ivy: Add a possiblity for mainboard early init.	Vladimir Serbinenko
2016-01-11	autoport: Add missing casts	Vladimir Serbinenko
2016-01-03	sb/intel/bd82x6x: Add missing PCIIDs for variants .	Vladimir Serbinenko
2015-06-24	autoport: Include 'default_irq_route.asl' into DSDT	Stefan Reinauer
2015-05-30	autoport/bd82x6x: Fix off-by-one error	Vladimir Serbinenko
2015-05-29	autoport: Write autoport together with porting guide for sandy/ivybridge.	Vladimir Serbinenko