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path: root/util/autoport/bd82x6x.go
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2020-05-04treewide: Drop ACPI_VIDEO_DEVICE macroAngel Pons
It was always defined to the same value, and only used twice. Change-Id: I2736eb7ea2cf15475f7bb99d7d12450730eb8be0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40864 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-06util/autoport: Remove redundant commentAngel Pons
Nobody needs "LPC bridge PCI-LPC bridge". Change-Id: Iac833d4fa34b00d89bdfc9aeb06a96583840b900 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-01-08util/autoport: correct build errors of produced filesAngel Pons
Change-Id: I8d1a6af6f1d70268f17692bee130c08502082c97 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-19sb/intel/{bd82x6x|ibexpeak}: Drop p_cnt_throttling_supportedPatrick Rudolph
The processor P_BLK doesn't support throttling. This behaviour could be emulated with SMM, but instead just update the FADT to indicate no support for legacy I/O based throttling using P_CNT. We have _PTC defined in SSDT, which should be used in favour of P_CNT by ACPI aware OS, so this change has no effect on modern OS. Drop all occurences of p_cnt_throttling_supported and update autoport to not generate it any more. Change-Id: Iaf82518d5114d6de7cef01dca2d3087eea8ff927 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-21sb/intel/bd82x6x: Set up io_gen_dec in romstage based on devicetreeArthur Heymans
Set up generic decode ranges based on the devicetree settings. Change-Id: Ie59b8272c69231d6dffccee30b4d3c84a7e83e8f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-15autoport: Remove unneeded include <arch/io.h>Elyes HAOUAS
Change-Id: I7cb4b47e2fd893274303bb20dc7fa895830b4493 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-04-19src/mb/Kconfig: Fix PCI subsystem IDsElyes HAOUAS
References to MAINBOARD_PCI_SUBSYSTEM_{DEVICE_ID,VENDOR_ID} were removed in commits dbd3132 sb/intel/{i82801g/i/j,bd82x6x}: Make use of generic set_subsystem() 00bb441 sb/intel/lynxpoint: Remove PCI bridge function Change-Id: I72bba8406eea4a264e36cc9bcf467cf5cfbed379 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32107 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-18util/autoport: fix default headersAngel Pons
Change-Id: I1b46d76a86f5db02ebc452d43472b51f0414ad96 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-03-13util/autoport: Separate NB and SB PCIe port IDsAngel Pons
The root port IDs on bd82x6x.go were for both the PCH and the CPU PCIe root ports. Put the latter on sandybridge.go instead, and add missing IDs. Change-Id: I04b5220c460f1930accd64b63c11f512581f2c6c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30962 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-18util/autoport: Fix include styleAngel Pons
Change-Id: If0dfee38bd82b3c8e9b5173e520cb244787c0a9a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/30970 Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-15autoport: move the generated gnvs.c to acpi_tables.cIru Cai
Change-Id: I8f6eea579f69060608639b1c50255acd8ab5a4a2 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/30889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-10-04util/autoport: Use romstage.c instead of early_southbridge.cAngel Pons
Until now, autoport used to create a dummy "romstage.c", then write romstage code to "early_southbridge.c". While it works, it makes more sense to write to "romstage.c" instead, as virtually all mainboards do. Change-Id: If9f9375f9a659e7e685de5f884163813261fa656 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28851 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-16autoport: add missing PCI IDsDan Elkouby
As seen on ASUS P8Z77-V Pro Change-Id: I9fce9a35174b5120f67c2345a0807db1b843eb48 Signed-off-by: Dan Elkouby <streetwalkermc@gmail.com> Reviewed-on: https://review.coreboot.org/25661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-30autoport: Don't do writes to FD in romstageArthur Heymans
ff4025c5f "sb/intel/bd82x6x: Reduce function-disable mess" Removed most of the writes to RCBA(FD) and renamed the function to mainboard_rcba_config. Writes to FD are properly handled in ramstage, so no need to do it in romstage. Change-Id: I4edb75569ceec2d2f1308755a66d286202ca0ae6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-01-20autoport: Don't include default_irq_route.aslArthur Heymans
This file is no longer there since ACPI pirq routing is now done in an automated fashion in SSDT. Change-Id: I8bafafbf670fe0fc2f20b46b5d8abee722931c6d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christoph Pomaska <cp_public@posteo.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-07autoport: Add Intel PCIe Root Port and BridgesJean Lucas
- 0x0151: Xeon E3-1200 PCIe Root Port - 0x1e25: 7/C216 Series Chipset Family DMI to PCI Bridge - 0x2448: 82801 Mobile PCI Bridge - 0x244e: 82801 Desktop PCI Bridge Change-Id: I4111b73adc0f08d643c940cd43ab7fd4c0af7668 Signed-off-by: Jean Lucas <jean@4ray.co> Reviewed-on: https://review.coreboot.org/22794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2017-11-01autoport: move spi_uvscc and spi_lvscc to devicetree.cbIru Cai
Change-Id: I36866cc793b3ddf9a78fed2e2840958d08327e7d Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/20486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-06autoport: Add GPL boilerplate header to not empty .c filesArthur Heymans
The idea behind this not to enforce a license on autogenerated code but is simply out of convenience in the case one wants to make the result public (in which case it needs to have these license headers). Change-Id: I1d6b48762b1249bb0becb178a30e1396bf6978fc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19510 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-10-06autoport/bd82x6x.go: Improve gpio.c generationArthur Heymans
This generates better gpio.c files where structs are initialised as static to be able to drop some entries since those would be initialised as 0. This makes these files less cluttered since only relevant things are shown: * GPIO direction, level, invert, blink depend on GPIO mode * GPIO level is read only on input * GPIO invert is only valid on input * only show when GPIO are inverted, blinking, reset by RSMRST# Change-Id: I83382d38a4a3b7ed11b8e7077cc5fbe154e261a7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-07-31util/autoport: Remove copy-pasting of PMIR registerNico Huber
AFAIR from reviews, writing the PMIR (aka. ETR3) register never turned out to do anything useful. Change-Id: I119fb1212f360a59b695e2dfef68e19c330d01ca Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-01mb/*/mainboard.c: Get rid of SPI AFC registerPatrick Rudolph
The AFC—Additional Flash Control Register is set by southbridge code. Remove redundant calls and get rid of it in autoport. Change-Id: I627082e09dd055e3b3c4dd8e0b90965a9fcb4342 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19493 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-07autoport: Fix romstage generatorKyösti Mälkki
Prototype changed here: e258b9a intel sandy/ivy: Improve DIMM replacement detection Change-Id: Id79238db2e497b9163f3bd1b1d5d4bc11fe4da9e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17711 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-02-18util/autoport: Use common gpio.c for bd82x6xStefan Reinauer
In accordance to change I8bd981c4696c174152cf41caefa6c083650d283a change autoport as well, as suggested by Vladimir. Change-Id: I7cdaa779c11fd3f791a3ad213c24d927b5da76b9 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13731 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2016-02-12Merge sandy/ivybridge romstage flow for MRC and non-MRC.Vladimir Serbinenko
Change-Id: I11e09804ed1d8a7ae8b8d4502bd18f6be933f9fa Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13656 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09ivy: Add a possiblity for mainboard early init.Vladimir Serbinenko
This is needed for stout EC init. Change-Id: I5c73499c17763229840152a473a2d820802ee2f6 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13535 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-11autoport: Add missing castsVladimir Serbinenko
Change-Id: I04abdd48f5e2440756f9b03041d46c773f200368 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/12890 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-03sb/intel/bd82x6x: Add missing PCIIDs for variants .Vladimir Serbinenko
Change-Id: I917b8167a028aa9412b0cc6dedf8f09a1d1fae7f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/12820 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-06-24autoport: Include 'default_irq_route.asl' into DSDTStefan Reinauer
After commit with Change-Id Ia1839ed3 (sandy/ivy: Include IRQ routes from platform), update autoport to include that file into the DSDT. Change-Id: I14534438d0b433895f384539c8b413eaa53d943a Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10612 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-05-30autoport/bd82x6x: Fix off-by-one errorVladimir Serbinenko
Change-Id: Ibd5c8a1364ab183f72e12cc9b450a36200fe3fde Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10371 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-29autoport: Write autoport together with porting guide for sandy/ivybridge.Vladimir Serbinenko
This should be able to generate bootable ports for sandy/ivy, possible with minor fixes. Howto is in readme.md Change-Id: Ia126cf0939ef2dc2cdbb7ea100d2b63ea6b02f28 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7131 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
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