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2020-07-26mb/lenovo: Prepend EC event number with 0x to denote hex notationPaul Menzel
Currently, the message below is printed, suggesting it’s decimal notation: coreboot-4.12-1530-g7acbd5fc45 Sun Jul 19 07:47:58 UTC 2020 smm starting (log level: 7)... EC event 48 GPI (mask 1000) Prepend 0x, so it’s clear it’s hexadecimal notation. EC event 0x48 Use the command below change all places: git grep -l 'EC event %02x' | xargs sed -i 's/EC event %02x/EC event %#02x/' Change-Id: I8d1e6434a0e550c5a19576f9f7fea05e7a812e49 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26autoport: Don't initialize already initialized fields in acpi_tablesPeter Lemenkov
Don't initialize fields with zeroes since gnvs structs were zeroed out in southbridge already. Also add some comments. See also these commits: * Commit a76cf28 with Change-Id I2ccf4699ba3ed3f5b9402c0340153d4a5bf82682 ("mb/lenovo/*/acpi_tables: Don't initialize already initialized fields"). * Commit 0c52638 with Change-Id I71f092ed7582b4931122d72f41d0b42a7569b96e ("mb/lenovo: Remove thermal.h header"). Change-Id: I1a0042bc93a2b30babcb896b3df23faf37998f3c Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40479 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25autoport/bd82x6x.go: Remove generated extra lineElyes HAOUAS
Change-Id: I48125b7efd599b6a6718d7353156217df874d490 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-30ACPI: Drop typedef global_nvs_tKyösti Mälkki
Bring all GNVS related initialisation function to global scope to force identical signatures. Followup work is likely to remove some as duplicates. Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42489 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22src/mainboard: Remove unused include 'sandybridge.h'Elyes HAOUAS
Change-Id: I9356a56c34d1c6746cf8acfe931386ffed58ba74 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-15sandybridge boards: Factor out MAX_CPUSAngel Pons
Also update autoport accordingly. Change-Id: I12481363cf0e7afc54e2e339504f70632e8d72e2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41839 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18util/autoport/bd82x6x.go: Drop unused includesElyes HAOUAS
Change-Id: Ifc0bf18dedc112e346062e0e0e988ac102991bb8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40826 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-04treewide: Drop ACPI_VIDEO_DEVICE macroAngel Pons
It was always defined to the same value, and only used twice. Change-Id: I2736eb7ea2cf15475f7bb99d7d12450730eb8be0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40864 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-02acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-16autoport: use GMA_STATIC_DISPLAYSIru Cai
Change-Id: Ie988b2caeb2cdc07a3d6466b7ae3501df469ef41 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-16autoport: Support bigger ACPI tablesIru Cai
DSDT can be bigger than 0x10000 bytes, so increase the space up to 1MB for an ACPI table and support lines in acpidump.log with address higher than 0x10000. Change-Id: Iaadcfd0964c1c516e9e39d6cbfe41ec9a8c45e9d Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31759 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-24drivers/intel/gma: Ditch `link_frequency_270_mhz` settingNico Huber
The `link_frequency_270_mhz` setting was originally used by the native graphics init code for Sandy/Ivy Bridge, which is long gone. The value of this information (which board had it set) is questionable. The only board that had an LVDS panel and set it to 0 was the ThinkPad L520, where native graphics init was never reported to work. Also, the native graphics init only used it for calculations, but never confi- gured the hardware to use a specific frequency. A look into the docu- mentation also doesn't reveal any straps that could be used to confi- gure it. Change-Id: Ieceaa13e4529096a8ba9036479fd84969faebd14 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39763 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-20util/autoport: Emit SPDX license headersAngel Pons
Change-Id: I8896b6c92c3126cc611e47b39d596108b90c6bf2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-18util/autoport: Correct formatting issuesAngel Pons
There is no need to use hexadecimal values in azalia codec IDs, nor need to print a redundant "LPC bridge PCI-LPC bridge" comment. Change-Id: I6658051c7a3d5b65a86ccca8bab7834bf4628a16 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-03-093rdparty/libgfxinit: Update submodule pointerNico Huber
Changes allow to use the integrated panel logic (power sequen- cing and backlight control) for more connectors. The Kconfigs GFX_GMA_PANEL_1_PORT and GFX_GMA_PANEL_2_PORT can now be set to any port, e.g. config GFX_GMA_PANEL_1_PORT default "DP3" Now that the panel logic is not tied to the `Internal` port choice anymore, we can properly split it into `LVDS` and `eDP`. This also adds Comet Lake PCI IDs which should still work the same as Kaby and Coffee Lake. Change-Id: I78b1b458ca00714dcbe7753a7beb4fb05d69986b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38921 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-06util/autoport: Remove redundant commentAngel Pons
Nobody needs "LPC bridge PCI-LPC bridge". Change-Id: Iac833d4fa34b00d89bdfc9aeb06a96583840b900 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-03LGA1155 mainboards: Remove gfx.did and gfx.ndidAngel Pons
They are downright useless and result in ACPI errors. So, burn them. Also, do a minor update to autoport's README about these values. Change-Id: Idb5832cfd2e3043b8d70e13cbbe8bd94ad613120 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-02-17util/autoport: Fix typoAngel Pons
Also reflow the paragraph in which the typo was hiding a bit. Change-Id: I2fea01fe23af21c2540fa90154ce29af3e74776b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
2020-02-17autoport: Remove space in example codePaul Menzel
The coreboot coding style does not insert a space between the function and argument list. Change-Id: I740f6c7f513e4f2715c793f61c9d9835c55c9dce Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-28autoport: Don't add useless whitespace in commentsPeter Lemenkov
Change-Id: Ie6c94c0627743f9e965347ecfd28f1b0441178ad Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38516 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-16autoport: Improve formatting of EC ASL codePaul Menzel
Change-Id: I7fe3e798346e760eebb357f20e55ee1a71a1e31a Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-15autoport: Use HTTPS URLsPaul Menzel
Update the two flashrom URLs to use HTTPS. All other URLs are already using HTTPS. Change-Id: I8e9861b2748289522ab418960a463ae55ab0d2d3 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-14autoport: Add Xeon E3-1200 v2 memory controller IDJonathan A. Kollasch
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Change-Id: Ic5f18669a04397f570d49c1ff056cd90b3eb04a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-01-08util/autoport: correct build errors of produced filesAngel Pons
Change-Id: I8d1a6af6f1d70268f17692bee130c08502082c97 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-12util/autoport: Stop generate empty h8_mainboard_init_dock().Bill XIE
CB:36385 makes dock init in ramstage fully mainboard-specific, so keeping generating empty h8_mainboard_init_dock() for lenovo EC becomes unnecessary and problematic. Change-Id: I19f57f41403ffd0319cc86f21bec7e142095df83 Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-08-20mb,autoport: Fix GCC 9 Port_List build errorJacob Garber
Port_List is an array of 8 elements, and GCC 9 is warning that there are no 'others' when all 8 elements are explicitly initialized, which is causing the build to fail. Remove the 'others => Disabled' clause to silence this. Change-Id: Id082e7a76641438f3fb4c4d976dbd254a7053473 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34918 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-19sb/intel/{bd82x6x|ibexpeak}: Drop p_cnt_throttling_supportedPatrick Rudolph
The processor P_BLK doesn't support throttling. This behaviour could be emulated with SMM, but instead just update the FADT to indicate no support for legacy I/O based throttling using P_CNT. We have _PTC defined in SSDT, which should be used in favour of P_CNT by ACPI aware OS, so this change has no effect on modern OS. Drop all occurences of p_cnt_throttling_supported and update autoport to not generate it any more. Change-Id: Iaf82518d5114d6de7cef01dca2d3087eea8ff927 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-21sb/intel/bd82x6x: Set up io_gen_dec in romstage based on devicetreeArthur Heymans
Set up generic decode ranges based on the devicetree settings. Change-Id: Ie59b8272c69231d6dffccee30b4d3c84a7e83e8f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-06-09autoport: Generate a libgfxinit template when IGD is detectedIru Cai
Change-Id: I213628e525cc11c502de7d538bd60f49f3a930b9 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-05-29util/autoport: Add info about rank 1 mirroringEvgeny Zinoviev
inteltool can't detect whether address mapping is normal or mirrored, which in turn may be cause RAM initialization to fail when using spd.bin generated by inteltool. Mention this in readme as it may help someone. Change-Id: I8d24e4d9332bdcf484987581dd6941e2bf9c4f87 Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-05-23util/autoport: Mention i2c-i801 module in readme.mdEvgeny Zinoviev
SMBus adapter will not appear if i2c-i801 module is not loaded. Added it to the readme. Change-Id: I3de0e02f13178d78b8cc02a74a745ad66e929070 Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-15autoport: Remove unneeded include <arch/io.h>Elyes HAOUAS
Change-Id: I7cb4b47e2fd893274303bb20dc7fa895830b4493 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-12nb/intel/snb: Drop NORTHBRIDGE_INTEL_IVYBRIDGENico Huber
We keep the support, though. Just now that `libgfxinit` is fixed, we don't need the distinction anymore. Causally, we also don't need CPU_INTEL_MODEL_306AX any more. TEST=Played tint on kontron/ktqm77. Score 606 Change-Id: Id1e33c77f44a66baacba375cbb2aeb71effb7b76 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-04-19src/mb/Kconfig: Fix PCI subsystem IDsElyes HAOUAS
References to MAINBOARD_PCI_SUBSYSTEM_{DEVICE_ID,VENDOR_ID} were removed in commits dbd3132 sb/intel/{i82801g/i/j,bd82x6x}: Make use of generic set_subsystem() 00bb441 sb/intel/lynxpoint: Remove PCI bridge function Change-Id: I72bba8406eea4a264e36cc9bcf467cf5cfbed379 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32107 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-18util/autoport: Rewrite readme.mdAngel Pons
The last part of the file has not been modified much. Change-Id: Icc45824d5d1298146f459d75f0a5121dbdd70d41 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30969 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-18util/autoport: Trim gfx.did to sizeAngel Pons
Since the values are hardcoded, we might as well hardcode values that make sense. Change-Id: I3ac0e2d74a42c1fe55b1cdc3e2a970ae80cc9f37 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30963 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-18util/autoport: fix default headersAngel Pons
Change-Id: I1b46d76a86f5db02ebc452d43472b51f0414ad96 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-03-14util/autoport: remove obsolete symbol SANDYBRIDGE_IVYBRIDGE_LVDSAlexander Couzens
This symbol was removed in a6be58fecec5 ("nb/intel/sandybridge: Remove the C native graphic init") Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Change-Id: I87801552e1c37162897949ec0db3904f850f0bfe Reviewed-on: https://review.coreboot.org/c/coreboot/+/31823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-03-13util/autoport: Separate NB and SB PCIe port IDsAngel Pons
The root port IDs on bd82x6x.go were for both the PCH and the CPU PCIe root ports. Put the latter on sandybridge.go instead, and add missing IDs. Change-Id: I04b5220c460f1930accd64b63c11f512581f2c6c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30962 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24cpu/intel/model_206ax: Remove the notion of socketsArthur Heymans
With the memory controller the separate sockets becomes a useless distinction. They all used the same code anyway. UNTESTED: This also updates autoport. Change-Id: I044d434a5b8fca75db9eb193c7ffc60f3c78212b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/31031 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-20util/autoport: Make dsdt.asl prettierAngel Pons
Small cosmetic changes which fix aesthetic inaccuracies. Change-Id: I8fef4bbe12b283cee2ab8d078de950171757bbfe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/30971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2019-01-18util/autoport: Fix include styleAngel Pons
Change-Id: If0dfee38bd82b3c8e9b5173e520cb244787c0a9a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/30970 Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-18util/autoport: Break very long lineAngel Pons
Change-Id: Id45b0970a457ad4a724b71b4887ce4a1332596be Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/30968 Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-18util/autoport: Correct DSDT include statementAngel Pons
With commit aaced4a (cpu/intel/common: Use a common acpi/cpu.asl file), some model_206ax code was moved to a common place. However, autoport was not updated accordingly. Change-Id: I51b7e9c5d226f591596c33d6a3cb326a34420493 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/30967 Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-15autoport: move the generated gnvs.c to acpi_tables.cIru Cai
Change-Id: I8f6eea579f69060608639b1c50255acd8ab5a4a2 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/30889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04util/autoport/readme.md: Correct minor inconsistencyAngel Pons
Commit a5072af67d85 ("util/autoport: Use romstage.c instead of early_southbridge.c") changed where the SPD map is. Reflect that. Change-Id: Id0bd1778617371bac5921c4eae63d0beb088216c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/30655 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-28mb/*/*/Kconfig: Remove useless commentElyes HAOUAS
Change-Id: Ibdff50761a205d936b0ebe067f418be0a2051798 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hellsenberg <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: David Guckian Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-23mb: Set coreboot as DSDT's manufacturer model IDElyes HAOUAS
Field 'OEMID' & "OEM Table ID" are related to DSDT table not to mainboard. So use macro to set them respectvely to "COREv4" and "COREBOOT". Change-Id: I060e07a730e721df4a86128ee89bfe168c69f31e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: David Guckian
2018-11-21ACPI: Fix DSDT's revision fieldElyes HAOUAS
DSDT revision is =1 for ACPI v1 and =2 for greater ACPI version. This will cause the AML interpreter to use 32-bit integers and math if the version is 1, and 64-bit if the version is >=2. Current spec version is 2 for ACPI 6.2-a. Change-Id: I77372882d5c77b7ed52dcdd88028403df6f6fa7f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29626 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 11:47:25 +0000