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path: root/util/flashrom
AgeCommit message (Collapse)Author
2007-10-30Add support for Intel 440MX systems.Uwe Hermann
Add support for the Fujitsu MBM29F400TC flash part. Detection and reading works, writing is not tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2903 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-25Added Am29LV040BPeter Lemenkov
Looking through the sources of Uniflash utility I found that this chip is no more no less than low-voltage variant of Am29F040B but with different ID. So I created a very quick patch (attached). Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2897 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-22Flashrom: Add more Vendor IDs and ensure correct sorting in flash.h.Peter Lemenkov
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2884 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-22Introduce block and sector erase routines to flashrom, but do not useCarl-Daniel Hailfinger
them yet. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2881 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-18Remove hardcoded wait from SPI write/erase routines and check the chipCarl-Daniel Hailfinger
status register instead. This has been tested by Harald Gutmann <harald.gutmann@gmx.net> with a MX25L4005 chip. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2876 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-18Documentation fixes and updates (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2875 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-18Add generic SPI flash erase and write support to flashrom. The firstCarl-Daniel Hailfinger
chip the code was tested and verified with is the Macronix MX25L4005, but other chips should work as well. Timeouts are still hardcoded to data sheet maxima, but the status register checking code is already there. Thanks to Harald Gutmann for the initial code on which this is loosely based. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2874 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-17Some cosmetic cleanups in the flashrom code and output.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2873 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-17Fix wrong values/typos in chipset_enable.c. This has been confirmed byCarl-Daniel Hailfinger
Ed Swierk in http://www.mail-archive.com/linuxbios@linuxbios.org/msg09788.html . Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2868 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-16Multiple flashrom fixes:Uwe Hermann
- Install binary in /usr/sbin (not /usr/bin), as it's a root-only tool. - Rename manpage from flashrom.1 to flashrom.8, as section 8 contains "System administration commands (usually only for root)". - Actually install the manpage upon 'make install'. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2866 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-16Add Gigabyte M61P-S3 SPI flash support to board_enable.cMichael van der Kolff
Signed-off-by: Michael van der Kolff <mvanderkolff@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2864 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-16Convert the existing it8716f_* functions to generic_spi_* functions byCarl-Daniel Hailfinger
applying abstraction and wrapping. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2863 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-15(forgot to add spi.c)Carl-Daniel Hailfinger
Move SPI code out of board_enable.c where it started its life. The SPI chip finding and SPI chip accessor code is moved as well. This can be split later if we feel like it. The non-use of svn cp is intentional because the only history we'd have to preserve are a few commits which were early prototypes of chip identification code. For those who intend to look at that history, they can look at board_enable.c revision 2853. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2858 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-15Move SPI code out of board_enable.c where it started its life. The SPICarl-Daniel Hailfinger
chip finding and SPI chip accessor code is moved as well. This can be split later if we feel like it. The non-use of svn cp is intentional because the only history we'd have to preserve are a few commits which were early prototypes of chip identification code. For those who intend to look at that history, they can look at board_enable.c revision 2853. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2857 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-12Changes to flashrom to support the K8N-NEO3, first tested at Google on GSOC ↵Ronald G. Minnich
day :-) Also minor changes to remove tab-space combinations where possible. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Signed-off-by: David Hendricks <david.hendricks@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> Index: jedec.c =================================================================== --- jedec.c (revision 2847) +++ jedec.c (working copy) @@ -281,7 +281,7 @@ // dumb check if erase was successful. for (i = 0; i < total_size; i++) { if (bios[i] != (uint8_t) 0xff) { - printf("ERASE FAILED\n"); + printf("ERASE FAILED @%d, val %02x\n", i, bios[i]); return -1; } } Index: board_enable.c =================================================================== --- board_enable.c (revision 2847) +++ board_enable.c (working copy) @@ -153,7 +153,8 @@ return 1; } /* Start IO, 33MHz, readcnt input bytes, writecnt output bytes. Note: - We can't use writecnt directly, but have to use a strange encoding */ + * We can't use writecnt directly, but have to use a strange encoding + */ outb((0x5 << 4) | ((readcnt & 0x3) << 2) | (writeenc), port); do { busy = inb(port) & 0x80; @@ -202,43 +203,39 @@ /* * Helper functions for many Winbond Super I/Os of the W836xx range. */ -#define W836_INDEX 0x2E -#define W836_DATA 0x2F - /* Enter extended functions */ -static void w836xx_ext_enter(void) +static void w836xx_ext_enter(uint16_t port) { - outb(0x87, W836_INDEX); - outb(0x87, W836_INDEX); + outb(0x87, port); + outb(0x87, port); } /* Leave extended functions */ -static void w836xx_ext_leave(void) +static void w836xx_ext_leave(uint16_t port) { - outb(0xAA, W836_INDEX); + outb(0xAA, port); } /* General functions for reading/writing Winbond Super I/Os. */ -static unsigned char wbsio_read(unsigned char index) +static unsigned char wbsio_read(uint16_t index, uint8_t reg) { - outb(index, W836_INDEX); - return inb(W836_DATA); + outb(reg, index); + return inb(index+1); } -static void wbsio_write(unsigned char index, unsigned char data) +static void wbsio_write(uint16_t index, uint8_t reg, uint8_t data) { - outb(index, W836_INDEX); - outb(data, W836_DATA); + outb(reg, index); + outb(data, index+1); } -static void wbsio_mask(unsigned char index, unsigned char data, - unsigned char mask) +static void wbsio_mask(uint16_t index, uint8_t reg, uint8_t data, uint8_t mask) { - unsigned char tmp; + uint8_t tmp; - outb(index, W836_INDEX); - tmp = inb(W836_DATA) & ~mask; - outb(tmp | (data & mask), W836_DATA); + outb(reg, index); + tmp = inb(index+1) & ~mask; + outb(tmp | (data & mask), index+1); } /** @@ -248,37 +245,80 @@ * - Agami Aruma * - IWILL DK8-HTX */ -static int w83627hf_gpio24_raise(const char *name) +static int w83627hf_gpio24_raise(uint16_t index, const char *name) { - w836xx_ext_enter(); + w836xx_ext_enter(index); /* Is this the w83627hf? */ - if (wbsio_read(0x20) != 0x52) { /* SIO device ID register */ + if (wbsio_read(index, 0x20) != 0x52) { /* Super I/O device ID register */ fprintf(stderr, "\nERROR: %s: W83627HF: Wrong ID: 0x%02X.\n", - name, wbsio_read(0x20)); - w836xx_ext_leave(); + name, wbsio_read(index, 0x20)); + w836xx_ext_leave(index); return -1; } /* PIN89S: WDTO/GP24 multiplex -> GPIO24 */ - wbsio_mask(0x2B, 0x10, 0x10); + wbsio_mask(index, 0x2B, 0x10, 0x10); - wbsio_write(0x07, 0x08); /* Select logical device 8: GPIO port 2 */ + wbsio_write(index, 0x07, 0x08); /* Select logical device 8: GPIO port 2 */ - wbsio_mask(0x30, 0x01, 0x01); /* Activate logical device. */ + wbsio_mask(index, 0x30, 0x01, 0x01); /* Activate logical device. */ - wbsio_mask(0xF0, 0x00, 0x10); /* GPIO24 -> output */ + wbsio_mask(index, 0xF0, 0x00, 0x10); /* GPIO24 -> output */ - wbsio_mask(0xF2, 0x00, 0x10); /* Clear GPIO24 inversion */ + wbsio_mask(index, 0xF2, 0x00, 0x10); /* Clear GPIO24 inversion */ - wbsio_mask(0xF1, 0x10, 0x10); /* Raise GPIO24 */ + wbsio_mask(index, 0xF1, 0x10, 0x10); /* Raise GPIO24 */ - w836xx_ext_leave(); + w836xx_ext_leave(index); return 0; } +static int w83627hf_gpio24_raise_2e(const char *name) +{ + return w83627hf_gpio24_raise(0x2d, name); +} + /** + * Winbond W83627THF: GPIO 4, bit 4 + * + * Suited for: + * - MSI K8N-NEO3 + */ +static int w83627thf_gpio4_4_raise(uint16_t index, const char *name) +{ + w836xx_ext_enter(index); + /* Is this the w83627thf? */ + if (wbsio_read(index, 0x20) != 0x82) { /* Super I/O device ID register */ + fprintf(stderr, "\nERROR: %s: W83627THF: Wrong ID: 0x%02X.\n", + name, wbsio_read(index, 0x20)); + w836xx_ext_leave(index); + return -1; + } + + /* PINxxxxS: GPIO4/bit 4 multiplex -> GPIOXXX */ + + wbsio_write(index, 0x07, 0x09); /* Select logical device 9: GPIO port 4 */ + + wbsio_mask(index, 0x30, 0x02, 0x02); /* Activate logical device. */ + + wbsio_mask(index, 0xF4, 0x00, 0x10); /* GPIO4 bit 4 -> output */ + + wbsio_mask(index, 0xF6, 0x00, 0x10); /* Clear GPIO4 bit 4 inversion */ + + wbsio_mask(index, 0xF5, 0x10, 0x10); /* Raise GPIO4 bit 4 */ + + w836xx_ext_leave(index); + + return 0; +} + +static int w83627thf_gpio4_4_raise_4e(const char *name) +{ + return w83627thf_gpio4_4_raise(0x4E, name); +} +/** * Suited for VIAs EPIA M and MII, and maybe other CLE266 based EPIAs. * * We don't need to do this when using LinuxBIOS, GPIO15 is never lowered there. @@ -335,12 +375,12 @@ pci_write_byte(dev, 0x59, val); /* Raise ROM MEMW# line on Winbond w83697 SuperIO */ - w836xx_ext_enter(); + w836xx_ext_enter(0x2E); - if (!(wbsio_read(0x24) & 0x02)) /* flash rom enabled? */ - wbsio_mask(0x24, 0x08, 0x08); /* enable MEMW# */ + if (!(wbsio_read(0x2E, 0x24) & 0x02)) /* flash rom enabled? */ + wbsio_mask(0x2E, 0x24, 0x08, 0x08); /* enable MEMW# */ - w836xx_ext_leave(); + w836xx_ext_leave(0x2E); return 0; } @@ -487,9 +527,11 @@ {0x10de, 0x0360, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, "gigabyte", "m57sli", "GIGABYTE GA-M57SLI", it87xx_probe_serial_flash}, {0x1022, 0x7468, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - "iwill", "dk8_htx", "IWILL DK8-HTX", w83627hf_gpio24_raise}, + "iwill", "dk8_htx", "IWILL DK8-HTX", w83627hf_gpio24_raise_2e}, + {0x10de, 0x005e, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + "msi", "k8n-neo3", "MSI K8N Neo3", w83627thf_gpio4_4_raise_4e}, {0x1022, 0x746B, 0x1022, 0x36C0, 0x0000, 0x0000, 0x0000, 0x0000, - "AGAMI", "ARUMA", "agami Aruma", w83627hf_gpio24_raise}, + "AGAMI", "ARUMA", "agami Aruma", w83627hf_gpio24_raise_2e}, {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, "VIA EPIA M/MII/...", board_via_epia_m}, {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, @@ -509,8 +551,8 @@ * Match boards on LinuxBIOS table gathered vendor and part name. * Require main PCI IDs to match too as extra safety. */ -static struct board_pciid_enable *board_match_linuxbios_name(char *vendor, - char *part) +static struct board_pciid_enable *board_match_linuxbios_name(char *vendor, + char *part) { struct board_pciid_enable *board = board_pciid_enables; @@ -525,10 +567,11 @@ continue; if (board->second_vendor && - !pci_dev_find(board->second_vendor, board->second_device)) + !pci_dev_find(board->second_vendor, board->second_device)) continue; return board; } + printf("NOT FOUND %s:%s\n", vendor, part); return NULL; } @@ -545,20 +588,20 @@ continue; if (!pci_card_find(board->first_vendor, board->first_device, - board->first_card_vendor, - board->first_card_device)) + board->first_card_vendor, + board->first_card_device)) continue; if (board->second_vendor) { if (board->second_card_vendor) { if (!pci_card_find(board->second_vendor, - board->second_device, - board->second_card_vendor, - board->second_card_device)) + board->second_device, + board->second_card_vendor, + board->second_card_device)) continue; } else { if (!pci_dev_find(board->second_vendor, - board->second_device)) + board->second_device)) continue; } } @@ -582,7 +625,7 @@ if (board) { printf("Found board \"%s\": Enabling flash write... ", - board->name); + board->name); ret = board->enable(board->name); if (ret) git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2850 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-10Revert my last cleanup patch.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2847 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-10Cosmetic changes to make the flashrom output more consistent (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2846 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-04[FLASHROM] Fix the help, and print a message when nothing happensJordan Crouse
The help implied that writes happen by default, which they don't. Fix the text, and say something when we dont specify any commands. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2820 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-02This patch aims to restructure SPI flash support in a more reasonableCarl-Daniel Hailfinger
way. It introduces a generic SPI host driver for the IT8716F Super I/O which will enable easy SPI programming without having to care for the peculiarities of the SPI host. To activate probing for the IT8716F, you have to use the gigabyte:m57sli mainboard override. SPI support will then use the gathered SPI host data to access the SPI flash. This has been tested sucessfully by Ward Vandewege <ward@gnu.org> on the GA-M57SLI v2.0, which has a MX25L4005 SPI flash part. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2817 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-27Add preliminary SPI flash identification support for SPI chips attachedCarl-Daniel Hailfinger
to ITE IT8716F Super I/O. Right now this is hardcoded to the Gigabyte M57SLI board. It works only with rev 2.0 of the board, but it will bail out on earlier versions, so no damage can occur. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2811 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-11Change out/in combinations to pci_read/write_byte inAlex Beregszaszi
sis630 chipset enable. Signed-off-by: Alex Beregszaszi <alex@rtfs.hu> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2770 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-09Remove useless 'extern' keywords (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2769 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-09Add '(C)' where it's missing (for consistency reasons).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2768 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-09Add missing license header to udelay.c.Uwe Hermann
I'm self-ack'ing this, as the origin of the code in udelay.c (and thus the license and copyright owner) is pretty clear. The code which is now in udelay.c was split out from flash_rom.c in r1428, and flash_rom.c, in turn, has been around since the beginning and had a 'Copyright 2000 Silicon Integrated System Corporation' line as well as the usual GPLv2-or-later license header. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2767 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-08Add a copy of the GPL in the flashrom repository as it's an independentUwe Hermann
project (being packaged by distros, among other things). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2764 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-30Add support for the Winbond W29EE011.Markus Boas
Signed-off-by: Markus Boas <ryven@ryven.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2753 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-30Add support for the Winbond W29C040P.Markus Boas
Signed-off-by: Markus Boas <ryven@ryven.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2752 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-29Change all flashrom license headers to use our standard format.Uwe Hermann
No changes in content of the files. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2751 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-23Cosmetic fixes (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2748 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-23Drop duplicated code (copies of plain JEDEC functions).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2747 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-23Drop a bunch of useless header files, merge them into flash.h.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2746 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-23Move code into *.c files, there's no reason to have it in header files.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2745 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-13Fix bug in probe_28sf040() causing flash corruption on SST49LF160C verify.Ed Swierk
The first byte of the flash chip was read at the start of the function and later written back to address 0 if the flash chip was not identified as SST28SF040, which means most of the time. This write caused corruption of flash contents when verifying a SST49LF160C part. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2744 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-11flashrom: Add board enable for the EPoX EP-BX3.Luc Verhaegen
Signed-off-by: Luc Verhaegen <libv@skynet.be> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2743 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-07-27flashrom: Add missing supported flash chips to the README (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2742 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-07-25This patch adds support for the M50FLW040A, M50FLW040B, M50FLW080A,Carl-Daniel Hailfinger
M50FLW080B, M50FW080, M50FW016, M50LPW116, M29W010B flash chips made by ST to flashrom. The patch is based on the data sheets of the chips and has not been tested at all. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2741 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-07-24This patch adds support for ST M50FW040 and ST M29W040B to flashrom.Carl-Daniel Hailfinger
Only reading from the chips was tested; writing support is untested. Thanks to Gürkan Sengün <gurkan@linuks.mine.nu> for testing! Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2740 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-07-04Flashrom: Add support for Tyan Tomcat K7M.Luc Verhaegen
Same board enable as Asus A7V8-MX. Tested by Reinhard Max. Signed-off-by: Luc Verhaegen <libv@skynet.be> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2732 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-06Fix up and document the AMD CS5530/CS5530A support in flashrom.Uwe Hermann
The previous code was pretty unreadable, undocumented and did some totally unrelated things (such as mucking with the game port or port 0x92). This version is tested with a 256 KB chip and should work for the CS5530 and CS5530A. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2715 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-05flashrom: Document the newly supported IBM x3455 board and theUwe Hermann
now-supported Broadcom HT-1000 chipset (trivial). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2713 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-05Move GPIO settings to board specific code for IBM x3455Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2712 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-05Add support for BCM HT1000 chipset to flashrom. Tested on IBM x3455.Stefan Reinauer
(trivial) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2711 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-24Minor cosmetics (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2696 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-24drop leftover includes (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2693 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-24some copyright analysisStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2692 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-24factor out register mapping code (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2691 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-23Unify mmap error messages in flashrom (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2690 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-23big cosmetic offensive on flashrom. (trivial)Stefan Reinauer
* Give decent names to virt_addr and virt_addr_2 * add some comments * move virtual addresses to the end of the struct, so they dont mess up the initializer. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2689 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-21Add support for the Winbond W39V040FA chip.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2686 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-20Flashrom: add support for ASUS P5A (Socket 7, ALi based).Luc Verhaegen
* Add support for the ALi M1533 to chipset_enable.c * Add some SMBus poking needed for the ASUS P5A, to board_enable.c Since PCI subsystem IDs are worthless with this board, people will have to name the board directly. Signed-off-by: Luc Verhaegen <libv@skynet.be> Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2677 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 05:46:51 +0000