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2019-05-15util/inteltool: Add Kabylake E3-1200 SupportChristian Walter
Change-Id: I5c55102d7ce15dbb708e9433500ebd1ed53179ad Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-06inteltool: Add Sunrise Point-LP Skylake PCH IDsFelix Singer
Sunrise Point-LP is used on Skylake and KabyLake platforms, but the PCH IDs differ. This commit adds the PCH IDs for Skylake mobile platforms and renames the Kabylake macros to distinguish them. Used Intel documents: - 332995-001EN (I/O datasheet vol. 1) - 332996-002EN (I/O datasheet vol. 2) Change-Id: Id46224fcc44b06c91cbcd6c74a55c95e1de65ec6 Signed-off-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-03-15inteltool: add 300 and C240 Series PCHThomas Heijligen
Values from - Intel doc 337347 rev4 - coreboot soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h On Coffeelake H (using Cannonlake / Cannonpoint PCH) p2sb is not accessible. Using a static value instead. 0xfd000000 is a common value chosen by coreboot and non-coreboot firmware. Change-Id: Id637f703ab0a99eb0908ecdc3da27ba80db1c6b8 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-06inteltool: Add multiple device IDs of Intel GPUsFelix Singer
* Intel HD Graphics 510 * Intel HD Graphics 515 * Intel HD Graphics 520 * Intel HD Graphics 530 (2x) * Intel UHD Graphics 615 (2x) * Intel UHD Graphics 617 * Intel UHD Graphics 620 (3x) * Intel UHD Graphics 630 (7x) * Intel UHD Graphics 640 * Intel Iris Graphics 540 * Intel Iris Graphics 550 * Intel Iris Pro Graphics 580 * Intel Iris Plus Graphics 650 * Intel Iris Plus Graphics 655 Change-Id: I299a5fc082433b0aab4861a24aecbe83b61a404a Signed-off-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30610 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-21util/inteltool: Add support for DenvertonThomas Heijligen
Used documents: - C3000 Product Family Datasheet Change-Id: I54d09c78e1cce84b63300dfc0aa1bb374bb7faae Co-authored-by: Felix Singer <migy@darmstadt.ccc.de> Signed-off-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-on: https://review.coreboot.org/c/30887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-12-28util/inteltool: Add support for Sunrise Point LPMatthew Garrett
Used documents: 334658 (Sunrise Point-LP I/O datasheet vol. 1) 334659 (Sunrise Point-LP I/O datasheet vol. 2) 332690 (Sunrise Point I/O datasheet vol. 1) Change-Id: I16237ffc9a225b46271f2a51d77a7f28dfc36138 Signed-off-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-on: https://review.coreboot.org/c/28623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-11-29util/inteltool: Add Apollo Lake LPC ID and allow to read PCRsNico Huber
The P2SB (PCI to Side-Band) bridge is on a different PCI device on APL. Hence, we have to decide based on the LPC ID which device to query. Also fix a comment. Change-Id: Ie20d7d2d246629d085bcf4740ba28b1e81e6a12a Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/29896 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-21inteltool: Add PCI IDs for the C220 PCH seriesqeed
Adds missing PCI IDs to allow tool to dump the C220 PCH (8 series) southbridge. Intel Document 328904 is the datasheet for this PCH. Change-Id: I07a8f2e9cb0ee8677c8fe2c51881147ed81c1a35 Signed-off-by: Quan Tran <qeed.quan@gmail.com> Reviewed-on: https://review.coreboot.org/27168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-11inteltool: Add dumping of full PCR portsYouness Alaoui
SoCs from Skylake on have many settings as so called private con- figuration registers (PCRs). These are organized as 256 ports with a 64KiB space each. We use the Primary to Sideband (P2SB) bridge's BAR to access them. Change-Id: Iede4ac601355e2be377bc986d62d20098980ec35 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19593 Reviewed-by: Youness Alaoui <snifikino@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-27inteltool: Add some Skylake desktop idsNico Huber
Change-Id: I1738a2544eb2435cb4b8718bcce5170d1ef04f72 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/25144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-03-15util/inteltool: Add missing #include <string.h>Nico Huber
Change-Id: I7bb142d9f936b73e84d301028069d85cc15d596a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/25143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-15inteltool: Support for nasty Primary to Sideband Bridge (P2SB)Nico Huber
The Primary to Sideband Bridge (P2SB) is the interface to Private Con- figuration Registers (PCR) including GPIO configuration. Of course, access is restricted to Intel partners and criminals, so the PCI device is hidden from the OS. Probably we only need to fetch the SBREG_BAR address and can hide the PCI device again after that. Change-Id: Ic121a09f021708aab82ae4b9d76d6c3c6fb884fa Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-10util/inteltool: Add Skylake Desktop NorthbridgeChristoph Pomaska
Add the 8086:191f North/Host Bridge to the list of definitions. Adding the definiton makes the Northbridge get recognized by inteltool. It is found in the Intel i5-6600K CPU: https://ark.intel.com/products/88191/Intel-Core-i5-6600K-Processor-6M-Cache-up-to-3_90-GHz Change-Id: Id746d1e8b3bb90b3b68a2f6c372890671dd61b5f Signed-off-by: Christoph Pomaska <cp_public@gmx.de> Reviewed-on: https://review.coreboot.org/23055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-12-20util/inteltool: Add GPU device IDsPatrick Rudolph
Add PCI device IDs for several Intel GPUs. Change-Id: I7d6ba16b2b115187fd57a31716f23a610b520d3e Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-11-03inteltool: Add southbridge and CPU definitions for SkylakeMaximilian Schander
Change-Id: Id9501f11a79cb314bc407760b22006a3375e669d Signed-off-by: Maximilian Schander <maxschander@googlemail.com> Reviewed-on: https://review.coreboot.org/22211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-08-20util/inteltool: Fix a comparison between signed and unsigned integersMaciej Suminski
Change-Id: Ic6489c408a87213d3c39626c5379a44acea2c34d Signed-off-by: Maciej Suminski <maciej.suminski@cern.ch> Reviewed-on: https://review.coreboot.org/21024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-07-28util/inteltool: Clean up checkpatch.pl warningsPratik Prajapati
Remove braces around single statements. "WARNING: braces {} are not necessary for single statement blocks" Change-Id: Id5a7dc3a9672266b66d7f46db2ff087b98fd174d Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/20771 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-28util/inteltool: Add support for SGX statusPratik Prajapati
Add support for dumping Intel Software Guard Extension (SGX) status. --sgx or -x is the command line switch to get SGX status. The code iterates through all cores and reads MSRs to check if SGX is supported, enabled and the feature is locked. Change-Id: I1f5046c1f6703f5429c8717053ffe9c981cedf6f Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/20758 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-06inteltool/ahci: Add Skylake supportNico Huber
The SATA device moved from 0:1f.2 to 0:17.0, 0:1f.2 became PMC. We detect that by checking the PCI device class. The ABAR MMIO space has grown to 2KiB and up to 8 ports are supported now. For backwards compatibility, only dump port registers of ports that are enabled in the Ports Implemented (PI) register. Change-Id: I8e0f07d7359d92f689882b5afefa5ffb3766ee8b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-06inteltool: Fix clean-up and close related TODONico Huber
We have to call pci_free_dev() for each device we allocated with pci_get_dev(). Since that's not the case for `sb`, we can close this TODO. Change-Id: I1ef80c837263a205467f835156dcb8fa667d3a8f Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-06inteltool: Add first Skylake PCI IDsNico Huber
Change-Id: Ia5ef6b04f01e381174a4d8f73ddafeb18d488803 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-06inteltool: Don't use PCI_FILL_SIZESNico Huber
This is supposed to fill the `size[]` array with the actual sizes of a device' MMIO ranges, but apparently isn't implemented for every access method in libpci (we let the library choose one). It tells us by clearing `PCI_FILL_SIZES` in the return value of `pci_fill_info()` (which we don't check). Since we don't ever use `size`, we can just make it clear and don't ask for it. Change-Id: I3fb9334472f1c7563a9e17910190f73affbe067a Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-05-01util/inteltool: Break long lines in supported_chips_listYouness Alaoui
Lint prevents my next commit which adds a new line to the table so it's better to break all the > 80 character lines so it will be consistent with the new line I'm about to add. Change-Id: Ic7ad0cb90e861cd830db1186225d4f839250792a Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/19444 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-15util/inteltool: Add ICH10 (Consumer Base) supportArthur Heymans
Reuses ICH10R functions. TESTED on Intel DG43GT (Not supported by coreboot) Change-Id: If9ae8ba8b95e3a7bf6596ae639eb8cafab583298 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19232 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-21util/inteltool: Fix bay trail ahci deviceMarshall Dawson
Use a unique bus/device/function if a bay trail LPC bridge was found. TEST=Run on MinnowBoard MAX Turbot and customer's LynxPoint-LP. Change-Id: Ib4b50aaf9817ac94f46c28925081540676226d84 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/17464 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-21inteltool: add --ahci for printing AHCI registersIru Cai
According to datasheets for Intel ICH/PCH, it works for chipsets from ICH7 to 9-series PCH, with PCI device address D31:F2. Change-Id: If1ddd7208108bda949b5a94894a7bf9e8bfe1e5f Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/15106 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-06-08inteltool: handle unsafe dumping of graphics registersStefan Tauner
The current implementation from Vladimir simply dumps 1 MB of memory contents starting at the base address of the second PCI device (which most likely is the VGA controller on Intel systems). This locks up a number of different systems, e.g. my Ibex Peak-based T410s. This patch documents the issue and stops dumping the graphics registers for the -a/--all parameter. Change-Id: I581bdc63db60afaf4792bc11fbeed73aab57f63a Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/14627 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-05-13inteltool: update documentationStefan Tauner
- manpage - usage message - new warning message if -S is used on an unsupported chipset Change-Id: I1acaa5f4232b65244ec00fd22ec7460d9cc387f1 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/14624 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-01-13utils: Remove old license text from help & disclaimer fileMartin Roth
The license text that we decided to remove was removed from the headers of these files, but was still left in the help text. Remove it from those locations as well. Change-Id: I0e1b3b79f1afa35e632c4a4dd09a8bf2b02eaa6d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12913 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-07inteltool: add NetBSD compatibilityAndrey Korolyov
Tested on NetBSD-7.0/i386 Change-Id: I6a693633d3a80ea07ade233b1b4fd1c5a1412032 Signed-off-by: Andrey Korolyov <andrey@xdel.ru> Reviewed-on: https://review.coreboot.org/12835 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-11inteltool: Add function to generate SPD dump.Vladimir Serbinenko
E.g. on my MacbookAir to generate spd.bin to be used with coreboot I do: ./inteltool -S spd.bin Change-Id: If165475ed3e1f3262a8926ef619128d25b1e2896 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/11847 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2015-08-30inteltool: Add Intel 4-Series chipset detectionDamien Zammit
Previously, X4X was incorrectly named because it provides support for SKUs within XX4X range. This is renamed. This patch provides support for all X4X SKUs according to datasheet Intel 4 Series Chipset Family Specification Update, namely: Q45, Q43, P45, P43, G45, G43, G41 and B43 (both versions). Tested on Gigabyte GA-G41M-ES2L Change-Id: I032265e80d9ca51e2fef29201280832ea3210a0b Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/11245 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-05-25inteltool: dump gfx registers.Vladimir Serbinenko
Useful for autoport and other gfx-related developpement. Change-Id: I1fc0952bc30ab15cd39a4f0c00649714dcf318f3 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10276 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-05-16util/inteltool: add Broadwell-U supportMatt DeVillier
add handling of PCI IDs for Broadwell-U/Wildcat Point LP, using same functions as Haswell-U/Lynx Point LP Change-Id: I1094cbdace3c73f0f85c2e27c676b877b1a04bfe Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: http://review.coreboot.org/10209 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-03-26inteltool: add ICH8M-E supportLubomir Rintel
Tested on a Lenovo X61. Change-Id: I047f5a029d9be9fe6a000e2b45be44c7f14b33d7 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: http://review.coreboot.org/8568 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-08inteltool: add `-s` to dump spi bar and bios_cntl registersAlexander Couzens
Change-Id: I3bb5dc23885af8c992456ee5e4bd374cd4b813bf Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/8049 Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-16inteltool: Start adding Bay TrailMartin Roth
- Add silvermont (Bay Trail core) MSRs - these are shared with rangeley/avoton. - Add GPIO values and GPIO muxing information. - Add Bay Trail to the PM list. Still to do: - Northbridge functionality (RCBA, Memory timings, etc.) - Add Graphics registers Change-Id: I9fe0c0f1efe5f4344aeb3bad3f13037555109060 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7711 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-11-09inteltool: add more hardware IDs and PCIEXBAR/PXPEPBAR read supportFelix Held
Add IDs of some SNB and Haswell chips; use more descriptive names. Add PCIEXBAR and PXPEPBAR read support for SNB/IVB/Haswell. Change-Id: I16753bf90061fc2065b813b1c2169e7b7bcc89e8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: http://review.coreboot.org/7360 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Mathias Krause <minipli@googlemail.com>
2014-11-06inteltool: Fix message in case of multiple LPC controllersMathias Krause
If we find multiple LPC controllers, we want to tell the user that we'll ignore all but the first. However, we use 'dev' in the message (the current device found) instead of 'sb' (the one we want to use). Fix the message by using 'sb' and break the loop right away in this case. It's sufficient to tell the user once which LPC controller we'll use. Change-Id: Ibd27e40525fabe8c63b112691ad49fd994c70a48 Signed-off-by: Mathias Krause <minipli@googlemail.com> Reviewed-on: http://review.coreboot.org/7342 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-11-06inteltool: Add support for Sandy Bridge desktop processorsFelix Held
Change-Id: I5e68b89c30d5550e4bce5c3e4c7b0689c38756bc Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: http://review.coreboot.org/7337 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Mathias Krause <minipli@googlemail.com>
2014-11-04inteltool: Add support for Haswell ULT and Lynx Point LPDennis Wassenberg
Signed-off-by: Dennis Wassenberg <dennis.wassenberg@secunet.com> Change-Id: I2d5a31c831afeb92522b2673fde82922dc4efca5 Reviewed-on: http://review.coreboot.org/7275 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2014-08-26util/inteltool: fix typoIdwer Vollering
Change-Id: I8c30742f6cd759dce4c9641edad107d9e3154975 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/6766 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-11util/inteltool: Add pci ids for 4 northbridge models instead of 1.Damien Zammit
This patch supports northbridges: 0x0150 0x0154 0x0158 0x015c as 3rd gen core. Tested on 0x0150 (0x0154 previously only model). Change-Id: I53a33d864494dd4ac1cb9e8330450f56001ed92c Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/5873 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-07-23inteltool: Print raw CPUID and make hexadecimal values unambiguousDamien Zammit
The raw CPUID is useful for matching the directories under 'src/cpu/intel' and is not easy to find out otherwise because it is most often decoded already. The decoded values are not obviously hexadecimal so prepend them with 0x to make sure they are unambiguous. The output differences look like this: - CPU: Processor Type: 0, Family 6, Model 25, Stepping 2 + CPU: ID 0x20652, Processor Type 0x0, Family 0x6, Model 0x25, Stepping 0x2 Change-Id: Id47f0b00f8db931f0000451c8f63ac1e966442c4 Signed-off-by: Damien Zammit <damien@zamaudio.com> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3788 Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at> Tested-by: build bot (Jenkins)
2013-06-23inteltool: add initial support for NehalemStefan Tauner
Also, add pretty printing of Westmere's DMI registers (tested on my t410s by staring at non-zero output values :) Apparently Nehalem does not have a MEMBAR? But there are some documented memory controller control registers in PCI configuration space... left out for now. The PCIEXBAR is not documented publicly AFAICT, but there is a similar register on a device on bus 0xFF. phcoder might know more... Change-Id: I5faadb6e4f701728f5290276c02809b4993bd86d Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: http://review.coreboot.org/3505 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-13util/inteltool: Add support for other 5 chipsetsStefan Tauner
e4e8e090fa36cb3a098e1ddf0ea44c796c140572 does add support for QM57, but there are many more that should work with that code(?). Does not explode on... CPU: Processor Type: 0, Family 6, Model 25, Stepping 2 Northbridge: 8086:0044 (1st generation (Westmere family) Core Processor) Southbridge: 8086:3b0f (QS57) Change-Id: I85e15ba45678a5bd635415a7a8d69c05bff8f7ef Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: http://review.coreboot.org/3321 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-04-08inteltool: remove unused file descriptor variable and ifdefsStefan Tauner
Change-Id: I6a119b1f362f481914377e8d14c713159f895130 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: http://review.coreboot.org/3030 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-01inteltool: Add option to show differences in GPIO setupNico Huber
This adds an option -G, --gpio-diffs to inteltool, which shows GPIO settings that differ from platform defaults. For differing registers, the current, the default, and an xor of the default and the current value is printed. A follow-up commit will add defaults for the Cougar/Panther Point platform controller hubs. If you specify both, -g and -G on the command line, all GPIO registers will be printed interleaved with the diff. Here's a preview: $ ./inteltool -G CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9 Northbridge: 8086:0150 (unknown) Southbridge: 8086:1e4a (H77) ========== GPIO DIFFS =========== GPIOBASE = 0x0500 (IO) gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL) gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL) gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF gpiobase+0x000c: 0xe1f17f7e (GP_LVL) gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF gpiobase+0x002c: 0x00002000 (GPI_INV) gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2) gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2) gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF gpiobase+0x0038: 0xb65e7f4f (GP_LVL2) gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3) gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3) gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF gpiobase+0x0048: 0x00000dfc (GPIO_LVL3) gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF gpiobase+0x0060: 0x00000000 (GP_RST_SEL1) gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF $ ./inteltool -gG CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9 Northbridge: 8086:0150 (unknown) Southbridge: 8086:1e4a (H77) ============= GPIOS ============= GPIOBASE = 0x0500 (IO) gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL) gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL) gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF gpiobase+0x0008: 0x00000000 (RESERVED) gpiobase+0x000c: 0xe1f17f7e (GP_LVL) gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF gpiobase+0x0010: 0x00000000 (RESERVED) gpiobase+0x0014: 0x00000000 (RESERVED) gpiobase+0x0018: 0x00040000 (GPO_BLINK) gpiobase+0x001c: 0x00000000 (GP_SER_BLINK) gpiobase+0x0020: 0x00080000 (GP_SB_CMDSTS) gpiobase+0x0024: 0x00000000 (GP_SB_DATA) gpiobase+0x0028: 0x0000 (GPI_NMI_EN) gpiobase+0x002a: 0x0000 (GPI_NMI_STS) gpiobase+0x002c: 0x00002000 (GPI_INV) gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2) gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2) gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF gpiobase+0x0038: 0xb65e7f4f (GP_LVL2) gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF gpiobase+0x003c: 0x00000000 (RESERVED) gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3) gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3) gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF gpiobase+0x0048: 0x00000dfc (GPIO_LVL3) gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF gpiobase+0x004c: 0x00000000 (RESERVED) gpiobase+0x0050: 0x00000000 (RESERVED) gpiobase+0x0054: 0x00000000 (RESERVED) gpiobase+0x0058: 0x00000000 (RESERVED) gpiobase+0x005c: 0x00000000 (RESERVED) gpiobase+0x0060: 0x00000000 (GP_RST_SEL1) gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF gpiobase+0x0064: 0x00000000 (GP_RST_SEL2) gpiobase+0x0068: 0x00000000 (GP_RST_SEL3) gpiobase+0x006c: 0x00000000 (RESERVED) gpiobase+0x0070: 0x00000000 (RESERVED) gpiobase+0x0074: 0x00000000 (RESERVED) gpiobase+0x0078: 0x00000000 (RESERVED) gpiobase+0x007c: 0x00000000 (RESERVED) Change-Id: Ic77474c4bc0871e95103ddecd9f6a9406c8f016d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: http://review.coreboot.org/3000 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-29 11:46:49 +0000