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2020-03-16inteltool: add support for CannonPoint-LPMatt DeVillier
Add support for CannonPoint-LP U Premium (CoffeeLake-U and WhiskeyLake-U) GPIO info taken from: - Intel doc #337867-002 - coreboot soc/intel/cannonlake/include/soc/gpio_soc_defs.h Test: Read GPIOs from out-of-tree WhiskeyLake-U board Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: I70f23eec71abb8d7c2a7a109c9e760bb31dee2ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/39393 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16util/inteltool: Split GPIO community switch-case into its own functionJohanna Schander
So far printing the GPIO groups chose the community definition. As the list of supported platforms grows the massive switch case gets repetetive and hinders the readers view. It also reduces the ability to reuse the code in a potential libinteltool. To takle these issues the detection logic was split into its own function. Change-Id: I215c1b7d6ec164b8afd9489ebd54b63d3df50cb9 Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38631 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16util/inteltool: Move Denverton definitions into their own headerJohanna Schander
So far all group and community definitions live in one big c file. This 2500 line file slowly grows to a size, where readability is lost. Also the definitions are not reusable in a potential libinteltool. This commit moved the Denverton definitions into its own header. Change-Id: I6ce672c24059b9f3a4a984766184066f14df3013 Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38630 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christoph Pomaska <github@slrie.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16util/inteltool: Move Lewisburg definitions into their own headerJohanna Schander
So far all group and community definitions live in one big c file. This 2500 line file slowly grows to a size, where readability is lost. Also the definitions are not reusable in a potential libinteltool. This commit moves the Lewisburg definitions into its own header. Change-Id: I7900f1d8b3ca022112874ac2fa7326d538166008 Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38629 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christoph Pomaska <github@slrie.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16util/inteltool: Move Sunrise Point (LP) definitions into their own headerJohanna Schander
So far all group and community definitions live in one big c file. This 2500 line file slowly grows to a size, where readability is lost. Also the definitions are not reusable in a potential libinteltool. This commit moves the Sunrise Point and Sunrise Point LP definitions into its own header. Change-Id: I06efbee700f1525770365428fb85ef700ac53b80 Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38628 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christoph Pomaska <github@slrie.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16util/inteltool: Move Apollo Lake definitions into their own headerJohanna Schander
So far all group and community definitions live in one big c file. This 2500 line file slowly grows to a size, where readability is lost. Also the definitions are not reusable in a potential libinteltool. This commit moves the Apollo Lake definitions into its own header. Change-Id: I44b21092f5495f758c1f2151a913c074dfc658f5 Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38627 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christoph Pomaska <github@slrie.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16util/inteltool: Move Cannon Lake definitions into their own headerJohanna Schander
So far all group and community definitions live in one big c file. This 2500 line file slowly grows to a size, where readability is lost. Also the definitions are not reusable in a potential libinteltool. This commit moves the Cannon Lake definitions into its own header. Change-Id: I5991c3cebba0e05504940ae66fa7bb63bf280ab1 Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38626 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christoph Pomaska <github@slrie.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16util/inteltool: Move Ice Lake definitions into their own headerJohanna Schander
So far all group and community definitions live in one big c file. This 2500 line file slowly grows to a size, where readability is lost. Also the definitions are not reusable in a potential libinteltool. This commit moves the Ice Lake definitions into its own header. Change-Id: I5735f12480091a9b6c5e5c103a1ca7b7b1f3f997 Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38625 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christoph Pomaska <github@slrie.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16Revert "crossgcc: Upgrade GCC to 9.2.0"Patrick Rudolph
Revert the upgrade as it breaks at least the devicetree parser on aarch64, tested on qemu aarch64 target. This reverts commit dfd3f211740be4cf0d234bf4621ac384758a24ce. Change-Id: I65607817188db21533014caa6d15be9a2004d498 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-16util/crossgcc: Temporarily disable GDB build test on serverMartin Roth
The latest debian builder image doesn't compile GDB correctly. Disable the build test until I can get it working again. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I7852a39ed40a7364d24d0bbf014fd25058491083 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39575 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16util/inteltool: add 6th gen. mobile core u/y seriesMichael Niewöhner
This adds the 6th gen. mobile core u/y series. Change-Id: I7d802452353afe568e3880765dcd340f0437b392 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39568 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15util/inteltool: powermgt: rename variable for consistencyMichael Niewöhner
Rename size variable for consistency with the other subsystems. Change-Id: I9407193ac9e34685362619cfd45384156e2385c3 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39507 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15util/inteltool: powermgt: initialize register size variablesMichael Niewöhner
Initialize register size variables to prevent segfaults. Change-Id: Ib89bf6f7c7582efdea1c54d1316ed8f33a87cfcc Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39513 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15treewide: Replace uses of "Nehalem"Angel Pons
The code in coreboot is actually for the Arrandale processors, which are a MCM (Multi-Chip Module) with two different dies: - Hillel: 32nm Westmere dual-core CPU - Ironlake: 45nm northbridge with integrated graphics This has nothing to do with the older, single-die Nehalem processors. Therefore, replace the references to Nehalem with the correct names. Change-Id: I8c10a2618c519d2411211b9b8f66d24f0018f908 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38942 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15nb/intel/nehalem: Rename to ironlakeAngel Pons
The code is for Arrandale CPUs, whose System Agent is Ironlake. This change simply replaces `nehalem` with `ironlake` and `NEHALEM` with `IRONLAKE`. The remaining `Nehalem` cases are handled later, as changing some of them would impact the resulting binary. Tested with BUILD_TIMELESS=1 without adding the configuration options into the binary, and packardbell/ms2290 does not change. Change-Id: I8eb96eeb5e69f49150d47793b33e87b650c64acc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38941 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15util/inteltool: powermgt: drop dead codeMichael Niewöhner
Drop dummy entry. Change-Id: I1257115bd73fe90c6435116c8705cb5c98d945e1 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39559 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15util/inteltool: gpio: drop dead codeMichael Niewöhner
Drop dummy entry. Change-Id: Ic2184453c628c034e40ba877791fab4b7fe1d934 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39558 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-14coreboot: add Volteer template filesPaul Fagerburg
Add template files for making a new barebones-copy of Volteer. BUG=b:147483699 BRANCH=None TEST=N/A Change-Id: I8cc69b8ce7dbc6809de058019bdc466a060069e7 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-03-10util/scripts/ucode_h_to_bin.sh: Accept microcode in INC formatBartek Pastudzki
Intel supplies microcode (at least for MinnowBoard) in Intel Assembly *.inc format rather than C header. This change allow to pass in configuration directory with *.inc files rather than list of *.h files. Change-Id: I3c716e5ad42e55ab3a3a67de1e9bf10e58855540 Signed-off-by: Bartek Pastudzki <Bartek.Pastudzki@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/25546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-10util/nvramtool: fix building on OpenBSDEvgeny Zinoviev
OpenBSD's gcc 4.2.1 doesn't know about _Noreturn Change-Id: Ie9e1885c483941d3d0ce8c8948af53f1ef8bb5db Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-10util/board_status: Add support of CMOS values dumpEvgeny Zinoviev
Change-Id: I89f9a0e9622557b01dda52378f8f1323777bce39 Signed-off-by: Evgeny Zinoviev <me@ch1p.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/28565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-10abuild: Always build the default configNico Huber
Abuild allows us to add config files below `configs/` for each mainboard. So far, these were built instead of the default config. However, that allows to hide errors in the default config. Hence, we should build that too in any case. Change-Id: I94075dbaa6fabeb75bdbc92e56f237df80c15cef Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39382 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-093rdparty/libgfxinit: Update submodule pointerNico Huber
Changes allow to use the integrated panel logic (power sequen- cing and backlight control) for more connectors. The Kconfigs GFX_GMA_PANEL_1_PORT and GFX_GMA_PANEL_2_PORT can now be set to any port, e.g. config GFX_GMA_PANEL_1_PORT default "DP3" Now that the panel logic is not tied to the `Internal` port choice anymore, we can properly split it into `LVDS` and `eDP`. This also adds Comet Lake PCI IDs which should still work the same as Kaby and Coffee Lake. Change-Id: I78b1b458ca00714dcbe7753a7beb4fb05d69986b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38921 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-09util/superiotool: Drop one SCH5317 entryAngel Pons
The SCH5317 can have either 0x85 or 0x8c as device ID. However, the former results in false positives on any ITE IT85xx series embedded controller, which has led some people to think that chip was actually in their laptops. Moreover, there is no register dump for the SCH5317. Since nobody has touched this in over a decade, avoid further confusion by dropping the misleading definition. Change-Id: I4d1d34d1b88b878461499e52f1a916ee1e33210d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-08util/kconfig: Silence warning about _GNU_SOURCEAngel Pons
For some reason, this symbol gets redefined, which causes a warning. Hide the warning by checking whether it is already defined. Change-Id: I70ffc9a799e0b536d6aba7d00f828bd6d915d94c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-07util/scripts/gerrit-rebase: Improve error messagePatrick Georgi
I received feedback that people were confused by "Error: foo", so replace it with something more user friendly that serves the same purpose. Change-Id: I17b902a62020109e079437c8d9ffd7ea5979a3a1 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-06util/autoport: Remove redundant commentAngel Pons
Nobody needs "LPC bridge PCI-LPC bridge". Change-Id: Iac833d4fa34b00d89bdfc9aeb06a96583840b900 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-06src/arch/x86: Convert to SPDX license headerPatrick Georgi
This also drops individual copyright notices, all mentioned authors in that part of the tree are listed in AUTHORS. Change-Id: Ib5a92bb46ff2b9d2928aae3763daec71747044c2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-03-06src/arch/riscv: Convert to SPDX license headerPatrick Georgi
This also drops individual copyright notices, all mentioned authors in that part of the tree are listed in AUTHORS. Change-Id: I770c1afd9b68a40ec0e69818f24b5ef3ad4f1d35 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-03-06util/lint: Add BSD-4-Clause-UC to acceptable licensesPatrick Georgi
While a 4 clause BSD license "with advertising" is incompatible to the GPL, the University of California declared the problematic clause null and void. See ftp://ftp.cs.berkeley.edu/pub/4bsd/README.Impt.License.Change Change-Id: I4ebb822f64989a5fc8f686e548a94653508d1113 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-06src/arch/ppc64: Convert to SPDX license headerPatrick Georgi
This also drops individual copyright notices, all mentioned authors in that part of the tree are already listed in AUTHORS. Change-Id: I19b1c379b474dd011e2d0f8c8202ff1351c9290d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-06src/arch/arm64: Convert to SPDX license headerPatrick Georgi
This also drops individual copyright notices, all mentioned authors in that part of the tree are already listed in AUTHORS. Change-Id: Ic5eddc961d015328e5a90994b7963e7af83cddd3 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-06src/arch/arm: Convert to SPDX license headerPatrick Georgi
This also drops individual copyright notices, all mentioned authors in that part of the tree are already listed in AUTHORS. Change-Id: Ic2bab77edaf7ad97b7f3278cb108226a18cf3791 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-03-04util/lint: use env to locate the bash binaryIdwer Vollering
Otherwise there will, after make gitconfig, be (hidden) shell command failures with 'git commit -s': gmake: util/lint/check-style: Command not found gmake: *** [Makefile.inc:632: check-style] Error 127 Change-Id: I3891dee53702ee10e5e44dae408193e49d7a89f1 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38227 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-04util/gitconfig: Fix commit-msg for BSD grepPatrick Elsen
BSD grep (on macOS) doesn't like repeated repetition operators, it throws the error grep: repetition-operator operand invalid This removes the superfluous repetition operator to make the commit-msg hook work on macOS and other platforms not using GNU grep. Change-Id: Id0f57d0f14634f7844b889d71342b2982fcadeb2 Signed-off-by: Patrick Elsen <pelsen@xfbs.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-04util: Remove viatoolAngel Pons
It somehow creeps into `make clean`, but is not used at all. Since no VIA platform remains in coreboot, drop the utility as well. Change-Id: Ia7e11379a6db650b5190a056226a9101c2be7dec Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-03util/chromeos: Add unzip as a dependencyMete Balci
unzip might not be installed by default, so it is added as a dependency in crosfirmware script. Change-Id: I420067b3e8ed26e6a7dccb863aae1272a3c7acbc Signed-off-by: Mete Balci <metebalci@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-03util/ifdtool: add --output flagMarcello Sylvester Bauer
Add an optional commandline flag to define the filename of the resulting output file. If this flag is not defined, it will behave like before by using the old filename with a ".new" suffix. With this additional flag it is not necessary to move the output file at build-time, and the stdout print "Writing new image to <filename>" makes more sense in the build context. Change-Id: I824e94e93749f55c3576e4ee2f7804d855fefed2 Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-03-03LGA1155 mainboards: Remove gfx.did and gfx.ndidAngel Pons
They are downright useless and result in ACPI errors. So, burn them. Also, do a minor update to autoport's README about these values. Change-Id: Idb5832cfd2e3043b8d70e13cbbe8bd94ad613120 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-03-02util/amdfwtool: Clarify APOB NV requirementsMarshall Dawson
Relocate the first size check. This was automatically continuing and not looking for the caller incorrectly passing a destination. New information indicates that the APOB_NV should always be present in the system. Augment the missing size check to inferring whether a missing size is valid, as in the case of older products, or truly missing when it's needed. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I51f5333de4392dec1478bd84563c053a508b9e9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-03-02lint/lint-extended-007-checkpatch: Fix obsolete pathsElyes HAOUAS
Change-Id: I7a6ca083e79d285b8c596631f21ccdfe2777e20e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-02lint/check_lint_tests: Fix obsolete pathsElyes HAOUAS
Change-Id: Ieac6e5ba0d425f873c3d4125d828224313017b69 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-02lz4: Fix out-of-bounds readsAlex Rebert
Fix two out-of-bounds reads in lz4 decompression: 1) LZ4_decompress_generic could read one byte past the input buffer when decoding variable length literals due to a missing bounds check. This issue was resolved in libpayload, commonlib and cbfstool 2) ulz4fn could read up to 4 bytes past the input buffer when reading a lz4_block_header due to a missing bounds check. This issue was resolved in libpayload and commonlib. Change-Id: I5afdf7e1d43ecdb06c7b288be46813c1017569fc Signed-off-by: Alex Rebert <alexandre.rebert@gmail.com> Found-by: Mayhem Reviewed-on: https://review.coreboot.org/c/coreboot/+/39174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-26Get rid of ROMCCElyes HAOUAS
Change-Id: Ib9816f6a4e064a82e81ca68a1906b1107a2abda3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-26treewide: capitalize 'USB'Elyes HAOUAS
Change-Id: I7650786ea50465a4c2d11de948fdb81f4e509772 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39100 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-26crossgcc: Upgrade GCC to 9.2.0Elyes HAOUAS
nds32 and GNAT bad constant patches are integrated in upstream so we don't need them anymore. Change-Id: Id6f65548764654ae5539ac3c835853ea2fa1c5e0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32564 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24util: Remove old reference to ROMCCElyes HAOUAS
Change-Id: Ia1a37db8341281102ae8ae9c03f1ce76d8d126eb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39075 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24xcompile: Use GCC wrappers for ar, nmJacob Garber
When compiling with GCC, use the special wrappers around ar and nm that provide the path to the plugin they need to understand LTO object files. These wrappers forward all other functionality to the underlying programs, so they should otherwise be equivalent. Change-Id: Ibdae4faabf67bf6a4bb8c38970f6189646ee74b3 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38290 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24treewide: Capitalize 'CMOS'Elyes HAOUAS
Change-Id: I1d36e554618498d70f33f6c425b0abc91d4fb952 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38928 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Peter Lemenkov <lemenkov@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24util/inteltool: Add missing entry for WPT-LP PremiumAngel Pons
Tested on a laptop with an i7-5500U processor, the device is now found. Change-Id: I49ddec862520d0d5492d78fec89efd841c141790 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-25 04:55:57 +0000