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2019-02-22intelvbttool: Add support for reading vbt from sysfsAlex Feinman
VBT on Intel(R) systems is available via sysfs as /sys/kernel/debug/dri/0/i915_vbt However the size of this file reads as 0 causing intelvbttool to fail. This patch implements incremental reads with realloc for such cases or whenever the file size is not available (e.g. reading from stdin). After this patch is applied, intelvbttool can be used as follows: sudo intelvbttool -f /sys/kernel/debug/dri/0/i915_vbt -d Change-Id: I5d17095a5747550b7115a54a7619b7294a846196 Signed-off-by: Alex Feinman <alexfeinman@hotmail.com> Reviewed-on: https://review.coreboot.org/c/31531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-21ACPI: Correct asl_compiler_revision valueElyes HAOUAS
Change-Id: I91b54b43c8bb5cb17ff86a6d9afa95f265ee49df Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-21SMBIOS: Fix bios versionElyes HAOUAS
Change-Id: I142f08ed3c2704b8fde6d176f23772f5d6b33e85 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-20util/lint: Exclude util/inteltool from checkpatchNico Huber
It's causing too much noise during review of register tables. Change-Id: Iae6cd4454c5ed84b5fe0ea5f8a244e2a2fa13407 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/31367 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-18crossgcc: Update MPFR to version 4.0.2Elyes HAOUAS
Change-Id: I5569e61c2a3a64cf353afe3195eca82709362305 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31218 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-15crossgcc: Update binutils to version 2.32Elyes HAOUAS
Change-Id: I943863587dff6db72d12673bc30ea46f4fd4b66f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-14util/ifdtools: Make EC region readable to BIOS/CPUBora Guvendik
Allow EC region to be readable by BIOS/CPU so that flashrom can read it. BUG=b:123199222 TEST=Build coreboot with CONFIG_LOCK_MANAGEMENT_ENGINE set, run firmware_LockedME test. Change-Id: I306c74a0893355e57632a22a712b1f4fdaa19306 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/31377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-02-06Makefile.inc: Create a default SMMSTORE regionArthur Heymans
Change-Id: I7b7b75050e0139ea9a0a4f2ad3c0d69a482fb38b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-06Makefile.inc: Optimize generating the default x86 fmapArthur Heymans
Put the FMAP FMAP region right above the coreboot CBFS region. The other regions like RW_MRC_CACHE and CONSOLE often have alignment requirements so it makes sense to put those on top. This also simplifies the code the generate the default fmap a little. Change-Id: I24fa6c89ecf85fb9002c0357f14aa970ee51b1df Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30419 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-01cbmem: use aligned_memcpy for reading cbmem address informationAaron Durbin
The coreboot table entry containing the memory entries can have fields unnaturally aligned in memory. Therefore one needs to perform an aligned_memcpy() so that it doesn't cause faults on certain architectures that assume naturally aligned accesses. BUG=chromium:925961 Change-Id: I28365b204962ac89d65d046076d862b6f9374c06 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/31181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Manoj Gupta <manojgupta@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-01-29util/docker: Update container for doc.coreboot.orgPatrick Georgi
Now running 1.8.3, with a fix to the theme so search still works, and a recommonmark version that properly rewrites links to .md files. Change-Id: Ice25554c77a398a71782c8d1cb9e205debd80d67 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/31129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-01-29util/ifdtools: Consider EC region accessLijian Zhao
Version 2 IFD will have flmstr5 as EC region access control, consider it during descriptor lock/unlock process. BUG=N/A TEST=Build coreboot with CONFIG_LOCK_MANAGEMENT_ENGINE set, and check flmstr5 value by hexdump the SPI image at offset FMBA+0x90. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I970064dcf6114a15f054ab7c44349841deb99dc8 Reviewed-on: https://review.coreboot.org/c/31111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-01-29util/ifdtool: Add lock support for CNL and ICLLijian Zhao
Cannonlake and Icelake have same read/write region permission settings with skylake and kabylake, so add it here as well. BUG=b:123199222 TEST=Turn on CONFIG_LOCK_MANAGEMENT_ENGINE and build image, check the setting matches 0x0D for read and 0x04 for write. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I71d8b815c7dff7dcbcff2bf77c85ebf80b8df6d2 Reviewed-on: https://review.coreboot.org/c/31104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-01-26Revert "util/bincfg: code cleanup: convert sym_table to a local variable"Angel Pons
This reverts commit 48c24ce5eefe64b1aa82237f0a4be2772c686ef6. Reason for revert: Commit broke bincfg, and sym_table as a global variable is less bad than passing it around in function calls. Change-Id: Ib8d64a1dc201d17a4e278ab0114958b6807a45ac Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/31105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-26crossgcc: Update CMake to version 3.13.3Elyes HAOUAS
Change-Id: If3bd670e2273715b6996e2ca78a0b9c412bfd220 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-26util/crossgcc: Update to binutils 2.31.1 and gcc 8.2Patrick Georgi
Change-Id: Icf7c6bdd4021bf84cc295c819f93838248e0f4c7 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/31089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-01-25util/superiotool: detect Fintek F81866, F8196*Kyle Stevenson
F81866 detection tested with the iBASE SI-613: superiotool r4.9-420-g034e5e6 Found Fintek F81866 (vid=0x3419, id=0x1010) at 0x4e F8196* detection is based on chip IDs provided by iBASE, but untested. Change-Id: I7210e1523a188a8593cd03547bb0c95cd3e7aa39 Signed-off-by: Kyle Stevenson <kstevenson@comqi.com> Reviewed-on: https://review.coreboot.org/c/31052 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24util/lint: update non-ascii linter checking rulesMartin Roth
- Check non-external payloads - Remove directories that aren't in the coreboot git repo. - Remove non-phrase rule from list of excluded phrases Change-Id: I9e056e8b43af567f102dfc0db76f60328aa1ed04 Signed-off-by: Martin Roth <martinr@coreboot.org> Reviewed-on: https://review.coreboot.org/c/28449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-01-24util/kconfig: Add `toada` Ada spec generation toolNico Huber
Converts `auto.conf` to an Ada spec file. Write to $(obj)/cb-config.ads and set the package name to `CB.Config`. Change-Id: I97c060d8a613c74a82a18aff9524ad4b01f9df56 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/31053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-24cpu/intel/model_206ax: Remove the notion of socketsArthur Heymans
With the memory controller the separate sockets becomes a useless distinction. They all used the same code anyway. UNTESTED: This also updates autoport. Change-Id: I044d434a5b8fca75db9eb193c7ffc60f3c78212b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/31031 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23util/lint: Update non-ascii linter for FreeBSDMartin Roth
On FreeBSD, this test was failing with the error: "grep: Argument list too long" - Remove support for testing coreboot not in a git repo. Many of the other linters already don't support this. - Use git grep to find offending files, then xargs to print out the lines. Change-Id: Ic017dc3465fd9a46ff4e6ec5ef16396e963483cd Signed-off-by: Martin Roth <martinr@coreboot.org> Reviewed-on: https://review.coreboot.org/c/28448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-01-22util/crossgcc: use fixed length version string.Wonkyu Kim
After merging util/crossgcc: derive date and version from latest commit (https://review.coreboot.org/c/coreboot/+/30804), crossgcc build is broken in internal repository due to long version name;coreboot.org repository is ok because it uses short tag name. The patch uses "git describe" which is dependent on git tag name. If tag name is little bit long, it can cause crossgcc build failed. To avoid this issue, use only short version of hash string which is fixed length. And it's enough as version string, because we also use date(CROSSGCC_DATE) together. TEST=Build crossgcc in both coreboot.org and internal repository which uses longer tag name and check version string in build log. Change-Id: I405b2e4e5c05831c25aebf1c73a281adab8ef452 Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-on: https://review.coreboot.org/c/31001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-21util/inteltool: Add support for DenvertonThomas Heijligen
Used documents: - C3000 Product Family Datasheet Change-Id: I54d09c78e1cce84b63300dfc0aa1bb374bb7faae Co-authored-by: Felix Singer <migy@darmstadt.ccc.de> Signed-off-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-on: https://review.coreboot.org/c/30887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-20util/autoport: Make dsdt.asl prettierAngel Pons
Small cosmetic changes which fix aesthetic inaccuracies. Change-Id: I8fef4bbe12b283cee2ab8d078de950171757bbfe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/30971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2019-01-18util/autoport: Fix include styleAngel Pons
Change-Id: If0dfee38bd82b3c8e9b5173e520cb244787c0a9a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/30970 Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-18util/autoport: Break very long lineAngel Pons
Change-Id: Id45b0970a457ad4a724b71b4887ce4a1332596be Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/30968 Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-18util/autoport: Correct DSDT include statementAngel Pons
With commit aaced4a (cpu/intel/common: Use a common acpi/cpu.asl file), some model_206ax code was moved to a common place. However, autoport was not updated accordingly. Change-Id: I51b7e9c5d226f591596c33d6a3cb326a34420493 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/30967 Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-15autoport: move the generated gnvs.c to acpi_tables.cIru Cai
Change-Id: I8f6eea579f69060608639b1c50255acd8ab5a4a2 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/30889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-15util/superiotool: Add ITE8528Patrick Rudolph
Add ITE8528 which can be found on the wedge100s. Most registers are dumped from hardware. No datasheet is publicy available. Change-Id: I24b12c0032157a4959336f8b51dadbe7b2e09d66 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/30801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-14[RFC]util/checklist: Remove this functionalityArthur Heymans
It was only hooked up for galileo board when using the obsolete FSP1.1. I don't see how it can be useful... Change-Id: Ifd7cbd664cfa3b729a11c885134fd9b5de62a96c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30691 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-11util/crossgcc: derive date and version from latest commitPatrick Georgi
This way date and version are automatically updated when util/crossgcc was changed, the version contains the commit ID and we have less churn on these variables. Change-Id: I475ba9578a8bb421d7c342d2569d7de7fcf4161d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/30804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-01-10crossgcc: Update acpica to version 20190108Elyes HAOUAS
changes in this version: https://acpica.org/node/164 Change-Id: Iff7fb6990f69f658c41ec115a3383ec902d8300f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-07crossgcc: Update Python to version 3.7.2Elyes HAOUAS
Change-Id: Ie0b3d31ba116314308d4fcc36a19587370fff7cc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30560 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-06util/ifdtool: Fix regions_collide() checkNico Huber
The old version was unnecessarily complex and allowed one region to include the other. Change-Id: Ibf7faf8103c8945b82c3962b5a7b82c3288b871f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/30673 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-05crossgcc: Update CMake to version 3.13.2Elyes HAOUAS
Change-Id: Ifd9e82d564e4e49194ac48786fd233cbf97a55c5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-05crossgcc: Update GDB to version 8.2.1Elyes HAOUAS
Change-Id: I454843dcabe7e3fa4b13dd58ce81ba9f25b5a432 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-05crossgcc: Update LLVM to 7.0.1Elyes HAOUAS
Change-Id: I7d88f0c36a254d8b2e3e76f632f46f0d2a4ad6f8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-05util/inteltool: fix PCR init of Sunrise Point-LP devicesShaleen Jain
Fixes getting a dump of GPIO registers for these devices. Change-Id: I80f05a170152969ba45d6aee33ab7ed5296ee496 Signed-off-by: Shaleen Jain <shaleen@jain.sh> Reviewed-on: https://review.coreboot.org/c/30604 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-04crossgcc: Update acpica and Expat versionsElyes HAOUAS
Update: * acpica to version 20181213 changes in this version: https://acpica.org/node/163 * Expat to version 2.2.6 changes in this version: https://github.com/libexpat/libexpat/blob/R_2_2_6/expat/Changes Change-Id: Ib67cf26497a0c2c2a364741675b13e4ce0190e41 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-04util/superiotool: Add ITE IT8786E-IKyösti Mälkki
Based on IT8786E-I V0.4.1 datasheet with following remark: "Please note that the IT8786E-I V0.4.1 is applicable only to the D version." Signed-off-by: Kyösti Mälkki <kyosti.malkki@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ibf6e290abb01ae1b6b28173a83e88d1d99663ad4 Reviewed-on: https://review.coreboot.org/c/30334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-04util/autoport/readme.md: Correct minor inconsistencyAngel Pons
Commit a5072af67d85 ("util/autoport: Use romstage.c instead of early_southbridge.c") changed where the SPD map is. Reflect that. Change-Id: Id0bd1778617371bac5921c4eae63d0beb088216c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/30655 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-04util/gitconfig/pre-commit: Use clang-format to sanitise commitsEdward O'Callaghan
Use the `git-format' tool to sanitise coreboot commits such that they conform to coreboot's coding style. This fancy piece of machinary allows one to have LibFormat from Clang to automatically check your commit conforms to coreboot's coding style, fix any issues automatically and provides you a diff you may review and apply at your convenience. N.B. When the `clang-format' binary is not found we issue a warning that the test was skipped and carry on as usual. Hence, this is strictly non-enforcing at this current time. You may use it at your leisure. Change-Id: If49017ea82f0707efd47cae5978a286a9af8f3b7 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: https://review.coreboot.org/c/8037 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-04crossgcc: Update acpica to 20180927Stefan Reinauer
Update to latest version of iasl: (From the acpica.org changelogs) * Fixed a regression introduced in version 20180927 that could cause the compiler to fault, especially with NamePaths containing one or more carats (^). Such as: ^^_SB_PCI0 * Added a new remark for the Sleep() operator when the sleep time operand is larger than one second. This is a very long time for the ASL/BIOS code and may not be what was intended by the ASL writer. * Implemented detection of extraneous/redundant uses of the Offset() operator within a Field Unit list. A remark is now issued for these. For example, the first two of the Offset() operators below are extraneous. Because both the compiler and the interpreter track the offsets automatically, these Offsets simply refer to the current offset and are unnecessary. Note, when optimization is enabled, the iASL compiler will in fact remove the redundant Offset operators and will not emit any AML code for them. Change-Id: I46a1b1be44328aa2172f4741e9fd0c9b0f4e0430 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/c/28944 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-04crossgcc: Update software versionsStefan Reinauer
Update toolchain to the following software versions: o Python 3.5.1 -> 3.7.0 o LLVM 6.0.0 -> 7.0.0 o Expat 2.2.1 -> 2.2.5 o MPC 1.0.3 -> 1.1.0 o MPFR 3.1.5 -> 4.0.1 Change-Id: I66c6138c7b65c73a89b3cf980bb08950d8fffe6a Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/c/28887 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-03util/chromeos/crosfirmware.sh: Print more messagesTristan Corrick
The existing code has several messages that are only printed when the DEBUG variable is set. These messages are not verbose, and are quite useful to see how the script is progressing. So, print them unconditionally. Change-Id: I8f78e4563f0b4a42f831194a6e526284c2fbcd92 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-03util/chromeos/crosfirmware.sh: Check for dependenciesTristan Corrick
crosfirmware.sh has dependencies that might not be installed on some systems. If a dependency is missing, provide a clear message about the issue and how to resolve it. Change-Id: I265bd03666f1273d3c22b60aae860c48c758005b Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30549 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-03util/chromeos/crosfirmware.sh: Print download statusTristan Corrick
It's quite useful to know the download progress, as it can take a while even with a fast connection. For example, the peppy recovery image is ~600 MiB. It also lets the user know that disk space is being filled. Change-Id: I8c175f9095478ffe33c95b7ef9907c25b5f10f8c Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30548 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-03util/chromeos/crosfirmware.sh: Add /sbin to PATHTristan Corrick
On some systems, such as Debian 9.6, `parted` and `debugfs` are located in /sbin. Adding /sbin to PATH means that this script can work when run as a regular user. Change-Id: I151dba467e2b196f13093334273dae8a05865491 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-28util/xcompile/xcompile: Use tab for indentElyes HAOUAS
Change-Id: I9878e6d962004003e2c05a6cdb8ecb0a3a02ae66 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-28util/inteltool: Add support for Sunrise Point LPMatthew Garrett
Used documents: 334658 (Sunrise Point-LP I/O datasheet vol. 1) 334659 (Sunrise Point-LP I/O datasheet vol. 2) 332690 (Sunrise Point I/O datasheet vol. 1) Change-Id: I16237ffc9a225b46271f2a51d77a7f28dfc36138 Signed-off-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-on: https://review.coreboot.org/c/28623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 17:32:36 +0000