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Running the x86_64 qemu mainboard target with '-accel kvm' results in hang,
as the 'D' and 'A' bits needs to be set in read only page tables.
Tested on QEMU Q35: Boots into payload with '-accel kvm'.
Change-Id: I4beae8deec6bf34f9762e7b54c5da4e5b63f6d24
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36778
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I2867d62d2e6f5ca1e97ce52ecc45a794b4831686
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The ApolloLake SoC allows two Logical Boot Partitions. This patch
introduces a '-s' optional parameter to select the second Logical
Boot Partition.
Change-Id: If32ec11fc7291d52b821bf95c1e186690d06ba11
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37660
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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If the compiler fails to inline all the FORCE_INLINE functions, it will
complain.
Change-Id: I7b8349c9a3d53c47ac189f02b296600abac8a0cf
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37734
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit 547de69de73629c051e9b5312f6369744ec6ce8f.
Merged out of order before CB:36317. The conflicting use of
_ADR and _HID needs to be properly addressed before we can
bump the IASL version.
Change-Id: Iacbc9877a8ff2324eba4789d65df8545b8a25413
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37713
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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cbfstool depends on vboot headers, and vboot expects to be able to use
modern C features like _Static_assert(). It just so happens that it
doesn't do that in any headers included from cbfstool right now, but
that may change. Let's switch cbfstool to a newer version to prevent
that from becoming a problem.
Change-Id: I884e1bdf4ec21487ddb1bca57ef5dc2104cf8e0e
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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* GBB_HWID is no longer used in Hatch Kconfig, so remove the code
that creates the GBB_HWID and adds it to the Kconfig section
* Add more information in the usage message when the cmdline params
are incorrect.
* Remove messages that tell the user what to do, because the top-level
program that invokes this script will handle those commands, and so
this script telling the user what to do is noise (and possibly harmful)
* Add more information to the commit message that the script prepares
for the user.
* Bump script version number.
BRANCH=None
BUG=b:140261109
TEST=Create the "sushi" variant of the "hatch" baseboard:
`util/mainboard/google/hatch/create_coreboot_variant.sh sushi`
Inspect the files in src/mainboard/google/hatch/variants/sushi
Change-Id: I04e949aedce61ed7fc7df681b72c3cfef31b5513
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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For prettier diagrams: http://ditaa.sourceforge.net/
Change-Id: Ic28dc5ea9d82ff6bf8654e2e33e675a536348654
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Ife90b61d04e32f307a688d81922bdcf6fa57cfc9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37572
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I638eda3040c7225aa4a8b492c8dc78b0e2effba1
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37369
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Changes: https://acpica.org/node/174
Change-Id: I72e44429f96c2ec82092c87aea46c3ff80755d4c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I81fcb58720fb20ac4f57e31e9f991f5009aba568
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This eases maintenance of our kconfig fork.
Change-Id: Ia4bc0bf22e66457356b9f8fcbea9412792495bca
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: I35e6a5210340b8057db6d1cff597428fa8dd3cd1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Ib564217c4fdcb609fd6dfd4cb71288dd54ffe4bf
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Changes: https://github.com/libexpat/libexpat/blob/R_2_2_9/expat/Changes
Change-Id: I591e4ed186bc8d46ff64161eddc488b640cad5fc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I1265e7df4d6c04aa1ccf0c65dc87e62bec5a4a35
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I380ba8678b22483b0d9c5fc558c0e08fd38778e7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I3bb6055383aa72153fffc70adc9cc446e5a0612e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36013
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I4417c733b3915ad74d81d2e1e0904da06eea300e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36956
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The old logic only uses the type to identify resources, which makes a
resource in override tree overriding the first resource with the same
type (but possibly different index) in base tree, and resources with
same type (but again different index) in override tree overriding each
other.
Resources had better be identified with both their type and index.
Change-Id: I7cd88905a8d6d1c7c6c03833835df2fba83047ea
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37109
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I4963ab249a8e0b31c014e92edf1e0a4a4f638084
Signed-off-by: rkanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37111
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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* Binary strings should be joined with a binary string
* Binary files should be opened in binary mode.
* Division that wants truncation should make it explicit.
I have tested that these changes let me compile.
Change-Id: I7c41b80688a9c6bdb3c66561ff531311cc7ebb13
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37024
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Even with four cloc invocations it's faster than doing the rename
dance and messes up the tree less. It also opens up using cloc's git
mode to work on a git tree instead of a checkout.
Change-Id: I3ad8fc6802ecedb332359d00b28ea61c33ed2ea0
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: Ie323112d27d228849cca7894b9ebd3f4dedd2d9a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: I8e6ff5bc72618e782ed472878bd6ea294be1b5ca
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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We had two _very_ long lines containing arguments that enumerate the
paths where blobs are stored: Now there's a variable containing them.
Change-Id: I501b27158d00ba00d1c9b9e2f00a17a8b9c3f682
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36955
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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git clone allows using a local repo as reference which reduces the
required network traffic.
Change-Id: I64722cd5dbdfc0c2bcd935715cffdb99b773711c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36954
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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GPG 2 expects the GPG_TTY variable to be configured so
that it can properly ask for the passphrase. If it's
not already set, do so.
Change-Id: I7e145a492c9eceda40cc1a1e04452a78852042d1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36953
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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I thought gcc ignores -Wno-* stuff that it doesn't know about, but
apparently not.
Change-Id: If265a7bcdcfb5e83cc06b1f914dd6bab964eaca6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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The MIPS architecture port has been added 5+ years ago in order to
support a Chrome OS project that ended up going nowhere. No other board
has used it since and nobody is still willing or has the expertise and
hardware to maintain it. We have decided that it has become too much of
a mainenance burden and the chance of anyone ever reviving it seems too
slim at this point. This patch eliminates all MIPS code and
MIPS-specific hacks.
Change-Id: I5e49451cd055bbab0a15dcae5f53e0172e6e2ebe
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34919
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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After removing urara no board still uses this SoC, and there are no
plans to add any in the future (I'm not sure if the chip really exists
tbh...).
Change-Id: Ic4628fdfacc9fb19b6210394d96431fdb5f8e8f1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36491
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This uses less lines, is the original Markdown syntax, and for short
blocks better readable.
Change-Id: Id96ad0f65980dfb943eef3cde5626d56f97622f9
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35729
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Run
- make -C util/docker doc.coreboot.org to build the docker image
- make -C util/docker docker-build-docs to build the documentation
- make -C docker-livehtml-docs to serve autoupdated documentation over
http://0.0.0.0:8000
Change-Id: Ic07f216f8d90d6e212383250b852dc91575304c3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36104
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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With GCC 9.x has a new warning *address-of-packed-member*.
> -Waddress-of-packed-member
>
> Warn when the address of packed member of struct or union is
> taken, which usually results in an unaligned pointer value.
> This is enabled by default.
This results in the build errors below, for example, with GCC 9.2 from
Debian Sid/unstable.
src/southbridge/intel/common/spi.c: In function 'spi_init':
src/southbridge/intel/common/spi.c:298:19: error: taking address of packed member of 'struct ich7_spi_regs' may result in an unaligned pointer value [-Werror=address-of-packed-member]
298 | cntlr->optype = &ich7_spi->optype;
| ^~~~~~~~~~~~~~~~~
Therefore, explicitly disable the warning.
Change-Id: I01d0dcdd0f8252ab65b91f40bb5f5c5e8177a293
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36940
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds an optional pre-RAM cache for the FMAP which most
platforms should be able to use, complementing the recently added
post-RAM FMAP cache in CBMEM. vboot systems currently read the FMAP
about half a dozen times from flash in verstage, which will all be
coalesced into a single read with this patch. It will also help
future vboot improvements since when FMAP reads become "free" vboot
doesn't need to keep track of so much information separately.
In order to make sure we have a single, well-defined point where the new
cache is first initialized, eliminate the build-time hardcoding of the
CBFS section offsets, so that all CBFS accesses explicitly read the
FMAP.
Add FMAP_CACHEs to all platforms that can afford it (other than the
RISC-V things where I have no idea how they work), trying to take the
space from things that look like they were oversized anyway (pre-RAM
consoles and CBFS caches).
Change-Id: I2820436776ef620bdc4481b5cd4b6957764248ea
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Joel Kitching <kitching@google.com>
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CB:36385 makes dock init in ramstage fully mainboard-specific, so
keeping generating empty h8_mainboard_init_dock() for lenovo EC becomes
unnecessary and problematic.
Change-Id: I19f57f41403ffd0319cc86f21bec7e142095df83
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I9067a95ff171d6da58583b3d4f15596b4584d937
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add support for x86_64 bootblock on qemu.
Introduce a new approach to long mode support. The previous patch set
generated page tables at runtime and placed them in heap. The new
approach places the page tables in memory mapped ROM.
Introduce a new tool called pgtblgen that creates x86 long mode compatible
page tables and writes those to a file. The file is included into the CBFS
and placed at a predefined offset.
Add assembly code to load the page tables, based on a Kconfig symbol and
enter long in bootblock.
The code can be easily ported to real hardware bootblock.
Tested on qemu q35.
Change-Id: Iec92c6cea464c97c18a0811e2e91bc22133ace42
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I3f9672053dcf0a4462ef6ab718af4f18fcfa7e14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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* Add defines for GPIO_MEM_CONFIG_0:3 in the template file, so
that code that relies on these defines can compile. Because they
are preprocessor symbols, there is no way to define them as
__weak in the baseboard header and allow the variant to override
as needed, so they need to be defined here and changed if needed.
* Add a version number for the script and an "auto-generated by"
line in the git commit message.
* Change the branch name so that it's not the same as the ones
that the other scripts will create, so that repo upload on those
CLs won't affect this one.
BUG=b:140261109
BRANCH=None
TEST=Create and build the "sushi" variant:
$ util/mainboard/google/hatch/create_coreboot_variant.sh sushi
$ util/abuild/abuild -p none -t google/hatch -x -a
Prior to this CL, you would get an error message that SPD_SOURCES is
not set. If you fixed that, then you would get failures for
GPIO_MEM_CONFIG_0, _1, _2, and _3 not defined, and/or gpio_table[]
and early_gpio_table[] not defined. After the CL, the build proceeds.
Change-Id: I0f48d6bb9544cad6d419d3a6fbb17f57200938b2
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36408
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To get a better idea what this code does, this patch adds
a new method called 'print_system_info'.
Change-Id: I16f1c9cdc402b1a816fac65d1490432e39c07baf
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36315
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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- honor $JOBS in build_IASL
- Build the following utilities in addition to iasl for easier debugging of
ACPI issues:
* acpibin
* acpidump
* acpiexec
* acpihelp
* acpinames
* acpisrc
* acpixtract
Change-Id: I84476da8f9a5ba4860ba4ad0220ec3efb229cc03
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36337
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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New changes in the latest binutils 2.32 lead to assembler errors causes
ipxe build failure. IPXE uses the divide test which requires /dev/null as
input as well as the output file name.
This patch facilitates the /dev/null as an exception to the current
changes in binutils package while building crossgcc for coreboot leads to
successful build of ipxe and further tests to pass based on /dev/null and
applies automatically during the crossgcc rebuild.
Also, this can be reverted once binutils/ipxe provides an updated release
in this respect.
Fixes: https://ticket.coreboot.org/issues/204
Change-Id: I9f664829b8c42420c0b2ab1f2316150f86ac0b1a
Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35098
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adds the MSR table for server family 6 model 85 (5065x) processors (Sky
Lake, Cascade Lake, Cooper Lake).
The cores number for these processors exceeds the limit of 8 cores
(it is hardcoded in cpu.c). For this reason, the patch also adds code
that determines the number of processor cores at run time.
These changes are in accordance with the documentation:
[*] pages: 2-265 ... 2-286, 2-297 ... 2-308.
Intel(R) 64 and IA-32 Architectures, Software Developer’s Manual,
Volume 4: Model-Specific Registers. May 2019.
Order Number: 335592-070US
Change-Id: I27a4f5c38a7317bc3e0ead4349dccfef1338a7f2
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <anpetrov@fb.com>
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Change-Id: Idf29275575ca7965a0df98dbc8f2b27ab9c5ec4d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Increase the number of potential APCB images to 5 by adding to the
amd_bios_table. New instance IDs are from 0 to 4. The backup APCB
block (type 0x68) still supports only instance ID 0.
Change-Id: Ib70dc6417fecf94549a0c7df36ea42f63331be26
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Ibc3e4c197f99f99007cb208cf6cc4ae6f56be70c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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* Mark files in CBFS as IBB (Initial BootBlock)
* Will be used to identify the IBB by any TEE
Change-Id: Idb4857c894b9ee1edc464c0a1216cdda29937bbd
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Previously if .xcompile was missing, abuild would silently ignore the
error. With https://review.coreboot.org/c/coreboot/+/34241 we now check
the return code so abuild started failing.
We should generate the .xcompile if it doesn't exist. The Makefile will
handle that so we include it as the first Makefile.
We then need to override the default target so we don't use the one from
the Makefile.
BUG=b:112267918
TEST=ran abuild and made sure it generated a .xcompile in the root.
Change-Id: I79ded36d47b0219d0b126adff80a57be1c2bdf07
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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