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2020-02-17treewide: capitalize 'BIOS'Elyes HAOUAS
Also replace 'BIOS' by coreboot when the image is 'coreboot.rom'. Change-Id: I8303b7baa9671f19a036a59775026ffd63c85273 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-17util/autoport: Fix typoAngel Pons
Also reflow the paragraph in which the typo was hiding a bit. Change-Id: I2fea01fe23af21c2540fa90154ce29af3e74776b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
2020-02-17util: Fix typosElyes HAOUAS
Change-Id: Ia405384211aa53ac089a99ecd31acc25effdb71e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-17util/k8resdump: Remove utilArthur Heymans
AMD K8 support was dropped. Change-Id: I94c38e588c0ebdc6b9e830067c935814a5d26b0a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-17autoport: Remove space in example codePaul Menzel
The coreboot coding style does not insert a space between the function and argument list. Change-Id: I740f6c7f513e4f2715c793f61c9d9835c55c9dce Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-17util/docker: Use more stable URLPatrick Georgi
The pgeorgi namespace is my own and things could change without notice there. To overcome this issue, encapsulate is now maintained on review.coreboot.org/encapsulate.git and mirrored over to github, so let's use that. Change-Id: I12e43f61f693a6b0392b84dd56ede665a1a2129a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38899 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-12crossgcc: Upgrade IASL to version 20200110Elyes HAOUAS
Changes: 20200110: https://acpica.org/node/176 20191213: https://acpica.org/node/175 20191018: https://acpica.org/node/174 20190816: https://acpica.org/node/172 Change-Id: Ifaa0d1c79802872c1a822c1108d2a50bc60c8fd8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38347 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-09util/mainboard/google: add support for ZorkPaul Fagerburg
Update the create_coreboot_variant.sh and kconfig.py to support the zork baseboard. Full template files will be added in a later CL. BUG=b:148161697, b:148281637 BRANCH=None TEST=`./create_coreboot_variant.sh zork dalboz` and verify that the changes staged are correct. Signed-off-by: Paul Fagerburg <pfagerburg@google.com> Change-Id: Ie0a29bb9f4bb8f3bb7eaeae8799cef861c395e7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/38559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-02-09trogdor: update python scripts for python3T Michael Turney
Change-Id: I46525243729c1dbcd30b346d4603452eea14ad9d Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-02-09util/ifdtool: Support modification of single Flash DescriptorMarcello Sylvester Bauer
Add the capability to update the Flash Descriptor directly instead of raising a Segmentation Fault. In this way it will be possible to add a Kconfig options to modify the ifd descriptor at build-time. Change-Id: Id3db09291af2bd2e759c283e316afd5da1fb4ca7 Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-02-08Add configurable ramstage support for minimal PCI scanningRonald G. Minnich
This CL has changes that allow us to enable a configurable ramstage, and one change that allows us to minimize PCI scanning. Minimal scanning is a frequently requested feature. To enable it, we add two new variables to src/Kconfig CONFIGURABLE_RAMSTAGE is the overall variable controlling other options for minimizing the ramstage. MINIMAL_PCI_SCANNING is how we indicate we wish to enable minimal PCI scanning. Some devices must be scanned in all cases, such as 0:0.0. To indicate which devices we must scan, we add a new mandatory keyword to sconfig It is used in place of on, off, or hidden, and indicates a device is enabled and mandatory. Mandatory devices are always scanned. When MINIMAL_PCI_SCANNING is enabled, ONLY mandatory devices are scanned. We further add support in src/device/pci_device.c to manage both MINIMAL_PCI_SCANNING and mandatory devices. Finally, to show how this works in practice, we add mandatory keywords to 3 devices on the qemu-q35. TEST= 1. This is tested and working on the qemu-q35 target. 2. On CML-Hatch Before CL: Total Boot time: ~685ms After CL: Total Boot time: ~615ms Change-Id: I2073d9f8e9297c2b02530821ebb634ea2a5c758e Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2020-02-07trogdor: support mbn_version 6 with python build scriptsT Michael Turney
Developer/Reviewer, be aware of this patch from Mistral: https://review.coreboot.org/c/coreboot/+/33425/18 Change-Id: I020d1e4d4f5c948948e1b39dd18af1d0e860c279 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-02-07util/docker/coreboot-sdk: Add packages required to build LinuxBootWim Vervoorn
Add golang and libelf-dev so LinuxBoot can be built from the coreboot-sdk docker container. BUG=N/A TEST=build Change-Id: I7a156fc24a6040d73467e06c16139bf298a29740 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38751 Tested-by: Martin Roth <martinroth@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2020-02-06trogdor: Add T32 scripts for full boot chainashk
Change-Id: I4ec1d4f722523f240fa293dd79235ab4e32e4489 Signed-off-by: Ashwin Kumar <ashk@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-02-03xcompile: Disable null pointer optimizationsJacob Garber
According to the C standard, accessing the NULL pointer (memory at address zero) is undefined behaviour, and so GCC is allowed to optimize it out. Of course, accessing this memory location is sometimes necessary, so this optimization can be disabled using -fno-delete-null-pointer-checks. This is already done in coreboot, but adding it to xcompile will also disable it for all the payloads. For example, coreinfo compiled with LTO libpayload crashes when this flag isn't set, presumably because the compiler is optimizing something out that it shouldn't. Change-Id: I4492277f02418ade3fe7a75304e8e0611f49ef36 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38289 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-01util/inteltool: Add GPIO dumping capabilites for Ice Lake U systemsJohanna Schander
This GPIO dumping was implemented using the Document Number: 341080-001 Intel® 495 Series Chipset Family On-Package Platform Controller Hub Volume 1 of 2 datasheet. The GPIO community ports can be found in table 36-1, while the community and pin descriptions are taken from linux/pinctrl/intel/pinctrl-icelake.c . This commit was tested on the late 2019 Razer Blade Stealth with 1065G7 and Chipset 495 PCH and the output manually compared against linux/pinctrl-intel. Change-Id: Ib40f1dbae57169678e92ea9ad0df60ff91b5b22c Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2020-02-01util/cbfstool/lzma: Make clang-11+'s indentation checker happyPatrick Georgi
Newest clang compilers warn about "misleading indentation", and because warnings-are-errors in our builds, that breaks the build. The lzma code base is vendored in, so we might just have to update it, but that's a bigger effort than just removing a couple of spaces (the coding style of the file is horrible, but I will only change it as much as the compilers ask for). BUG=chromium:1039526 Change-Id: I6b9d7a760380081af996ea5412d7e3e688048bfd Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-01util/docker/Makefile: Correct help outputWim Vervoorn
The help output suggests clean-docker should be used to remove the docker coreboot containers and images. The Makefile actually supports the docker-clean target. Corrected the help output to reflect the actual Makefile target. BUG=N/A TEST=build Change-Id: Ib24f8e1ecdf3bdc31b3f8b484ce7ca0c19b645ee Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-31cbfstool: Set deprecated _BSD_SOURCE and _SVID_SOURCE macrosJulius Werner
In glibc feature control macros, _DEFAULT_SOURCE is the shorthand to tell glibc to enable "all the default stuff", meaning POSIX, BSD and System V interfaces. However, this macro is somewhat recent and older glibc versions (e.g. 2.12) are still occasionally in use that don't recognize it yet. For the benefits of users with these versions, let's also enable the deprecated _BSD_SOURCE and _SVID_SOURCE macros which essentially achieve the same thing. We must continue to define _DEFAULT_SOURCE so that newer glibc versions don't throw a deprecation warning. This patch should make BSD-style byteswap macros like le32toh() available on these older glibc versions. Change-Id: I019bbcf738a1bcdccd7b299bdde29cd4d4ded134 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-01-30util/lint: enforce SPDX license headers in src/superioFelix Held
Change-Id: Iae8d4f0470f75b47e53c50790f06902acb9a24cc Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-01-30util/*: more typo fixesPatrick Georgi
Found by: util/lint/checkpatch.pl --types TYPO_SPELLING --fix-inplace --strict --terse -f $(find util -name '*.[ch]') Change-Id: I059071fd3a2edb41c72fc57fccbb520bd2ebb757 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-01-30util/msrtool: Fix formatting issues reported by checkpatchPatrick Georgi
Change-Id: I487a9e6a6416bbe874ddadeaf464f54c02cacb0a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38635 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-30util/msrtool: Fix typosPatrick Georgi
The Intel docs also call it "Scalable Bus Speed", so the typo is on us. Found by: util/lint/checkpatch.pl --types TYPO_SPELLING --fix-inplace --strict --terse -f util/msrtool/*.c Change-Id: I84bdba687060e695d29420b9dd8eeb5f4ec44610 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38634 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-30util/cbfstool: Fix typosPatrick Georgi
Found by: util/lint/checkpatch.pl --types TYPO_SPELLING --fix-inplace --strict --terse -f util/cbfstool/*.c Change-Id: I13a27407bf2bad4b9fadcec8cdbd5889068f13cf Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38633 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-30util/lint: Update spelling.txt from lintian data setPatrick Georgi
commit 1191c09201b43aab55333a70d056d0c355abe329 at https://salsa.debian.org/agx/lintian/tree/master/data/spelling provides a much more comprehensive collection of misspellings, so merge it in. While at it, also sort the file for future easier merging which is the main reason that some lines appear to be removed: they're merely moved. For sorting, I adapted their make rule: make -f - sort-spelling.txt <<'EOF' .RECIPEPREFIX=% sort-%: % %csplit --prefix $<- $< '/^$$/' %LC_ALL=en_US sort -u $<-01 | cat $<-00 - > $< %rm -f $<-0[01] EOF Change-Id: I939e3a8820c88d0e639bd29b46a86b72bce1a098 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38632 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-28autoport: Don't add useless whitespace in commentsPeter Lemenkov
Change-Id: Ie6c94c0627743f9e965347ecfd28f1b0441178ad Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38516 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-28commonlib: Add commonlib/bsdJulius Werner
This patch creates a new commonlib/bsd subdirectory with a similar purpose to the existing commonlib, with the difference that all files under this subdirectory shall be licensed under the BSD-3-Clause license (or compatible permissive license). The goal is to allow more code to be shared with libpayload in the future. Initially, I'm going to move a few files there that have already been BSD-licensed in the existing commonlib. I am also exracting most contents of the often-needed <commonlib/helpers.h> as long as they have either been written by me (and are hereby relicensed) or have an existing equivalent in BSD-licensed libpayload code. I am also relicensing <commonlib/compression.h> (written by me) and <commonlib/compiler.h> (same stuff exists in libpayload). Finally, I am extracting the cb_err error code definitions from <types.h> into a new BSD-licensed header so that future commonlib/bsd code can build upon a common set of error values. I am making the assumption here that the enum constants and the half-sentence fragments of documentation next to them by themselves do not meet the threshold of copyrightability. Change-Id: I316cea70930f131e8e93d4218542ddb5ae4b63a2 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-01-22superiotool: add IT8772F register dumpAngel Pons
Values as per "IT8772E Preliminary Specification V0.4 (For F Version)". Some values are unclear on this document, but is the only one I have. Change-Id: I6d74984f453c47d6ec71963a7dcab961a22a5964 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-20util/amdfwtool: guard typedef aliasesIdwer Vollering
Build tested on Ubuntu 18 LTS, FreeBSD. Change-Id: Ida2c1f36aba7469d69dbb12ee6afce4a181bd6b7 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-01-20util/cbmem: simplify include lines in MakefileIdwer Vollering
Change-Id: I3d0ab7dacb5facb7dd14dd471cd0fb9f06bf0e37 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-01-20util/nvramtool: Create nvramtool object directories earlierPatrick Georgi
The existing rule created a potential race condition between creating the directory and putting files in there, so use our existing infrastructure for directory creation instead. Change-Id: If52a9f558c7d9ce85f71ba53232594699c9d357a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37798 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jett Rink <jettrink@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-20util/ifdtool: Correct region resize handlingWim Vervoorn
When regions are resized they are always aligned to the top of the region. For the BIOS region this is correct. The other regions however should be aligned to the bottom of the region. Update the region handling to only align BIOS region to top of region. BUG=N/A TEST=verified image resize Change-Id: Ied0e763b5335f5f124fc00de38e5db1a4d0f6785 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38460 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-16autoport: Improve formatting of EC ASL codePaul Menzel
Change-Id: I7fe3e798346e760eebb357f20e55ee1a71a1e31a Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-15autoport: Use HTTPS URLsPaul Menzel
Update the two flashrom URLs to use HTTPS. All other URLs are already using HTTPS. Change-Id: I8e9861b2748289522ab418960a463ae55ab0d2d3 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-14crossgcc: Upgrade cmake to version 3.16.2Elyes HAOUAS
Change-Id: I2012f0adcb348a3ea6c50c361a49a0a600d3db3d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-01-14util/crossgcc: Add comment on IASL versionElyes HAOUAS
Change-Id: I81c6f4134610bcd35e173cdb002ef821788b0538 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-01-14autoport: Add Xeon E3-1200 v2 memory controller IDJonathan A. Kollasch
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Change-Id: Ic5f18669a04397f570d49c1ff056cd90b3eb04a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-01-13util/lint: Enforce SPDX licenses only in src/acpi directoryMartin Roth
Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I9241f96eed652c8ca72d4f4a94f860a875e55680 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-01-10util/inteltool: Add MCHBAR dumping support for Ice Lake U systemsJohanna Schander
According to intels datasheet Document Number: 341078-001 10th Generation Intel® Core™ Processor Families Volume 2 of 2 we can dump the ICL MCHBAR similiar as on 8th / 9th gen CPUs. The difference is that on ICL the MCHBAR address is definited by the bits 38:16 instead of 38:15 giving the constraint that it has to be 64kbit instead of 32kbit aligned. (Section 3.1.13) Change-Id: Ia597a4b3738c11cb48ce5808d8459b4a2a768077 Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-01-08Make: Add supermicro/smcbiosinfo to toolsPatrick Rudolph
Build the smcbiosinfo tool with other tools. Fixes possible race condition on jenkins. Change-Id: I38f7ee2fdef2818ad685b3de53ad74f7da50600f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: ron minnich <rminnich@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-08util/autoport: correct build errors of produced filesAngel Pons
Change-Id: I8d1a6af6f1d70268f17692bee130c08502082c97 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-06util/amdfwtool: Add instances for APCB backupMarshall Dawson
Match each of the possible APCB items with a corresponding backup APCB. A missing backup copy can prevent the system from booting. Change-Id: I400194b2763239896214ea42cfe6fbeb8ed261a8 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-01-06util/supermicro: Add and use new tool smcbiosinfoPatrick Rudolph
The BMC and tools interacting with it depend on metadata placed inside the ROM in order the flash the BIOS. Add a new tool smcbiosinfo, integrate it into the build system, and generate a 128byte metadata file called smcbiosinfo.bin on build. You need to provide the BoardID for every SMC mainboard through a new Kconfig symbol: SUPERMICRO_BOARDID Some fields are unknown, but it's sufficient to flash it using SMC vendor tools. Tested on Supermicro X11SSH: * Flashing using the WebUI works * Flashing using SMCIPMITool works No further validation is done on the firmware. Change-Id: Id608c2ce78614b45a2fd0b26d97d666f02223998 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-05abuild: Allow proper build tests with USE_AMD_BLOBS=yNico Huber
Properly build test AMD ports that rely on blobs, too. Change-Id: Ia82f38d0e57f463ee33844c7afebb9dd602cef05 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-01-02util/lint: Update license header text for SPDX headers.Martin Roth
In preparation to update to SPDX license headers, add identifiers for the licenses seen in the coreboot project and create a command line parameter allowing only SPDX license identifiers to be detected. Here are example locations of these licenses: Apache-2.0 - src/soc/sifive BSD-3-Clause - Throughout coreboot & libpayload source GPL-2.0-only - Throughout coreboot source GPL-2.0-or-later - Throughout coreboot source GPL-3.0-only - util/amdtools GPL-3.0-or-later - src/lib/[gcov/libgcov/gnat] ISC - src/lib/ubsan.c, soc/qualcomm/ipq806x/include/soc/gsbi.h, others MIT - soc/nvidia/tegra210/mipi_dsi.c, files in mainboard/cavium/ X11 - include/device/drm_dp_helper.h, drivers/aspeed/common/ast_tables.h Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I07a7ca408ac8563e03e189d05ef7729dfb6fc24e Reviewed-on: https://review.coreboot.org/c/coreboot/+/36175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-12-29util/inteltool: Add chip detection for IceLake chipsJohanna Schander
Change-Id: Ia4752391e1232ac67d8927778a3a94eec5c68410 Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37986 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Christoph Pomaska <github@aufmachen.jetzt> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-28util/testing: Remove romcc from testingPatrick Georgi
Change-Id: If90193dc7c85133b10082c68a6cec6c1b0b35ffb Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37958 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-27util/docker/coreboot-sdk: Add libcurl4 requirements for em100Martin Roth
Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ia1cd7e12f12cb6d26a10fd358a3b32c31ce1c834 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-12-27util/mainboard/google: add support for VolteerPaul Fagerburg
create_coreboot_variant.sh now supports the Volteer baseboard in addition to Hatch. The shell script and supporting python code are moved up one level, while retaining the ${BASE}/template/* file structure for each supported baseboard. kconfig.py has to add slightly different text to Kconfig.name depending on which baseboard is selected. BRANCH=None BUG=b:146646594 TEST=Create variants of Hatch and Volteer, check that the staged commits are correct. $ ./create_coreboot_variant.sh hatch sushi b:12345 src/mainboard/google/hatch/Kconfig and Kconfig.name will have new sections for SUSHI. src/mainboard/google/hatch/variants/sushi will have a copy of util/mainboard/google/hatch/template $ ./create_coreboot_variant.sh volteer ripto b:12345 src/mainboard/google/volteer/Kconfig and Kconfig.name will have new sections for RIPTO. src/mainboard/google/volteer/variants/ripto will have a copy of util/mainboard/google/volteer/template Also run the script with an existing board name to verify that you can't create a variant that already exists. Change-Id: I084b6c50bb76af0d11dc86a96b3c3c434569a0dd Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Marco Chen <marcochen@google.com>
2019-12-27util/romcc: Drop romcc supportArthur Heymans
Finally all boards use a GCC compiled bootblock! Change-Id: I0c9a1b19dbdc32b43875da7d685718bae9d7f5f4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37337 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 04:49:47 +0000